Hi all,
This patch series add minimal change to provide mt7621 resets properly
defining them in the 'mediatek,mt7621-sysc' node which is the system
controller of the SoC and is already providing clocks to the rest of
the world.
There is shared architecture code for all ralink platforms in 'reset.c'
file located in 'arch/mips/ralink' but the correct thing to do to align
hardware with software seems to define and add related reset code to the
already mainlined clock driver.
After this changes, we can get rid of the useless reset controller node
in the device tree and use system controller node instead where the property
'#reset-cells' has been added. Binding documentation for this nodeq has
been updated with the new property accordly.
This series also provide a bindings include header where all related
reset bits for the MT7621 SoC are defined.
Also, please take a look to this review [0] to understand better motivation
for this series.
Regarding the way of merging this:
- I'd like patches 1 and 4 which are related going through staging tree.
- The other two (patches 2 and 3) can perfectly go through the clock tree.
Thanks in advance for your feedback.
Changes in v5:
- Move platform driver init process into 'arch_initcall' to be sure the
rest of the world can get the resets available when needed (since PCIe
controller driver has been moved from staging into 'drivers/pci/controller'
is probed earlier and reset was not available so it was returning
-EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
anoying' PCI first failed log trace.
Changes in v4:
- I sent wrong patch 3 accidentaly so now include the good version, sorry.
Changes in v3:
- Collect Rob's Acked-by for patches 1 and 2.
- Rebase on the top of staging-next since there were already many
changes there and PATCH 4 of the series didn't apply cleanly.
Changes in v2:
- Address review comments of Dan Carpenter [1]:
+ Avoid 'inline' in function definition.
+ Return proper error codes (-EINVAL) instead of '-1'.
+ Make use of 'devm_kzalloc' instead of 'kzalloc'.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (4):
dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
clk: ralink: make system controller node a reset provider
staging: mt7621-dts: align resets with binding documentation
.../bindings/clock/mediatek,mt7621-sysc.yaml | 12 +++
drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++-
drivers/staging/mt7621-dts/mt7621.dtsi | 25 +++---
include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++
4 files changed, 145 insertions(+), 15 deletions(-)
create mode 100644 include/dt-bindings/reset/mt7621-reset.h
--
2.33.0
Add dt binding header for resets lines in Mediatek MT7621 SoCs.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sergio Paracuellos <[email protected]>
---
include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 include/dt-bindings/reset/mt7621-reset.h
diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h
new file mode 100644
index 000000000000..7572c6b41453
--- /dev/null
+++ b/include/dt-bindings/reset/mt7621-reset.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 Sergio Paracuellos
+ * Author: Sergio Paracuellos <[email protected]>
+ */
+
+#ifndef DT_BINDING_MT7621_RESET_H
+#define DT_BINDING_MT7621_RESET_H
+
+#define MT7621_RST_SYS 0
+#define MT7621_RST_MCM 2
+#define MT7621_RST_HSDMA 5
+#define MT7621_RST_FE 6
+#define MT7621_RST_SPDIFTX 7
+#define MT7621_RST_TIMER 8
+#define MT7621_RST_INT 9
+#define MT7621_RST_MC 10
+#define MT7621_RST_PCM 11
+#define MT7621_RST_PIO 13
+#define MT7621_RST_GDMA 14
+#define MT7621_RST_NFI 15
+#define MT7621_RST_I2C 16
+#define MT7621_RST_I2S 17
+#define MT7621_RST_SPI 18
+#define MT7621_RST_UART1 19
+#define MT7621_RST_UART2 20
+#define MT7621_RST_UART3 21
+#define MT7621_RST_ETH 23
+#define MT7621_RST_PCIE0 24
+#define MT7621_RST_PCIE1 25
+#define MT7621_RST_PCIE2 26
+#define MT7621_RST_AUX_STCK 28
+#define MT7621_RST_CRYPTO 29
+#define MT7621_RST_SDXC 30
+#define MT7621_RST_PPE 31
+
+#endif /* DT_BINDING_MT7621_RESET_H */
--
2.33.0
MT7621 system controller node is already providing the clocks for the whole
system but must also serve as a reset provider. Hence, add reset controller
related code to the clock driver itself. To get resets properly ready for
the rest of the world we need to move platform driver initialization process
to 'arch_initcall'.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++++++++++++++++-
1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
index a2c045390f00..c725bf6e6e07 100644
--- a/drivers/clk/ralink/clk-mt7621.c
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -11,14 +11,17 @@
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <dt-bindings/clock/mt7621-clk.h>
+#include <dt-bindings/reset/mt7621-reset.h>
/* Configuration registers */
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
#define SYSC_REG_CLKCFG0 0x2c
#define SYSC_REG_CLKCFG1 0x30
+#define SYSC_REG_RESET_CTRL 0x34
#define SYSC_REG_CUR_CLK_STS 0x44
#define MEMC_REG_CPU_PLL 0x648
@@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node)
}
CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
+struct mt7621_rst {
+ struct reset_controller_dev rcdev;
+ struct regmap *sysc;
+};
+
+static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
+{
+ return container_of(dev, struct mt7621_rst, rcdev);
+}
+
+static int mt7621_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
+ struct regmap *sysc = data->sysc;
+
+ if (id == MT7621_RST_SYS)
+ return -EINVAL;
+
+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
+}
+
+static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
+ struct regmap *sysc = data->sysc;
+
+ if (id == MT7621_RST_SYS)
+ return -EINVAL;
+
+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
+}
+
+static int mt7621_reset_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = mt7621_assert_device(rcdev, id);
+ if (ret < 0)
+ return ret;
+
+ return mt7621_deassert_device(rcdev, id);
+}
+
+static const struct reset_control_ops reset_ops = {
+ .reset = mt7621_reset_device,
+ .assert = mt7621_assert_device,
+ .deassert = mt7621_deassert_device
+};
+
+static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
+{
+ struct mt7621_rst *rst_data;
+
+ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
+ if (!rst_data)
+ return -ENOMEM;
+
+ rst_data->sysc = sysc;
+ rst_data->rcdev.ops = &reset_ops;
+ rst_data->rcdev.owner = THIS_MODULE;
+ rst_data->rcdev.nr_resets = 32;
+ rst_data->rcdev.of_reset_n_cells = 1;
+ rst_data->rcdev.of_node = dev_of_node(dev);
+
+ return devm_reset_controller_register(dev, &rst_data->rcdev);
+}
+
static int mt7621_clk_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev)
return ret;
}
+ ret = mt7621_reset_init(dev, priv->sysc);
+ if (ret) {
+ dev_err(dev, "Could not init reset controller\n");
+ return ret;
+ }
+
count = ARRAY_SIZE(mt7621_clks_base) +
ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
@@ -485,4 +564,9 @@ static struct platform_driver mt7621_clk_driver = {
.of_match_table = mt7621_clk_of_match,
},
};
-builtin_platform_driver(mt7621_clk_driver);
+
+static int __init mt7621_clk_reset_init(void)
+{
+ return platform_driver_register(&mt7621_clk_driver);
+}
+arch_initcall(mt7621_clk_reset_init);
--
2.33.0
Hi Stephen,
On Sun, Nov 7, 2021 at 8:42 AM Sergio Paracuellos
<[email protected]> wrote:
>
> Hi all,
>
> This patch series add minimal change to provide mt7621 resets properly
> defining them in the 'mediatek,mt7621-sysc' node which is the system
> controller of the SoC and is already providing clocks to the rest of
> the world.
>
> There is shared architecture code for all ralink platforms in 'reset.c'
> file located in 'arch/mips/ralink' but the correct thing to do to align
> hardware with software seems to define and add related reset code to the
> already mainlined clock driver.
>
> After this changes, we can get rid of the useless reset controller node
> in the device tree and use system controller node instead where the property
> '#reset-cells' has been added. Binding documentation for this nodeq has
> been updated with the new property accordly.
>
> This series also provide a bindings include header where all related
> reset bits for the MT7621 SoC are defined.
>
> Also, please take a look to this review [0] to understand better motivation
> for this series.
>
> Regarding the way of merging this:
> - I'd like patches 1 and 4 which are related going through staging tree.
> - The other two (patches 2 and 3) can perfectly go through the clock tree.
>
> Thanks in advance for your feedback.
>
> Changes in v5:
> - Move platform driver init process into 'arch_initcall' to be sure the
> rest of the world can get the resets available when needed (since PCIe
> controller driver has been moved from staging into 'drivers/pci/controller'
> is probed earlier and reset was not available so it was returning
> -EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
> anoying' PCI first failed log trace.
Gentle ping on this series.
Thanks,
Sergio Paracuellos
>
> Changes in v4:
> - I sent wrong patch 3 accidentaly so now include the good version, sorry.
>
> Changes in v3:
> - Collect Rob's Acked-by for patches 1 and 2.
> - Rebase on the top of staging-next since there were already many
> changes there and PATCH 4 of the series didn't apply cleanly.
>
> Changes in v2:
> - Address review comments of Dan Carpenter [1]:
> + Avoid 'inline' in function definition.
> + Return proper error codes (-EINVAL) instead of '-1'.
> + Make use of 'devm_kzalloc' instead of 'kzalloc'.
>
> Best regards,
> Sergio Paracuellos
>
> Sergio Paracuellos (4):
> dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
> dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
> clk: ralink: make system controller node a reset provider
> staging: mt7621-dts: align resets with binding documentation
>
> .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 +++
> drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++-
> drivers/staging/mt7621-dts/mt7621.dtsi | 25 +++---
> include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++
> 4 files changed, 145 insertions(+), 15 deletions(-)
> create mode 100644 include/dt-bindings/reset/mt7621-reset.h
>
> --
> 2.33.0
>
Quoting Sergio Paracuellos (2021-12-13 04:00:17)
> Hi Stephen,
>
> On Sun, Nov 7, 2021 at 8:42 AM Sergio Paracuellos
> <[email protected]> wrote:
> >
> > Hi all,
> >
> > This patch series add minimal change to provide mt7621 resets properly
> > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > controller of the SoC and is already providing clocks to the rest of
> > the world.
> >
> > There is shared architecture code for all ralink platforms in 'reset.c'
> > file located in 'arch/mips/ralink' but the correct thing to do to align
> > hardware with software seems to define and add related reset code to the
> > already mainlined clock driver.
> >
> > After this changes, we can get rid of the useless reset controller node
> > in the device tree and use system controller node instead where the property
> > '#reset-cells' has been added. Binding documentation for this nodeq has
> > been updated with the new property accordly.
> >
> > This series also provide a bindings include header where all related
> > reset bits for the MT7621 SoC are defined.
> >
> > Also, please take a look to this review [0] to understand better motivation
Is [0] a link?
> > for this series.
> >
> > Regarding the way of merging this:
> > - I'd like patches 1 and 4 which are related going through staging tree.
> > - The other two (patches 2 and 3) can perfectly go through the clock tree.
> >
> > Thanks in advance for your feedback.
> >
> > Changes in v5:
> > - Move platform driver init process into 'arch_initcall' to be sure the
> > rest of the world can get the resets available when needed (since PCIe
> > controller driver has been moved from staging into 'drivers/pci/controller'
> > is probed earlier and reset was not available so it was returning
> > -EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
> > anoying' PCI first failed log trace.
>
> Gentle ping on this series.
>
It looks to largely be a reset controller patch series. Can you get
review from the reset maintainer?
RESET CONTROLLER FRAMEWORK
M: Philipp Zabel <[email protected]>
S: Maintained
Hi Stephen,
On Fri, Jan 7, 2022 at 3:10 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2021-12-13 04:00:17)
> > Hi Stephen,
> >
> > On Sun, Nov 7, 2021 at 8:42 AM Sergio Paracuellos
> > <[email protected]> wrote:
> > >
> > > Hi all,
> > >
> > > This patch series add minimal change to provide mt7621 resets properly
> > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > controller of the SoC and is already providing clocks to the rest of
> > > the world.
> > >
> > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > hardware with software seems to define and add related reset code to the
> > > already mainlined clock driver.
> > >
> > > After this changes, we can get rid of the useless reset controller node
> > > in the device tree and use system controller node instead where the property
> > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > been updated with the new property accordly.
> > >
> > > This series also provide a bindings include header where all related
> > > reset bits for the MT7621 SoC are defined.
> > >
> > > Also, please take a look to this review [0] to understand better motivation
>
> Is [0] a link?
Yes, sorry it was not included:
[0]: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/
>
> > > for this series.
> > >
> > > Regarding the way of merging this:
> > > - I'd like patches 1 and 4 which are related going through staging tree.
> > > - The other two (patches 2 and 3) can perfectly go through the clock tree.
> > >
> > > Thanks in advance for your feedback.
> > >
> > > Changes in v5:
> > > - Move platform driver init process into 'arch_initcall' to be sure the
> > > rest of the world can get the resets available when needed (since PCIe
> > > controller driver has been moved from staging into 'drivers/pci/controller'
> > > is probed earlier and reset was not available so it was returning
> > > -EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
> > > anoying' PCI first failed log trace.
> >
> > Gentle ping on this series.
> >
>
> It looks to largely be a reset controller patch series. Can you get
> review from the reset maintainer?
>
> RESET CONTROLLER FRAMEWORK
> M: Philipp Zabel <[email protected]>
> S: Maintained
Ok, I'll rebase and resend the series including Philipp Zabel for
reviewing this.
Thanks,
Sergio Paracuellos