Existing genphy_loopback() is not applicable for Marvell PHY. Besides
configuring bit-6 and bit-13 in Page 0 Register 0 (Copper Control
Register), it is also required to configure same bits in Page 2
Register 21 (MAC Specific Control Register 2) according to speed of
the loopback is operating.
Tested working on Marvell88E1510 PHY for all speeds (1000/100/10Mbps).
FIXME: Based on trial and error test, it seem 1G need to have delay between
soft reset and loopback enablement.
Fixes: 014068dcb5b1 ("net: phy: genphy_loopback: add link speed configuration")
Cc: <[email protected]> # 5.15.x
Signed-off-by: Mohammad Athari Bin Ismail <[email protected]>
---
v2 changelog:
- For loopback enabled, add bit-6 and bit-13 configuration in both Page
0 Register 0 and Page 2 Register 21. Commented by Heiner Kallweit
<[email protected]>.
- For loopback disabled, follow genphy_loopback() implementation.
---
drivers/net/phy/marvell.c | 46 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4fcfca4e1702..51ca2cc05e10 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -189,6 +189,8 @@
#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
+#define MII_88E1510_MSCR_2 0x15
+
#define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
#define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
#define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
@@ -1932,6 +1934,48 @@ static void marvell_get_stats(struct phy_device *phydev,
data[i] = marvell_get_stat(phydev, i);
}
+static int marvell_loopback(struct phy_device *phydev, bool enable)
+{
+ if (enable) {
+ u16 bmcr_ctl = 0, mscr2_ctl = 0;
+
+ if (phydev->speed == SPEED_1000)
+ bmcr_ctl = BMCR_SPEED1000;
+ else if (phydev->speed == SPEED_100)
+ bmcr_ctl = BMCR_SPEED100;
+
+ if (phydev->duplex == DUPLEX_FULL)
+ bmcr_ctl |= BMCR_FULLDPLX;
+
+ phy_modify(phydev, MII_BMCR, ~0, bmcr_ctl);
+
+ if (phydev->speed == SPEED_1000)
+ mscr2_ctl = BMCR_SPEED1000;
+ else if (phydev->speed == SPEED_100)
+ mscr2_ctl = BMCR_SPEED100;
+
+ phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
+ MII_88E1510_MSCR_2, BMCR_SPEED1000 |
+ BMCR_SPEED100, mscr2_ctl);
+
+ /* Need soft reset to have speed configuration takes effect */
+ genphy_soft_reset(phydev);
+
+ /* FIXME: Based on trial and error test, it seem 1G need to have
+ * delay between soft reset and loopback enablement.
+ */
+ if (phydev->speed == SPEED_1000)
+ msleep(1000);
+
+ return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
+ BMCR_LOOPBACK);
+ } else {
+ phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
+
+ return phy_config_aneg(phydev);
+ }
+}
+
static int marvell_vct5_wait_complete(struct phy_device *phydev)
{
int i;
@@ -3078,7 +3122,7 @@ static struct phy_driver marvell_drivers[] = {
.get_sset_count = marvell_get_sset_count,
.get_strings = marvell_get_strings,
.get_stats = marvell_get_stats,
- .set_loopback = genphy_loopback,
+ .set_loopback = marvell_loopback,
.get_tunable = m88e1011_get_tunable,
.set_tunable = m88e1011_set_tunable,
.cable_test_start = marvell_vct7_cable_test_start,
--
2.17.1
On Wed, Jan 12, 2022 at 05:33:44PM +0800, Mohammad Athari Bin Ismail wrote:
> +static int marvell_loopback(struct phy_device *phydev, bool enable)
> +{
> + if (enable) {
> + u16 bmcr_ctl = 0, mscr2_ctl = 0;
> +
> + if (phydev->speed == SPEED_1000)
> + bmcr_ctl = BMCR_SPEED1000;
> + else if (phydev->speed == SPEED_100)
> + bmcr_ctl = BMCR_SPEED100;
> +
> + if (phydev->duplex == DUPLEX_FULL)
> + bmcr_ctl |= BMCR_FULLDPLX;
> +
> + phy_modify(phydev, MII_BMCR, ~0, bmcr_ctl);
Is there any point in doing a read-modify-write here if you're just
setting all bits in the register? Wouldn't phy_write() be more
appropriate? What about error handing?
> +
> + if (phydev->speed == SPEED_1000)
> + mscr2_ctl = BMCR_SPEED1000;
> + else if (phydev->speed == SPEED_100)
> + mscr2_ctl = BMCR_SPEED100;
> +
> + phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
> + MII_88E1510_MSCR_2, BMCR_SPEED1000 |
> + BMCR_SPEED100, mscr2_ctl);
> +
> + /* Need soft reset to have speed configuration takes effect */
> + genphy_soft_reset(phydev);
> +
> + /* FIXME: Based on trial and error test, it seem 1G need to have
> + * delay between soft reset and loopback enablement.
> + */
> + if (phydev->speed == SPEED_1000)
> + msleep(1000);
> +
> + return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
> + BMCR_LOOPBACK);
> + } else {
> + phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
Error handling?
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
> -----Original Message-----
> From: Russell King <[email protected]>
> Sent: Wednesday, January 12, 2022 9:13 PM
> To: Ismail, Mohammad Athari <[email protected]>
> Cc: Andrew Lunn <[email protected]>; David S . Miller
> <[email protected]>; Jakub Kicinski <[email protected]>; Oleksij
> Rempel <[email protected]>; Heiner Kallweit
> <[email protected]>; [email protected]; linux-
> [email protected]; [email protected]
> Subject: Re: [PATCH net v2] net: phy: marvell: add Marvell specific PHY
> loopback
>
> On Wed, Jan 12, 2022 at 05:33:44PM +0800, Mohammad Athari Bin Ismail
> wrote:
> > +static int marvell_loopback(struct phy_device *phydev, bool enable) {
> > + if (enable) {
> > + u16 bmcr_ctl = 0, mscr2_ctl = 0;
> > +
> > + if (phydev->speed == SPEED_1000)
> > + bmcr_ctl = BMCR_SPEED1000;
> > + else if (phydev->speed == SPEED_100)
> > + bmcr_ctl = BMCR_SPEED100;
> > +
> > + if (phydev->duplex == DUPLEX_FULL)
> > + bmcr_ctl |= BMCR_FULLDPLX;
> > +
> > + phy_modify(phydev, MII_BMCR, ~0, bmcr_ctl);
>
> Is there any point in doing a read-modify-write here if you're just setting all
> bits in the register? Wouldn't phy_write() be more appropriate? What about
> error handing?
Yes, you're right. phy_write() is more suitable. And will add error handling as well.
Will include them in v3 patch.
>
> > +
> > + if (phydev->speed == SPEED_1000)
> > + mscr2_ctl = BMCR_SPEED1000;
> > + else if (phydev->speed == SPEED_100)
> > + mscr2_ctl = BMCR_SPEED100;
> > +
> > + phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
> > + MII_88E1510_MSCR_2, BMCR_SPEED1000 |
> > + BMCR_SPEED100, mscr2_ctl);
> > +
I believe this also need error handling.
> > + /* Need soft reset to have speed configuration takes effect
> */
> > + genphy_soft_reset(phydev);
Ditto.
> > +
> > + /* FIXME: Based on trial and error test, it seem 1G need to
> have
> > + * delay between soft reset and loopback enablement.
> > + */
> > + if (phydev->speed == SPEED_1000)
> > + msleep(1000);
> > +
> > + return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
> > + BMCR_LOOPBACK);
> > + } else {
> > + phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
>
> Error handling?
Will add it in v3 patch.
-Athari-
>
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!