2021-12-03 14:12:32

by Adam Wujek

Subject: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2

SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
SI5341_OUT_R_REG is set 0).
Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
interpreted as output is disabled.

Signed-off-by: Adam Wujek <[email protected]>
---
drivers/clk/clk-si5341.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index b7641abe6747..15b1c90cafe5 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -798,6 +798,15 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
u32 r_divider;
u8 r[3];

+ err = regmap_read(output->data->regmap,
+ SI5341_OUT_CONFIG(output), &val);
+ if (err < 0)
+ return err;
+
+ /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
+ if (val & SI5341_OUT_CFG_RDIV_FORCE2)
+ return parent_rate / 2;
+
err = regmap_bulk_read(output->data->regmap,
SI5341_OUT_R_REG(output), r, 3);
if (err < 0)
@@ -814,13 +823,6 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
r_divider += 1;
r_divider <<= 1;

- err = regmap_read(output->data->regmap,
- SI5341_OUT_CONFIG(output), &val);
- if (err < 0)
- return err;
-
- if (val & SI5341_OUT_CFG_RDIV_FORCE2)
- r_divider = 2;

return parent_rate / r_divider;
}
--
2.25.1

2022-01-13 21:23:15

by Stephen Boyd

Subject: Re: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2

+Robert

Please review

Quoting Adam Wujek (2021-12-03 06:12:07)
> SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
> a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
> is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
> SI5341_OUT_R_REG is set 0).
> Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
> interpreted as output is disabled.
>
> Signed-off-by: Adam Wujek <[email protected]>
> ---
> drivers/clk/clk-si5341.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
> index b7641abe6747..15b1c90cafe5 100644
> --- a/drivers/clk/clk-si5341.c
> +++ b/drivers/clk/clk-si5341.c
> @@ -798,6 +798,15 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
> u32 r_divider;
> u8 r[3];
>
> + err = regmap_read(output->data->regmap,
> + SI5341_OUT_CONFIG(output), &val);
> + if (err < 0)
> + return err;
> +
> + /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
> + if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> + return parent_rate / 2;
> +
> err = regmap_bulk_read(output->data->regmap,
> SI5341_OUT_R_REG(output), r, 3);
> if (err < 0)
> @@ -814,13 +823,6 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
> r_divider += 1;
> r_divider <<= 1;
>
> - err = regmap_read(output->data->regmap,
> - SI5341_OUT_CONFIG(output), &val);
> - if (err < 0)
> - return err;
> -
> - if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> - r_divider = 2;
>
> return parent_rate / r_divider;
> }

2022-01-13 22:29:55

by Robert Hancock

Subject: Re: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2

On Thu, 2022-01-13 at 13:23 -0800, Stephen Boyd wrote:
> +Robert
>
> Please review
>
> Quoting Adam Wujek (2021-12-03 06:12:07)
> > SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
> > a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
> > is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
> > SI5341_OUT_R_REG is set 0).
> > Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
> > interpreted as output is disabled.
> >
> > Signed-off-by: Adam Wujek <[email protected]>
> > ---
> > drivers/clk/clk-si5341.c | 16 +++++++++-------
> > 1 file changed, 9 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
> > index b7641abe6747..15b1c90cafe5 100644
> > --- a/drivers/clk/clk-si5341.c
> > +++ b/drivers/clk/clk-si5341.c
> > @@ -798,6 +798,15 @@ static unsigned long
> > si5341_output_clk_recalc_rate(struct clk_hw *hw,
> > u32 r_divider;
> > u8 r[3];
> >
> > + err = regmap_read(output->data->regmap,
> > + SI5341_OUT_CONFIG(output), &val);
> > + if (err < 0)
> > + return err;
> > +
> > + /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
> > + if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> > + return parent_rate / 2;
> > +
> > err = regmap_bulk_read(output->data->regmap,
> > SI5341_OUT_R_REG(output), r, 3);
> > if (err < 0)
> > @@ -814,13 +823,6 @@ static unsigned long
> > si5341_output_clk_recalc_rate(struct clk_hw *hw,
> > r_divider += 1;
> > r_divider <<= 1;
> >
> > - err = regmap_read(output->data->regmap,
> > - SI5341_OUT_CONFIG(output), &val);
> > - if (err < 0)
> > - return err;
> > -
> > - if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> > - r_divider = 2;
> >
> > return parent_rate / r_divider;
> > }

Looks reasonable to me. I guess this bug doesn't affect register settings that
were previously applied by this driver, as it always sets the RDIV to 1 when
setting the FORCE2 flag, but if the chip has power-up NVM configuration
generated by ClockBuilder etc. then this problem could show up.

Reviewed-by: Robert Hancock <[email protected]>

--
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
http://www.calian.com

2022-01-25 08:47:06

by Stephen Boyd

Subject: Re: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2

Quoting Adam Wujek (2021-12-03 06:12:07)
> SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
> a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
> is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
> SI5341_OUT_R_REG is set 0).
> Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
> interpreted as output is disabled.
>
> Signed-off-by: Adam Wujek <[email protected]>
> ---

Applied to clk-next