2022-03-08 08:51:33

by Heiko Stuebner

Subject: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
for things like non-cacheable pages or I/O memory pages.


So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
types) using the alternatives framework.

This includes a number of changes to the alternatives mechanism itself.
The biggest one being the move to a more central location, as I expect
in the future, nearly every chip needing some sort of patching, be it
either for erratas or for optional features (svpbmt or others).

Detection of the svpbmt functionality is done via Atish's isa extension
handling series [0] and thus does not need any dt-parsing of its own
anymore.

The series also introduces support for the memory types of the D1
which are implemented differently to svpbmt. But when patching anyway
it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
location.

The only slightly bigger difference is that the "normal" type is not 0
as with svpbmt, so kernel patches for this PMA type need to be applied
even before the MMU is brought up, so the series introduces a separate
stage for that.


In theory this series is 3 parts:
- sbi cache-flush / null-ptr
- alternatives improvements
- svpbmt+d1

So expecially patches from the first 2 areas could be applied when
deemed ready, I just thought to keep it together to show-case where
the end-goal is and not requiring jumping between different series.


I picked the recipient list from the previous versions, hopefully
I didn't forget anybody.

changes in v7:
- fix typo in patch1 (Atish)
- moved to Atish's isa-extension framework
- and therefore move regular boot-alternatives directly behind fill_hwcaps
- change T-Head errata Kconfig text (Atish)

changes in v6:
- rebase onto 5.17-rc1
- handle sbi null-ptr differently
- improve commit messages
- use riscv,mmu as property name

changes in v5:
- move to use alternatives for runtime-patching
- add D1 variant


[0] https://lore.kernel.org/r/[email protected]


Heiko Stuebner (12):
riscv: prevent null-pointer dereference with sbi_remote_fence_i
riscv: integrate alternatives better into the main architecture
riscv: allow different stages with alternatives
riscv: implement module alternatives
riscv: implement ALTERNATIVE_2 macro
riscv: extend concatenated alternatives-lines to the same length
riscv: prevent compressed instructions in alternatives
riscv: move boot alternatives to after fill_hwcap
riscv: Fix accessing pfn bits in PTEs for non-32bit variants
riscv: add cpufeature handling via alternatives
riscv: remove FIXMAP_PAGE_IO and fall back to its default value
riscv: add memory-type errata for T-Head

Wei Fu (1):
riscv: add RISC-V Svpbmt extension support

arch/riscv/Kconfig.erratas | 29 +++--
arch/riscv/Kconfig.socs | 1 -
arch/riscv/Makefile | 2 +-
arch/riscv/errata/Makefile | 2 +-
arch/riscv/errata/sifive/errata.c | 17 ++-
arch/riscv/errata/thead/Makefile | 1 +
arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
arch/riscv/include/asm/alternative.h | 16 ++-
arch/riscv/include/asm/errata_list.h | 52 +++++++++
arch/riscv/include/asm/fixmap.h | 2 -
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/pgtable-32.h | 17 +++
arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
arch/riscv/include/asm/pgtable-bits.h | 10 --
arch/riscv/include/asm/pgtable.h | 53 +++++++--
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/Makefile | 1 +
arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
arch/riscv/kernel/module.c | 29 +++++
arch/riscv/kernel/sbi.c | 10 +-
arch/riscv/kernel/setup.c | 2 +
arch/riscv/kernel/smpboot.c | 4 -
arch/riscv/kernel/traps.c | 2 +-
arch/riscv/mm/init.c | 1 +
27 files changed, 546 insertions(+), 114 deletions(-)
create mode 100644 arch/riscv/errata/thead/Makefile
create mode 100644 arch/riscv/errata/thead/errata.c
rename arch/riscv/{errata => kernel}/alternative.c (59%)

--
2.30.2

2022-03-08 09:08:01

by Heiko Stuebner

Subject: [PATCH v7 02/13] riscv: integrate alternatives better into the main architecture

Right now the alternatives need to be explicitly enabled and
erratas are limited to SiFive ones.

Over time with more SoCs and additional RiscV extensions, many more
erratas or other patch-worthy features will emerge, so it doesn't
really make sense to have the core alternatives able to get
deactivated.

So make it part of the core RiscV kernel and drop the main
RISCV_ERRATA_ALTERNATIVES config symbol.

This mimics how i.e. arm64 handles its alternatives implementation.

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/Kconfig.erratas | 10 ----------
arch/riscv/Kconfig.socs | 1 -
arch/riscv/Makefile | 2 +-
arch/riscv/errata/Makefile | 1 -
arch/riscv/include/asm/alternative-macros.h | 22 ---------------------
arch/riscv/kernel/Makefile | 1 +
arch/riscv/{errata => kernel}/alternative.c | 0
arch/riscv/kernel/smpboot.c | 2 --
arch/riscv/kernel/traps.c | 2 +-
9 files changed, 3 insertions(+), 38 deletions(-)
rename arch/riscv/{errata => kernel}/alternative.c (100%)

diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index b44d6ecdb46e..d18be8ff0245 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -1,17 +1,7 @@
menu "CPU errata selection"

-config RISCV_ERRATA_ALTERNATIVE
- bool "RISC-V alternative scheme"
- default y
- help
- This Kconfig allows the kernel to automatically patch the
- errata required by the execution platform at run time. The
- code patching is performed once in the boot stages. It means
- that the overhead from this mechanism is just taken once.
-
config ERRATA_SIFIVE
bool "SiFive errata"
- depends on RISCV_ERRATA_ALTERNATIVE
help
All SiFive errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all SiFive errata. Please say "Y"
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6ec44a22278a..3df7f7ed0d81 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -14,7 +14,6 @@ config SOC_SIFIVE
select CLK_SIFIVE
select CLK_SIFIVE_PRCI
select SIFIVE_PLIC
- select RISCV_ERRATA_ALTERNATIVE
select ERRATA_SIFIVE
help
This enables support for SiFive SoC platform hardware.
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 7d81102cffd4..a7ed47ce9311 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -103,7 +103,7 @@ endif

head-y := arch/riscv/kernel/head.o

-core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
+core-y += arch/riscv/errata/
core-$(CONFIG_KVM) += arch/riscv/kvm/

libs-y += arch/riscv/lib/
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index b8f8740a3e44..0ca1c5281a2d 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -1,2 +1 @@
-obj-y += alternative.o
obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 67406c376389..92da6b3920a3 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -2,8 +2,6 @@
#ifndef __ASM_ALTERNATIVE_MACROS_H
#define __ASM_ALTERNATIVE_MACROS_H

-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
-
#ifdef __ASSEMBLY__

.macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len
@@ -76,26 +74,6 @@

#endif /* __ASSEMBLY__ */

-#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/
-#ifdef __ASSEMBLY__
-
-.macro __ALTERNATIVE_CFG old_c
- \old_c
-.endm
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
- __ALTERNATIVE_CFG old_c
-
-#else /* !__ASSEMBLY__ */
-
-#define __ALTERNATIVE_CFG(old_c) \
- old_c "\n"
-
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
- __ALTERNATIVE_CFG(old_c)
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */
/*
* Usage:
* ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index ffc87e76b1dd..b02142517f7f 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -18,6 +18,7 @@ extra-y += head.o
extra-y += vmlinux.lds

obj-y += soc.o
+obj-y += alternative.o
obj-y += cpu.o
obj-y += cpufeature.o
obj-y += entry.o
diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c
similarity index 100%
rename from arch/riscv/errata/alternative.c
rename to arch/riscv/kernel/alternative.c
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 622f226454d5..a6d13dca1403 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running);
void __init smp_prepare_boot_cpu(void)
{
init_cpu_topology();
-#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
apply_boot_alternatives();
-#endif
}

void __init smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index fe92e119e6a3..9984c8622c3b 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code,
}
}

-#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE)
+#if defined (CONFIG_XIP_KERNEL)
#define __trap_section __section(".xip.traps")
#else
#define __trap_section
--
2.30.2

2022-03-08 10:54:20

by Heiko Stuebner

Subject: [PATCH v7 06/13] riscv: extend concatenated alternatives-lines to the same length

ALT_NEW_CONTENT already uses same-length assembler lines, so
extend this to the other elements as well.

This makes it more readable when these elements need to be extended
in the future.

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/include/asm/alternative-macros.h | 30 ++++++++++-----------
1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index baf649293288..c0fb11fad631 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -56,14 +56,14 @@
#include <asm/asm.h>
#include <linux/stringify.h>

-#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
- RISCV_PTR " " oldptr "\n" \
- RISCV_PTR " " newptr "\n" \
- REG_ASM " " vendor_id "\n" \
- REG_ASM " " newlen "\n" \
+#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
+ RISCV_PTR " " oldptr "\n" \
+ RISCV_PTR " " newptr "\n" \
+ REG_ASM " " vendor_id "\n" \
+ REG_ASM " " newlen "\n" \
".word " errata_id "\n"

-#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
".if " __stringify(enable) " == 1\n" \
".pushsection .alternative, \"a\"\n" \
ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -77,21 +77,21 @@
".org . - (889b - 888b) + (887b - 886b)\n" \
".endif\n"

-#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
+#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)

-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
+#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))

#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
- ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
+ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)

#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
--
2.30.2

2022-03-08 14:38:46

by Heiko Stuebner

Subject: [PATCH v7 12/13] riscv: remove FIXMAP_PAGE_IO and fall back to its default value

If not defined in the arch, FIXMAP_PAGE_IO defaults to PAGE_KERNEL_IO,
which we defined when adding the svpbmt implementation.

So drop the FIXMAP_PAGE_IO riscv define.

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/include/asm/fixmap.h | 2 --
1 file changed, 2 deletions(-)

diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
index 58a718573ad6..692e25e56d8e 100644
--- a/arch/riscv/include/asm/fixmap.h
+++ b/arch/riscv/include/asm/fixmap.h
@@ -44,8 +44,6 @@ enum fixed_addresses {
__end_of_fixed_addresses
};

-#define FIXMAP_PAGE_IO PAGE_KERNEL
-
#define __early_set_fixmap __set_fixmap

#define __late_set_fixmap __set_fixmap
--
2.30.2

2022-03-08 14:42:01

by Heiko Stuebner

Subject: [PATCH v7 08/13] riscv: move boot alternatives to after fill_hwcap

Move the application of boot alternatives to after the hw-capabilities
are populated. This allows to check for available extensions when
determining which alternatives to apply and also makes it actually
work if CONFIG_SMP is disabled for whatever reason.

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/kernel/setup.c | 2 ++
arch/riscv/kernel/smpboot.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 339ceb595b38..b4879c942b42 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -21,6 +21,7 @@
#include <linux/efi.h>
#include <linux/crash_dump.h>

+#include <asm/alternative.h>
#include <asm/cpu_ops.h>
#include <asm/early_ioremap.h>
#include <asm/pgtable.h>
@@ -295,6 +296,7 @@ void __init setup_arch(char **cmdline_p)
#endif

riscv_fill_hwcap();
+ apply_boot_alternatives();
}

static int __init topology_init(void)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index a6d13dca1403..f1e4948a4b52 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -32,7 +32,6 @@
#include <asm/sections.h>
#include <asm/sbi.h>
#include <asm/smp.h>
-#include <asm/alternative.h>

#include "head.h"

@@ -41,7 +40,6 @@ static DECLARE_COMPLETION(cpu_running);
void __init smp_prepare_boot_cpu(void)
{
init_cpu_topology();
- apply_boot_alternatives();
}

void __init smp_prepare_cpus(unsigned int max_cpus)
--
2.30.2

2022-03-08 17:20:02

by Heiko Stuebner

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

Hi Palmer,

Am Dienstag, 8. M?rz 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
> > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > for things like non-cacheable pages or I/O memory pages.
> >
> >
> > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > types) using the alternatives framework.
> >
> > This includes a number of changes to the alternatives mechanism itself.
> > The biggest one being the move to a more central location, as I expect
> > in the future, nearly every chip needing some sort of patching, be it
> > either for erratas or for optional features (svpbmt or others).
> >
> > Detection of the svpbmt functionality is done via Atish's isa extension
> > handling series [0] and thus does not need any dt-parsing of its own
> > anymore.
> >
> > The series also introduces support for the memory types of the D1
> > which are implemented differently to svpbmt. But when patching anyway
> > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > location.
> >
> > The only slightly bigger difference is that the "normal" type is not 0
> > as with svpbmt, so kernel patches for this PMA type need to be applied
> > even before the MMU is brought up, so the series introduces a separate
> > stage for that.
> >
> >
> > In theory this series is 3 parts:
> > - sbi cache-flush / null-ptr
>
> That first patch looks like an acceptable candidate for fixes. If
> there's a regression that manifests I'm happy to take it, but if it's
> only possible to manifest a crash with the new stuff then I'm OK just
> holding off until the merge window.

While right now only my poking around the early init via alternatives
is affected, the problem exists for everyone.

I.e. I do consider flush_icache_all() to be generic enough that we
should expect someone trying to call this in some early code-path
as well.

But any call to flush_icache_all() before sbi_init() ran will cause the
breakage that is fixed by patch1 .


So it doesn't look like any _current_ code path has that issue, but
it might be good to just pick patch1 for the next merge window
individually?



> > - alternatives improvements
> > - svpbmt+d1
> >
> > So expecially patches from the first 2 areas could be applied when
> > deemed ready, I just thought to keep it together to show-case where
> > the end-goal is and not requiring jumping between different series.
> >
> >
> > I picked the recipient list from the previous versions, hopefully
> > I didn't forget anybody.
> >
> > changes in v7:
> > - fix typo in patch1 (Atish)
> > - moved to Atish's isa-extension framework
> > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > - change T-Head errata Kconfig text (Atish)
>
> I was just poking around v6, so I have some minor comments there. None
> of those need to block merging this, but I am getting a bunch of build
> failures under allmodconfig
>
> $ make.riscv allmodconfig
> #
> # configuration written to .config
> #
> $ make.riscv mm/kasan/init.o
> SYNC include/config/auto.conf.cmd
> CALL scripts/atomic/check-atomics.sh
> CC arch/riscv/kernel/asm-offsets.s
> CALL scripts/checksyscalls.sh
> CC mm/kasan/init.o
> ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> make: *** [Makefile:1831: mm] Error 2
>
> Unfortunately my build box just blew up so I haven't had time to confim
> this still exists on v7, but nothing's jumping out as a fix. I've put
> this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
> what's going on but I'm guessing one of the macros has gone off the
> rails. I'm going to look at something else (as this one at least
> depends on Atish's patches), but LMK if you've got the time to look into
> this or if I should.

Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
series and some more series I saw on the list), so getting that into a
mergeable position would be really great :-)

"attempt to move .org backwards" seems to be the telltale sign of the
alternatives blocks not matching up in size. While I definitly didn't see
anything like this in my tests on qemu + d1, I'll try to investigate where
that comes from.


Heiko



> > changes in v6:
> > - rebase onto 5.17-rc1
> > - handle sbi null-ptr differently
> > - improve commit messages
> > - use riscv,mmu as property name
> >
> > changes in v5:
> > - move to use alternatives for runtime-patching
> > - add D1 variant
> >
> >
> > [0] https://lore.kernel.org/r/[email protected]
> >
> >
> > Heiko Stuebner (12):
> > riscv: prevent null-pointer dereference with sbi_remote_fence_i
> > riscv: integrate alternatives better into the main architecture
> > riscv: allow different stages with alternatives
> > riscv: implement module alternatives
> > riscv: implement ALTERNATIVE_2 macro
> > riscv: extend concatenated alternatives-lines to the same length
> > riscv: prevent compressed instructions in alternatives
> > riscv: move boot alternatives to after fill_hwcap
> > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> > riscv: add cpufeature handling via alternatives
> > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> > riscv: add memory-type errata for T-Head
> >
> > Wei Fu (1):
> > riscv: add RISC-V Svpbmt extension support
> >
> > arch/riscv/Kconfig.erratas | 29 +++--
> > arch/riscv/Kconfig.socs | 1 -
> > arch/riscv/Makefile | 2 +-
> > arch/riscv/errata/Makefile | 2 +-
> > arch/riscv/errata/sifive/errata.c | 17 ++-
> > arch/riscv/errata/thead/Makefile | 1 +
> > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
> > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> > arch/riscv/include/asm/alternative.h | 16 ++-
> > arch/riscv/include/asm/errata_list.h | 52 +++++++++
> > arch/riscv/include/asm/fixmap.h | 2 -
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/include/asm/pgtable-32.h | 17 +++
> > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
> > arch/riscv/include/asm/pgtable-bits.h | 10 --
> > arch/riscv/include/asm/pgtable.h | 53 +++++++--
> > arch/riscv/include/asm/vendorid_list.h | 1 +
> > arch/riscv/kernel/Makefile | 1 +
> > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
> > arch/riscv/kernel/cpu.c | 1 +
> > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
> > arch/riscv/kernel/module.c | 29 +++++
> > arch/riscv/kernel/sbi.c | 10 +-
> > arch/riscv/kernel/setup.c | 2 +
> > arch/riscv/kernel/smpboot.c | 4 -
> > arch/riscv/kernel/traps.c | 2 +-
> > arch/riscv/mm/init.c | 1 +
> > 27 files changed, 546 insertions(+), 114 deletions(-)
> > create mode 100644 arch/riscv/errata/thead/Makefile
> > create mode 100644 arch/riscv/errata/thead/errata.c
> > rename arch/riscv/{errata => kernel}/alternative.c (59%)
>

2022-03-08 21:45:05

by Heiko Stuebner

Subject: [PATCH v7 07/13] riscv: prevent compressed instructions in alternatives

Instructions are opportunistically compressed by the RISC-V assembler
when possible, but in alternatives-blocks both the old and new content
need to be the same size, so having the toolchain do somewhat random
optimizations will cause strange side-effects like
"attempt to move .org backwards" compile-time errors.

Already a simple "and" used in alternatives assembly will cause these
mismatched code sizes.

So prevent compressed instructions to be generated in alternatives-
code and use option-push and -pop to only limit this to the relevant
code blocks

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/include/asm/alternative-macros.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index c0fb11fad631..3a52884bf23d 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -19,7 +19,10 @@
.popsection
.subsection 1
888 :
+ .option push
+ .option norvc
\new_c
+ .option pop
889 :
.previous
.org . - (889b - 888b) + (887b - 886b)
@@ -29,7 +32,10 @@

.macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable
886 :
+ .option push
+ .option norvc
\old_c
+ .option pop
887 :
ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c
.endm
@@ -40,7 +46,10 @@
.macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2
886 :
+ .option push
+ .option norvc
\old_c
+ .option pop
887 :
ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1
ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
@@ -70,7 +79,10 @@
".popsection\n" \
".subsection 1\n" \
"888 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
new_c "\n" \
+ ".option pop\n" \
"889 :\n" \
".previous\n" \
".org . - (887b - 886b) + (889b - 888b)\n" \
@@ -79,7 +91,10 @@

#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
"886 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
old_c "\n" \
+ ".option pop\n" \
"887 :\n" \
ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)

@@ -89,7 +104,10 @@
#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2) \
"886 :\n" \
+ ".option push\n" \
+ ".option norvc\n" \
old_c "\n" \
+ ".option pop\n" \
"887 :\n" \
ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
--
2.30.2

2022-03-08 23:00:32

by Heiko Stuebner

Subject: [PATCH v7 01/13] riscv: prevent null-pointer dereference with sbi_remote_fence_i

The callback used inside sbi_remote_fence_i is set at sbi probe time
to the needed variant. Before that it is a NULL pointer.

Some users like the flush_icache_*() functions suggest a generic
functionality, that doesn't depend on a specific boot-stage but
uses sbi_remote_fence_i as one option to flush other cpu cores.

So they definitely shouldn't run into null-pointer dereference
issues when called "too early" during boot.

So introduce an empty function to be the standard for the __sbi_rfence
function pointer until sbi_init has run.

Users of sbi_remote_fence_i will have separate code for the local
cpu and sbi_init() is called before other cpus are brought up.
So there are no other cpus present at the time when the issue
might happen.

Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
---
arch/riscv/kernel/sbi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5a60a458c0b7 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -16,11 +16,19 @@
unsigned long sbi_spec_version __ro_after_init = SBI_SPEC_VERSION_DEFAULT;
EXPORT_SYMBOL(sbi_spec_version);

+static int __sbi_rfence_none(int fid, const struct cpumask *cpu_mask,
+ unsigned long start, unsigned long size,
+ unsigned long arg4, unsigned long arg5)
+{
+ return -EOPNOTSUPP;
+}
+
static void (*__sbi_set_timer)(uint64_t stime) __ro_after_init;
static int (*__sbi_send_ipi)(const struct cpumask *cpu_mask) __ro_after_init;
static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask,
unsigned long start, unsigned long size,
- unsigned long arg4, unsigned long arg5) __ro_after_init;
+ unsigned long arg4, unsigned long arg5)
+ __ro_after_init = __sbi_rfence_none;

struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
--
2.30.2

2022-03-09 00:23:33

by Heiko Stuebner

Subject: [PATCH v7 09/13] riscv: Fix accessing pfn bits in PTEs for non-32bit variants

On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
while on rv64 it is defined to use bits [53:10], leaving [63:54]
as reserved.

With upcoming optional extensions like svpbmt these previously
reserved bits will get used so simply right-shifting the PTE
to get the PFN won't be enough.

So introduce a _PAGE_PFN_MASK constant to mask the correct bits
for both rv32 and rv64 before shifting.

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/include/asm/pgtable-32.h | 8 ++++++++
arch/riscv/include/asm/pgtable-64.h | 14 +++++++++++---
arch/riscv/include/asm/pgtable-bits.h | 6 ------
arch/riscv/include/asm/pgtable.h | 6 +++---
4 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 5b2e79e5bfa5..e266a4fe7f43 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -7,6 +7,7 @@
#define _ASM_RISCV_PGTABLE_32_H

#include <asm-generic/pgtable-nopmd.h>
+#include <linux/bits.h>
#include <linux/const.h>

/* Size of region mapped by a page global directory */
@@ -16,4 +17,11 @@

#define MAX_POSSIBLE_PHYSMEM_BITS 34

+/*
+ * rv32 PTE format:
+ * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * PFN reserved for SW D A G U X W R V
+ */
+#define _PAGE_PFN_MASK GENMASK(31, 10)
+
#endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index bbbdd66e5e2f..9412c6157c88 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -6,6 +6,7 @@
#ifndef _ASM_RISCV_PGTABLE_64_H
#define _ASM_RISCV_PGTABLE_64_H

+#include <linux/bits.h>
#include <linux/const.h>

extern bool pgtable_l4_enabled;
@@ -48,6 +49,13 @@ typedef struct {

#define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))

+/*
+ * rv64 PTE format:
+ * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * N MT RSV PFN reserved for SW D A G U X W R V
+ */
+#define _PAGE_PFN_MASK GENMASK(53, 10)
+
static inline int pud_present(pud_t pud)
{
return (pud_val(pud) & _PAGE_PRESENT);
@@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud)

static inline pmd_t *pud_pgtable(pud_t pud)
{
- return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
+ return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}

static inline struct page *pud_page(pud_t pud)
{
- return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT);
+ return pfn_to_page((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}

#define mm_pud_folded mm_pud_folded
@@ -117,7 +125,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot)

static inline unsigned long _pmd_pfn(pmd_t pmd)
{
- return pmd_val(pmd) >> _PAGE_PFN_SHIFT;
+ return (pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
}

#define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a6b0c89824c2..e571fa954afc 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,12 +6,6 @@
#ifndef _ASM_RISCV_PGTABLE_BITS_H
#define _ASM_RISCV_PGTABLE_BITS_H

-/*
- * PTE format:
- * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * PFN reserved for SW D A G U X W R V
- */
-
#define _PAGE_ACCESSED_OFFSET 6

#define _PAGE_PRESENT (1 << 0)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index e3549e50de95..6d31489818cd 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -259,12 +259,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd)

static inline struct page *pmd_page(pmd_t pmd)
{
- return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+ return pfn_to_page((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}

static inline unsigned long pmd_page_vaddr(pmd_t pmd)
{
- return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
+ return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}

static inline pte_t pmd_pte(pmd_t pmd)
@@ -280,7 +280,7 @@ static inline pte_t pud_pte(pud_t pud)
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
- return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+ return ((pte_val(pte) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
}

#define pte_page(x) pfn_to_page(pte_pfn(x))
--
2.30.2

2022-03-09 00:41:35

by Palmer Dabbelt

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
> Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> for things like non-cacheable pages or I/O memory pages.
>
>
> So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> types) using the alternatives framework.
>
> This includes a number of changes to the alternatives mechanism itself.
> The biggest one being the move to a more central location, as I expect
> in the future, nearly every chip needing some sort of patching, be it
> either for erratas or for optional features (svpbmt or others).
>
> Detection of the svpbmt functionality is done via Atish's isa extension
> handling series [0] and thus does not need any dt-parsing of its own
> anymore.
>
> The series also introduces support for the memory types of the D1
> which are implemented differently to svpbmt. But when patching anyway
> it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> location.
>
> The only slightly bigger difference is that the "normal" type is not 0
> as with svpbmt, so kernel patches for this PMA type need to be applied
> even before the MMU is brought up, so the series introduces a separate
> stage for that.
>
>
> In theory this series is 3 parts:
> - sbi cache-flush / null-ptr

That first patch looks like an acceptable candidate for fixes. If
there's a regression that manifests I'm happy to take it, but if it's
only possible to manifest a crash with the new stuff then I'm OK just
holding off until the merge window.

> - alternatives improvements
> - svpbmt+d1
>
> So expecially patches from the first 2 areas could be applied when
> deemed ready, I just thought to keep it together to show-case where
> the end-goal is and not requiring jumping between different series.
>
>
> I picked the recipient list from the previous versions, hopefully
> I didn't forget anybody.
>
> changes in v7:
> - fix typo in patch1 (Atish)
> - moved to Atish's isa-extension framework
> - and therefore move regular boot-alternatives directly behind fill_hwcaps
> - change T-Head errata Kconfig text (Atish)

I was just poking around v6, so I have some minor comments there. None
of those need to block merging this, but I am getting a bunch of build
failures under allmodconfig

$ make.riscv allmodconfig
#
# configuration written to .config
#
$ make.riscv mm/kasan/init.o
SYNC include/config/auto.conf.cmd
CALL scripts/atomic/check-atomics.sh
CC arch/riscv/kernel/asm-offsets.s
CALL scripts/checksyscalls.sh
CC mm/kasan/init.o
./arch/riscv/include/asm/pgtable.h: Assembler messages:
./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
make: *** [Makefile:1831: mm] Error 2

Unfortunately my build box just blew up so I haven't had time to confim
this still exists on v7, but nothing's jumping out as a fix. I've put
this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
what's going on but I'm guessing one of the macros has gone off the
rails. I'm going to look at something else (as this one at least
depends on Atish's patches), but LMK if you've got the time to look into
this or if I should.

Thanks!

>
> changes in v6:
> - rebase onto 5.17-rc1
> - handle sbi null-ptr differently
> - improve commit messages
> - use riscv,mmu as property name
>
> changes in v5:
> - move to use alternatives for runtime-patching
> - add D1 variant
>
>
> [0] https://lore.kernel.org/r/[email protected]
>
>
> Heiko Stuebner (12):
> riscv: prevent null-pointer dereference with sbi_remote_fence_i
> riscv: integrate alternatives better into the main architecture
> riscv: allow different stages with alternatives
> riscv: implement module alternatives
> riscv: implement ALTERNATIVE_2 macro
> riscv: extend concatenated alternatives-lines to the same length
> riscv: prevent compressed instructions in alternatives
> riscv: move boot alternatives to after fill_hwcap
> riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> riscv: add cpufeature handling via alternatives
> riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> riscv: add memory-type errata for T-Head
>
> Wei Fu (1):
> riscv: add RISC-V Svpbmt extension support
>
> arch/riscv/Kconfig.erratas | 29 +++--
> arch/riscv/Kconfig.socs | 1 -
> arch/riscv/Makefile | 2 +-
> arch/riscv/errata/Makefile | 2 +-
> arch/riscv/errata/sifive/errata.c | 17 ++-
> arch/riscv/errata/thead/Makefile | 1 +
> arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
> arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> arch/riscv/include/asm/alternative.h | 16 ++-
> arch/riscv/include/asm/errata_list.h | 52 +++++++++
> arch/riscv/include/asm/fixmap.h | 2 -
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/pgtable-32.h | 17 +++
> arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 10 --
> arch/riscv/include/asm/pgtable.h | 53 +++++++--
> arch/riscv/include/asm/vendorid_list.h | 1 +
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
> arch/riscv/kernel/module.c | 29 +++++
> arch/riscv/kernel/sbi.c | 10 +-
> arch/riscv/kernel/setup.c | 2 +
> arch/riscv/kernel/smpboot.c | 4 -
> arch/riscv/kernel/traps.c | 2 +-
> arch/riscv/mm/init.c | 1 +
> 27 files changed, 546 insertions(+), 114 deletions(-)
> create mode 100644 arch/riscv/errata/thead/Makefile
> create mode 100644 arch/riscv/errata/thead/errata.c
> rename arch/riscv/{errata => kernel}/alternative.c (59%)

2022-03-09 01:27:10

by Heiko Stuebner

Subject: [PATCH v7 04/13] riscv: implement module alternatives

This allows alternatives to also be applied when loading modules
and follows the implementation of other architectures (e.g. arm64).

Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/errata/sifive/errata.c | 7 ++++---
arch/riscv/include/asm/alternative.h | 3 ++-
arch/riscv/kernel/alternative.c | 18 +++++++++++++----
arch/riscv/kernel/module.c | 29 ++++++++++++++++++++++++++++
4 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 4fe03ac41fd7..42457efcaaa3 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -4,6 +4,7 @@
*/

#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/string.h>
#include <linux/bug.h>
#include <asm/patch.h>
@@ -54,7 +55,7 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = {
},
};

-static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
+static u32 __init_or_module sifive_errata_probe(unsigned long archid, unsigned long impid)
{
int idx;
u32 cpu_req_errata = 0;
@@ -66,7 +67,7 @@ static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
return cpu_req_errata;
}

-static void __init warn_miss_errata(u32 miss_errata)
+static void __init_or_module warn_miss_errata(u32 miss_errata)
{
int i;

@@ -79,7 +80,7 @@ static void __init warn_miss_errata(u32 miss_errata)
pr_warn("----------------------------------------------------------------\n");
}

-void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage)
{
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 811bdd8027db..f0657b1b3174 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -18,8 +18,10 @@
#include <asm/hwcap.h>

#define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */
+#define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */

void __init apply_boot_alternatives(void);
+void apply_module_alternatives(void *start, size_t length);

struct alt_entry {
void *old_ptr; /* address of original instruciton or data */
@@ -37,6 +39,5 @@ struct errata_checkfunc_id {
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage);
-
#endif
#endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 02db62f55bac..223770b3945c 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -7,6 +7,7 @@
*/

#include <linux/init.h>
+#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/uaccess.h>
#include <asm/alternative.h>
@@ -23,7 +24,7 @@ static struct cpu_manufacturer_info_t {

static void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
- unsigned int stage) __initdata;
+ unsigned int stage) __initdata_or_module;

static inline void __init riscv_fill_cpu_mfr_info(void)
{
@@ -58,9 +59,9 @@ static void __init init_alternative(void)
* a feature detect on the boot CPU). No need to worry about other CPUs
* here.
*/
-static void __init _apply_alternatives(struct alt_entry *begin,
- struct alt_entry *end,
- unsigned int stage)
+static void __init_or_module _apply_alternatives(struct alt_entry *begin,
+ struct alt_entry *end,
+ unsigned int stage)
{
if (!vendor_patch_func)
return;
@@ -81,3 +82,12 @@ void __init apply_boot_alternatives(void)
(struct alt_entry *)__alt_end,
RISCV_ALTERNATIVES_BOOT);
}
+
+#ifdef CONFIG_MODULES
+void apply_module_alternatives(void *start, size_t length)
+{
+ _apply_alternatives((struct alt_entry *)start,
+ (struct alt_entry *)(start + length),
+ RISCV_ALTERNATIVES_MODULE);
+}
+#endif
diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
index 68a9e3d1fe16..a778abd5b8b9 100644
--- a/arch/riscv/kernel/module.c
+++ b/arch/riscv/kernel/module.c
@@ -11,6 +11,7 @@
#include <linux/vmalloc.h>
#include <linux/sizes.h>
#include <linux/pgtable.h>
+#include <asm/alternative.h>
#include <asm/sections.h>

static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
@@ -416,3 +417,31 @@ void *module_alloc(unsigned long size)
__builtin_return_address(0));
}
#endif
+
+static const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
+ const Elf_Shdr *sechdrs,
+ const char *name)
+{
+ const Elf_Shdr *s, *se;
+ const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+
+ for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
+ if (strcmp(name, secstrs + s->sh_name) == 0)
+ return s;
+ }
+
+ return NULL;
+}
+
+int module_finalize(const Elf_Ehdr *hdr,
+ const Elf_Shdr *sechdrs,
+ struct module *me)
+{
+ const Elf_Shdr *s;
+
+ s = find_section(hdr, sechdrs, ".alternative");
+ if (s)
+ apply_module_alternatives((void *)s->sh_addr, s->sh_size);
+
+ return 0;
+}
--
2.30.2

2022-03-10 07:45:23

by Heiko Stuebner

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

Am Dienstag, 8. M?rz 2022, 12:56:20 CET schrieb Heiko St?bner:
> Hi Palmer,
>
> Am Dienstag, 8. M?rz 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> > > for things like non-cacheable pages or I/O memory pages.
> > >
> > >
> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> > > types) using the alternatives framework.
> > >
> > > This includes a number of changes to the alternatives mechanism itself.
> > > The biggest one being the move to a more central location, as I expect
> > > in the future, nearly every chip needing some sort of patching, be it
> > > either for erratas or for optional features (svpbmt or others).
> > >
> > > Detection of the svpbmt functionality is done via Atish's isa extension
> > > handling series [0] and thus does not need any dt-parsing of its own
> > > anymore.
> > >
> > > The series also introduces support for the memory types of the D1
> > > which are implemented differently to svpbmt. But when patching anyway
> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> > > location.
> > >
> > > The only slightly bigger difference is that the "normal" type is not 0
> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> > > even before the MMU is brought up, so the series introduces a separate
> > > stage for that.
> > >
> > >
> > > In theory this series is 3 parts:
> > > - sbi cache-flush / null-ptr
> >
> > That first patch looks like an acceptable candidate for fixes. If
> > there's a regression that manifests I'm happy to take it, but if it's
> > only possible to manifest a crash with the new stuff then I'm OK just
> > holding off until the merge window.
>
> While right now only my poking around the early init via alternatives
> is affected, the problem exists for everyone.
>
> I.e. I do consider flush_icache_all() to be generic enough that we
> should expect someone trying to call this in some early code-path
> as well.
>
> But any call to flush_icache_all() before sbi_init() ran will cause the
> breakage that is fixed by patch1 .
>
>
> So it doesn't look like any _current_ code path has that issue, but
> it might be good to just pick patch1 for the next merge window
> individually?
>
>
>
> > > - alternatives improvements
> > > - svpbmt+d1
> > >
> > > So expecially patches from the first 2 areas could be applied when
> > > deemed ready, I just thought to keep it together to show-case where
> > > the end-goal is and not requiring jumping between different series.
> > >
> > >
> > > I picked the recipient list from the previous versions, hopefully
> > > I didn't forget anybody.
> > >
> > > changes in v7:
> > > - fix typo in patch1 (Atish)
> > > - moved to Atish's isa-extension framework
> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> > > - change T-Head errata Kconfig text (Atish)
> >
> > I was just poking around v6, so I have some minor comments there. None
> > of those need to block merging this, but I am getting a bunch of build
> > failures under allmodconfig
> >
> > $ make.riscv allmodconfig
> > #
> > # configuration written to .config
> > #
> > $ make.riscv mm/kasan/init.o
> > SYNC include/config/auto.conf.cmd
> > CALL scripts/atomic/check-atomics.sh
> > CC arch/riscv/kernel/asm-offsets.s
> > CALL scripts/checksyscalls.sh
> > CC mm/kasan/init.o
> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> > make: *** [Makefile:1831: mm] Error 2
> >
> > Unfortunately my build box just blew up so I haven't had time to confim
> > this still exists on v7, but nothing's jumping out as a fix. I've put
> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
> > what's going on but I'm guessing one of the macros has gone off the
> > rails. I'm going to look at something else (as this one at least
> > depends on Atish's patches), but LMK if you've got the time to look into
> > this or if I should.
>
> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> series and some more series I saw on the list), so getting that into a
> mergeable position would be really great :-)
>
> "attempt to move .org backwards" seems to be the telltale sign of the
> alternatives blocks not matching up in size. While I definitly didn't see
> anything like this in my tests on qemu + d1, I'll try to investigate where
> that comes from.

Hmm, looking at your branch [0] it seems that you're missing
patch7 that introduces the no-compressed-instruction thingy
for alternatives.

And missing that patch will of course cause the size issue.

The patch has made its way to the actual mailing lists [1], so I guess
it "just" somehow didn't reach your inbox due to some mail hickup?


Heiko


[0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
[1] https://lore.kernel.org/all/[email protected]/


> > > changes in v6:
> > > - rebase onto 5.17-rc1
> > > - handle sbi null-ptr differently
> > > - improve commit messages
> > > - use riscv,mmu as property name
> > >
> > > changes in v5:
> > > - move to use alternatives for runtime-patching
> > > - add D1 variant
> > >
> > >
> > > [0] https://lore.kernel.org/r/[email protected]
> > >
> > >
> > > Heiko Stuebner (12):
> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
> > > riscv: integrate alternatives better into the main architecture
> > > riscv: allow different stages with alternatives
> > > riscv: implement module alternatives
> > > riscv: implement ALTERNATIVE_2 macro
> > > riscv: extend concatenated alternatives-lines to the same length
> > > riscv: prevent compressed instructions in alternatives
> > > riscv: move boot alternatives to after fill_hwcap
> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> > > riscv: add cpufeature handling via alternatives
> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> > > riscv: add memory-type errata for T-Head
> > >
> > > Wei Fu (1):
> > > riscv: add RISC-V Svpbmt extension support
> > >
> > > arch/riscv/Kconfig.erratas | 29 +++--
> > > arch/riscv/Kconfig.socs | 1 -
> > > arch/riscv/Makefile | 2 +-
> > > arch/riscv/errata/Makefile | 2 +-
> > > arch/riscv/errata/sifive/errata.c | 17 ++-
> > > arch/riscv/errata/thead/Makefile | 1 +
> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> > > arch/riscv/include/asm/alternative.h | 16 ++-
> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
> > > arch/riscv/include/asm/fixmap.h | 2 -
> > > arch/riscv/include/asm/hwcap.h | 1 +
> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
> > > arch/riscv/include/asm/vendorid_list.h | 1 +
> > > arch/riscv/kernel/Makefile | 1 +
> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
> > > arch/riscv/kernel/cpu.c | 1 +
> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
> > > arch/riscv/kernel/module.c | 29 +++++
> > > arch/riscv/kernel/sbi.c | 10 +-
> > > arch/riscv/kernel/setup.c | 2 +
> > > arch/riscv/kernel/smpboot.c | 4 -
> > > arch/riscv/kernel/traps.c | 2 +-
> > > arch/riscv/mm/init.c | 1 +
> > > 27 files changed, 546 insertions(+), 114 deletions(-)
> > > create mode 100644 arch/riscv/errata/thead/Makefile
> > > create mode 100644 arch/riscv/errata/thead/errata.c
> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >
>
>

2022-03-18 14:28:53

by Palmer Dabbelt

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

On Wed, 09 Mar 2022 14:06:55 PST (-0800), [email protected] wrote:
> Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> Hi Palmer,
>>
>> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
>> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> > > for things like non-cacheable pages or I/O memory pages.
>> > >
>> > >
>> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> > > types) using the alternatives framework.
>> > >
>> > > This includes a number of changes to the alternatives mechanism itself.
>> > > The biggest one being the move to a more central location, as I expect
>> > > in the future, nearly every chip needing some sort of patching, be it
>> > > either for erratas or for optional features (svpbmt or others).
>> > >
>> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> > > handling series [0] and thus does not need any dt-parsing of its own
>> > > anymore.
>> > >
>> > > The series also introduces support for the memory types of the D1
>> > > which are implemented differently to svpbmt. But when patching anyway
>> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> > > location.
>> > >
>> > > The only slightly bigger difference is that the "normal" type is not 0
>> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> > > even before the MMU is brought up, so the series introduces a separate
>> > > stage for that.
>> > >
>> > >
>> > > In theory this series is 3 parts:
>> > > - sbi cache-flush / null-ptr
>> >
>> > That first patch looks like an acceptable candidate for fixes. If
>> > there's a regression that manifests I'm happy to take it, but if it's
>> > only possible to manifest a crash with the new stuff then I'm OK just
>> > holding off until the merge window.
>>
>> While right now only my poking around the early init via alternatives
>> is affected, the problem exists for everyone.
>>
>> I.e. I do consider flush_icache_all() to be generic enough that we
>> should expect someone trying to call this in some early code-path
>> as well.
>>
>> But any call to flush_icache_all() before sbi_init() ran will cause the
>> breakage that is fixed by patch1 .
>>
>>
>> So it doesn't look like any _current_ code path has that issue, but
>> it might be good to just pick patch1 for the next merge window
>> individually?
>>
>>
>>
>> > > - alternatives improvements
>> > > - svpbmt+d1
>> > >
>> > > So expecially patches from the first 2 areas could be applied when
>> > > deemed ready, I just thought to keep it together to show-case where
>> > > the end-goal is and not requiring jumping between different series.
>> > >
>> > >
>> > > I picked the recipient list from the previous versions, hopefully
>> > > I didn't forget anybody.
>> > >
>> > > changes in v7:
>> > > - fix typo in patch1 (Atish)
>> > > - moved to Atish's isa-extension framework
>> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> > > - change T-Head errata Kconfig text (Atish)
>> >
>> > I was just poking around v6, so I have some minor comments there. None
>> > of those need to block merging this, but I am getting a bunch of build
>> > failures under allmodconfig
>> >
>> > $ make.riscv allmodconfig
>> > #
>> > # configuration written to .config
>> > #
>> > $ make.riscv mm/kasan/init.o
>> > SYNC include/config/auto.conf.cmd
>> > CALL scripts/atomic/check-atomics.sh
>> > CC arch/riscv/kernel/asm-offsets.s
>> > CALL scripts/checksyscalls.sh
>> > CC mm/kasan/init.o
>> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> > make: *** [Makefile:1831: mm] Error 2
>> >
>> > Unfortunately my build box just blew up so I haven't had time to confim
>> > this still exists on v7, but nothing's jumping out as a fix. I've put
>> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
>> > what's going on but I'm guessing one of the macros has gone off the
>> > rails. I'm going to look at something else (as this one at least
>> > depends on Atish's patches), but LMK if you've got the time to look into
>> > this or if I should.
>>
>> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> series and some more series I saw on the list), so getting that into a
>> mergeable position would be really great :-)
>>
>> "attempt to move .org backwards" seems to be the telltale sign of the
>> alternatives blocks not matching up in size. While I definitly didn't see
>> anything like this in my tests on qemu + d1, I'll try to investigate where
>> that comes from.
>
> Hmm, looking at your branch [0] it seems that you're missing
> patch7 that introduces the no-compressed-instruction thingy
> for alternatives.
>
> And missing that patch will of course cause the size issue.
>
> The patch has made its way to the actual mailing lists [1], so I guess
> it "just" somehow didn't reach your inbox due to some mail hickup?

Sorry about that, I'm not sure what happened.

Unfortunately I'm now getting some even trickier failures: a handful of
configurations are failing very early in boot. There doesn't seem to be
much pattern to the configs that fail, but at least rv32 defconfig (on
QEMU's virt board) is doing so. I've tried poking around a bit and
can't figure out what's going on. I'll try and look again tomorrow
morning.

I've put my somewhat messy merged test branch at
kernel.org/palmer/riscv-d1-merge . Happy to hear if you have any
insights, otherwise I'l give it another shot (possibly after looking at
some other patches, there's quite a bit of a queue for this late).

>
>
> Heiko
>
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> [1] https://lore.kernel.org/all/[email protected]/
>
>
>> > > changes in v6:
>> > > - rebase onto 5.17-rc1
>> > > - handle sbi null-ptr differently
>> > > - improve commit messages
>> > > - use riscv,mmu as property name
>> > >
>> > > changes in v5:
>> > > - move to use alternatives for runtime-patching
>> > > - add D1 variant
>> > >
>> > >
>> > > [0] https://lore.kernel.org/r/[email protected]
>> > >
>> > >
>> > > Heiko Stuebner (12):
>> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> > > riscv: integrate alternatives better into the main architecture
>> > > riscv: allow different stages with alternatives
>> > > riscv: implement module alternatives
>> > > riscv: implement ALTERNATIVE_2 macro
>> > > riscv: extend concatenated alternatives-lines to the same length
>> > > riscv: prevent compressed instructions in alternatives
>> > > riscv: move boot alternatives to after fill_hwcap
>> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> > > riscv: add cpufeature handling via alternatives
>> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> > > riscv: add memory-type errata for T-Head
>> > >
>> > > Wei Fu (1):
>> > > riscv: add RISC-V Svpbmt extension support
>> > >
>> > > arch/riscv/Kconfig.erratas | 29 +++--
>> > > arch/riscv/Kconfig.socs | 1 -
>> > > arch/riscv/Makefile | 2 +-
>> > > arch/riscv/errata/Makefile | 2 +-
>> > > arch/riscv/errata/sifive/errata.c | 17 ++-
>> > > arch/riscv/errata/thead/Makefile | 1 +
>> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
>> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> > > arch/riscv/include/asm/alternative.h | 16 ++-
>> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
>> > > arch/riscv/include/asm/fixmap.h | 2 -
>> > > arch/riscv/include/asm/hwcap.h | 1 +
>> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
>> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
>> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
>> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
>> > > arch/riscv/include/asm/vendorid_list.h | 1 +
>> > > arch/riscv/kernel/Makefile | 1 +
>> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
>> > > arch/riscv/kernel/cpu.c | 1 +
>> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
>> > > arch/riscv/kernel/module.c | 29 +++++
>> > > arch/riscv/kernel/sbi.c | 10 +-
>> > > arch/riscv/kernel/setup.c | 2 +
>> > > arch/riscv/kernel/smpboot.c | 4 -
>> > > arch/riscv/kernel/traps.c | 2 +-
>> > > arch/riscv/mm/init.c | 1 +
>> > > 27 files changed, 546 insertions(+), 114 deletions(-)
>> > > create mode 100644 arch/riscv/errata/thead/Makefile
>> > > create mode 100644 arch/riscv/errata/thead/errata.c
>> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >
>>
>>

2022-03-19 14:38:15

by Heiko Stuebner

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

Hi Palmer,

Am Freitag, 18. M?rz 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> On Wed, 09 Mar 2022 14:06:55 PST (-0800), [email protected] wrote:
> > Am Dienstag, 8. M?rz 2022, 12:56:20 CET schrieb Heiko St?bner:
> >> Hi Palmer,
> >>
> >> Am Dienstag, 8. M?rz 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> > > for things like non-cacheable pages or I/O memory pages.
> >> > >
> >> > >
> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> > > types) using the alternatives framework.
> >> > >
> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> > > The biggest one being the move to a more central location, as I expect
> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> > > either for erratas or for optional features (svpbmt or others).
> >> > >
> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> > > anymore.
> >> > >
> >> > > The series also introduces support for the memory types of the D1
> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> > > location.
> >> > >
> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> > > even before the MMU is brought up, so the series introduces a separate
> >> > > stage for that.
> >> > >
> >> > >
> >> > > In theory this series is 3 parts:
> >> > > - sbi cache-flush / null-ptr
> >> >
> >> > That first patch looks like an acceptable candidate for fixes. If
> >> > there's a regression that manifests I'm happy to take it, but if it's
> >> > only possible to manifest a crash with the new stuff then I'm OK just
> >> > holding off until the merge window.
> >>
> >> While right now only my poking around the early init via alternatives
> >> is affected, the problem exists for everyone.
> >>
> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> should expect someone trying to call this in some early code-path
> >> as well.
> >>
> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> breakage that is fixed by patch1 .
> >>
> >>
> >> So it doesn't look like any _current_ code path has that issue, but
> >> it might be good to just pick patch1 for the next merge window
> >> individually?
> >>
> >>
> >>
> >> > > - alternatives improvements
> >> > > - svpbmt+d1
> >> > >
> >> > > So expecially patches from the first 2 areas could be applied when
> >> > > deemed ready, I just thought to keep it together to show-case where
> >> > > the end-goal is and not requiring jumping between different series.
> >> > >
> >> > >
> >> > > I picked the recipient list from the previous versions, hopefully
> >> > > I didn't forget anybody.
> >> > >
> >> > > changes in v7:
> >> > > - fix typo in patch1 (Atish)
> >> > > - moved to Atish's isa-extension framework
> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> > > - change T-Head errata Kconfig text (Atish)
> >> >
> >> > I was just poking around v6, so I have some minor comments there. None
> >> > of those need to block merging this, but I am getting a bunch of build
> >> > failures under allmodconfig
> >> >
> >> > $ make.riscv allmodconfig
> >> > #
> >> > # configuration written to .config
> >> > #
> >> > $ make.riscv mm/kasan/init.o
> >> > SYNC include/config/auto.conf.cmd
> >> > CALL scripts/atomic/check-atomics.sh
> >> > CC arch/riscv/kernel/asm-offsets.s
> >> > CALL scripts/checksyscalls.sh
> >> > CC mm/kasan/init.o
> >> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> > make: *** [Makefile:1831: mm] Error 2
> >> >
> >> > Unfortunately my build box just blew up so I haven't had time to confim
> >> > this still exists on v7, but nothing's jumping out as a fix. I've put
> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
> >> > what's going on but I'm guessing one of the macros has gone off the
> >> > rails. I'm going to look at something else (as this one at least
> >> > depends on Atish's patches), but LMK if you've got the time to look into
> >> > this or if I should.
> >>
> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> series and some more series I saw on the list), so getting that into a
> >> mergeable position would be really great :-)
> >>
> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> that comes from.
> >
> > Hmm, looking at your branch [0] it seems that you're missing
> > patch7 that introduces the no-compressed-instruction thingy
> > for alternatives.
> >
> > And missing that patch will of course cause the size issue.
> >
> > The patch has made its way to the actual mailing lists [1], so I guess
> > it "just" somehow didn't reach your inbox due to some mail hickup?
>
> Sorry about that, I'm not sure what happened.

no worries :-) . And I also have no clue where the hickup happened
but am thankful that there is no general problem with mails.


> Unfortunately I'm now getting some even trickier failures: a handful of
> configurations are failing very early in boot. There doesn't seem to be
> much pattern to the configs that fail, but at least rv32 defconfig (on
> QEMU's virt board) is doing so. I've tried poking around a bit and
> can't figure out what's going on. I'll try and look again tomorrow
> morning.

Hmm, really strange especially as the whole thing is somewhat
limited to 64bit anyway.

I guess it would be interesting if it's in the alternative-basics
part of the svpbmt implementation.

My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
yet, so I'll need to poke that more next week.

Heiko


> I've put my somewhat messy merged test branch at
> kernel.org/palmer/riscv-d1-merge . Happy to hear if you have any
> insights, otherwise I'l give it another shot (possibly after looking at
> some other patches, there's quite a bit of a queue for this late).
>
> >
> >
> > Heiko
> >
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> > [1] https://lore.kernel.org/all/[email protected]/
> >
> >
> >> > > changes in v6:
> >> > > - rebase onto 5.17-rc1
> >> > > - handle sbi null-ptr differently
> >> > > - improve commit messages
> >> > > - use riscv,mmu as property name
> >> > >
> >> > > changes in v5:
> >> > > - move to use alternatives for runtime-patching
> >> > > - add D1 variant
> >> > >
> >> > >
> >> > > [0] https://lore.kernel.org/r/[email protected]
> >> > >
> >> > >
> >> > > Heiko Stuebner (12):
> >> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> > > riscv: integrate alternatives better into the main architecture
> >> > > riscv: allow different stages with alternatives
> >> > > riscv: implement module alternatives
> >> > > riscv: implement ALTERNATIVE_2 macro
> >> > > riscv: extend concatenated alternatives-lines to the same length
> >> > > riscv: prevent compressed instructions in alternatives
> >> > > riscv: move boot alternatives to after fill_hwcap
> >> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> > > riscv: add cpufeature handling via alternatives
> >> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> > > riscv: add memory-type errata for T-Head
> >> > >
> >> > > Wei Fu (1):
> >> > > riscv: add RISC-V Svpbmt extension support
> >> > >
> >> > > arch/riscv/Kconfig.erratas | 29 +++--
> >> > > arch/riscv/Kconfig.socs | 1 -
> >> > > arch/riscv/Makefile | 2 +-
> >> > > arch/riscv/errata/Makefile | 2 +-
> >> > > arch/riscv/errata/sifive/errata.c | 17 ++-
> >> > > arch/riscv/errata/thead/Makefile | 1 +
> >> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
> >> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> > > arch/riscv/include/asm/alternative.h | 16 ++-
> >> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
> >> > > arch/riscv/include/asm/fixmap.h | 2 -
> >> > > arch/riscv/include/asm/hwcap.h | 1 +
> >> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
> >> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
> >> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
> >> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
> >> > > arch/riscv/include/asm/vendorid_list.h | 1 +
> >> > > arch/riscv/kernel/Makefile | 1 +
> >> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
> >> > > arch/riscv/kernel/cpu.c | 1 +
> >> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
> >> > > arch/riscv/kernel/module.c | 29 +++++
> >> > > arch/riscv/kernel/sbi.c | 10 +-
> >> > > arch/riscv/kernel/setup.c | 2 +
> >> > > arch/riscv/kernel/smpboot.c | 4 -
> >> > > arch/riscv/kernel/traps.c | 2 +-
> >> > > arch/riscv/mm/init.c | 1 +
> >> > > 27 files changed, 546 insertions(+), 114 deletions(-)
> >> > > create mode 100644 arch/riscv/errata/thead/Makefile
> >> > > create mode 100644 arch/riscv/errata/thead/errata.c
> >> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> >
> >>
> >>
>

2022-03-21 19:19:59

by Palmer Dabbelt

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

On Fri, 18 Mar 2022 09:22:29 PDT (-0700), [email protected] wrote:
> Hi Palmer,
>
> Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> On Wed, 09 Mar 2022 14:06:55 PST (-0800), [email protected] wrote:
>> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> Hi Palmer,
>> >>
>> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
>> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> > >
>> >> > >
>> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> > > types) using the alternatives framework.
>> >> > >
>> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> > > The biggest one being the move to a more central location, as I expect
>> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> > > either for erratas or for optional features (svpbmt or others).
>> >> > >
>> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> > > anymore.
>> >> > >
>> >> > > The series also introduces support for the memory types of the D1
>> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> > > location.
>> >> > >
>> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> > > stage for that.
>> >> > >
>> >> > >
>> >> > > In theory this series is 3 parts:
>> >> > > - sbi cache-flush / null-ptr
>> >> >
>> >> > That first patch looks like an acceptable candidate for fixes. If
>> >> > there's a regression that manifests I'm happy to take it, but if it's
>> >> > only possible to manifest a crash with the new stuff then I'm OK just
>> >> > holding off until the merge window.
>> >>
>> >> While right now only my poking around the early init via alternatives
>> >> is affected, the problem exists for everyone.
>> >>
>> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> should expect someone trying to call this in some early code-path
>> >> as well.
>> >>
>> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> breakage that is fixed by patch1 .
>> >>
>> >>
>> >> So it doesn't look like any _current_ code path has that issue, but
>> >> it might be good to just pick patch1 for the next merge window
>> >> individually?
>> >>
>> >>
>> >>
>> >> > > - alternatives improvements
>> >> > > - svpbmt+d1
>> >> > >
>> >> > > So expecially patches from the first 2 areas could be applied when
>> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> > > the end-goal is and not requiring jumping between different series.
>> >> > >
>> >> > >
>> >> > > I picked the recipient list from the previous versions, hopefully
>> >> > > I didn't forget anybody.
>> >> > >
>> >> > > changes in v7:
>> >> > > - fix typo in patch1 (Atish)
>> >> > > - moved to Atish's isa-extension framework
>> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> > > - change T-Head errata Kconfig text (Atish)
>> >> >
>> >> > I was just poking around v6, so I have some minor comments there. None
>> >> > of those need to block merging this, but I am getting a bunch of build
>> >> > failures under allmodconfig
>> >> >
>> >> > $ make.riscv allmodconfig
>> >> > #
>> >> > # configuration written to .config
>> >> > #
>> >> > $ make.riscv mm/kasan/init.o
>> >> > SYNC include/config/auto.conf.cmd
>> >> > CALL scripts/atomic/check-atomics.sh
>> >> > CC arch/riscv/kernel/asm-offsets.s
>> >> > CALL scripts/checksyscalls.sh
>> >> > CC mm/kasan/init.o
>> >> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> > make: *** [Makefile:1831: mm] Error 2
>> >> >
>> >> > Unfortunately my build box just blew up so I haven't had time to confim
>> >> > this still exists on v7, but nothing's jumping out as a fix. I've put
>> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
>> >> > what's going on but I'm guessing one of the macros has gone off the
>> >> > rails. I'm going to look at something else (as this one at least
>> >> > depends on Atish's patches), but LMK if you've got the time to look into
>> >> > this or if I should.
>> >>
>> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> series and some more series I saw on the list), so getting that into a
>> >> mergeable position would be really great :-)
>> >>
>> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> that comes from.
>> >
>> > Hmm, looking at your branch [0] it seems that you're missing
>> > patch7 that introduces the no-compressed-instruction thingy
>> > for alternatives.
>> >
>> > And missing that patch will of course cause the size issue.
>> >
>> > The patch has made its way to the actual mailing lists [1], so I guess
>> > it "just" somehow didn't reach your inbox due to some mail hickup?
>>
>> Sorry about that, I'm not sure what happened.
>
> no worries :-) . And I also have no clue where the hickup happened
> but am thankful that there is no general problem with mails.
>
>
>> Unfortunately I'm now getting some even trickier failures: a handful of
>> configurations are failing very early in boot. There doesn't seem to be
>> much pattern to the configs that fail, but at least rv32 defconfig (on
>> QEMU's virt board) is doing so. I've tried poking around a bit and
>> can't figure out what's going on. I'll try and look again tomorrow
>> morning.

(I guess morning means 2pm these days...)

> Hmm, really strange especially as the whole thing is somewhat
> limited to 64bit anyway.
>
> I guess it would be interesting if it's in the alternative-basics
> part of the svpbmt implementation.

Oddly enough it seems to be hanging as soon as I call into any of the
m*id SBI routines, but I'm not entierly sure what's up and I've been
bouncing between things so I might just be crazy.

I did bisect the rv32-defconfig failure down to the last patch.

>
> My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> yet, so I'll need to poke that more next week.

There's a bunch of failing cases, not just rv32, but I can't figure out
what logic there is behind the failing cases. They're all in my
riscv-system-ci repo, it's a mess but should at least build. I see the
following hang:

qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic

rv32 defconfig seemed like the simplest, but there's a bunch of rv64
configs that fail too (though not defconfig, and the earlycon configs
don't hang).

I'm going to go look at that other stuff I wanted to, but I'll try and
find some time this weekend if nobody else can figure out what's up.


>
> Heiko
>
>
>> I've put my somewhat messy merged test branch at
>> kernel.org/palmer/riscv-d1-merge . Happy to hear if you have any
>> insights, otherwise I'l give it another shot (possibly after looking at
>> some other patches, there's quite a bit of a queue for this late).
>>
>> >
>> >
>> > Heiko
>> >
>> >
>> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> > [1] https://lore.kernel.org/all/[email protected]/
>> >
>> >
>> >> > > changes in v6:
>> >> > > - rebase onto 5.17-rc1
>> >> > > - handle sbi null-ptr differently
>> >> > > - improve commit messages
>> >> > > - use riscv,mmu as property name
>> >> > >
>> >> > > changes in v5:
>> >> > > - move to use alternatives for runtime-patching
>> >> > > - add D1 variant
>> >> > >
>> >> > >
>> >> > > [0] https://lore.kernel.org/r/[email protected]
>> >> > >
>> >> > >
>> >> > > Heiko Stuebner (12):
>> >> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> > > riscv: integrate alternatives better into the main architecture
>> >> > > riscv: allow different stages with alternatives
>> >> > > riscv: implement module alternatives
>> >> > > riscv: implement ALTERNATIVE_2 macro
>> >> > > riscv: extend concatenated alternatives-lines to the same length
>> >> > > riscv: prevent compressed instructions in alternatives
>> >> > > riscv: move boot alternatives to after fill_hwcap
>> >> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> > > riscv: add cpufeature handling via alternatives
>> >> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> > > riscv: add memory-type errata for T-Head
>> >> > >
>> >> > > Wei Fu (1):
>> >> > > riscv: add RISC-V Svpbmt extension support
>> >> > >
>> >> > > arch/riscv/Kconfig.erratas | 29 +++--
>> >> > > arch/riscv/Kconfig.socs | 1 -
>> >> > > arch/riscv/Makefile | 2 +-
>> >> > > arch/riscv/errata/Makefile | 2 +-
>> >> > > arch/riscv/errata/sifive/errata.c | 17 ++-
>> >> > > arch/riscv/errata/thead/Makefile | 1 +
>> >> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
>> >> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> > > arch/riscv/include/asm/alternative.h | 16 ++-
>> >> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
>> >> > > arch/riscv/include/asm/fixmap.h | 2 -
>> >> > > arch/riscv/include/asm/hwcap.h | 1 +
>> >> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
>> >> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
>> >> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
>> >> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
>> >> > > arch/riscv/include/asm/vendorid_list.h | 1 +
>> >> > > arch/riscv/kernel/Makefile | 1 +
>> >> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
>> >> > > arch/riscv/kernel/cpu.c | 1 +
>> >> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
>> >> > > arch/riscv/kernel/module.c | 29 +++++
>> >> > > arch/riscv/kernel/sbi.c | 10 +-
>> >> > > arch/riscv/kernel/setup.c | 2 +
>> >> > > arch/riscv/kernel/smpboot.c | 4 -
>> >> > > arch/riscv/kernel/traps.c | 2 +-
>> >> > > arch/riscv/mm/init.c | 1 +
>> >> > > 27 files changed, 546 insertions(+), 114 deletions(-)
>> >> > > create mode 100644 arch/riscv/errata/thead/Makefile
>> >> > > create mode 100644 arch/riscv/errata/thead/errata.c
>> >> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> >
>> >>
>> >>
>>

2022-03-24 02:03:53

by Heiko Stuebner

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

Am Freitag, 18. M?rz 2022, 22:50:05 CET schrieb Palmer Dabbelt:
> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), [email protected] wrote:
> > Hi Palmer,
> >
> > Am Freitag, 18. M?rz 2022, 04:40:23 CET schrieb Palmer Dabbelt:
> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), [email protected] wrote:
> >> > Am Dienstag, 8. M?rz 2022, 12:56:20 CET schrieb Heiko St?bner:
> >> >> Hi Palmer,
> >> >>
> >> >> Am Dienstag, 8. M?rz 2022, 01:47:25 CET schrieb Palmer Dabbelt:
> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> >> >> > > for things like non-cacheable pages or I/O memory pages.
> >> >> > >
> >> >> > >
> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> >> >> > > types) using the alternatives framework.
> >> >> > >
> >> >> > > This includes a number of changes to the alternatives mechanism itself.
> >> >> > > The biggest one being the move to a more central location, as I expect
> >> >> > > in the future, nearly every chip needing some sort of patching, be it
> >> >> > > either for erratas or for optional features (svpbmt or others).
> >> >> > >
> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
> >> >> > > anymore.
> >> >> > >
> >> >> > > The series also introduces support for the memory types of the D1
> >> >> > > which are implemented differently to svpbmt. But when patching anyway
> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> >> >> > > location.
> >> >> > >
> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
> >> >> > > even before the MMU is brought up, so the series introduces a separate
> >> >> > > stage for that.
> >> >> > >
> >> >> > >
> >> >> > > In theory this series is 3 parts:
> >> >> > > - sbi cache-flush / null-ptr
> >> >> >
> >> >> > That first patch looks like an acceptable candidate for fixes. If
> >> >> > there's a regression that manifests I'm happy to take it, but if it's
> >> >> > only possible to manifest a crash with the new stuff then I'm OK just
> >> >> > holding off until the merge window.
> >> >>
> >> >> While right now only my poking around the early init via alternatives
> >> >> is affected, the problem exists for everyone.
> >> >>
> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
> >> >> should expect someone trying to call this in some early code-path
> >> >> as well.
> >> >>
> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
> >> >> breakage that is fixed by patch1 .
> >> >>
> >> >>
> >> >> So it doesn't look like any _current_ code path has that issue, but
> >> >> it might be good to just pick patch1 for the next merge window
> >> >> individually?
> >> >>
> >> >>
> >> >>
> >> >> > > - alternatives improvements
> >> >> > > - svpbmt+d1
> >> >> > >
> >> >> > > So expecially patches from the first 2 areas could be applied when
> >> >> > > deemed ready, I just thought to keep it together to show-case where
> >> >> > > the end-goal is and not requiring jumping between different series.
> >> >> > >
> >> >> > >
> >> >> > > I picked the recipient list from the previous versions, hopefully
> >> >> > > I didn't forget anybody.
> >> >> > >
> >> >> > > changes in v7:
> >> >> > > - fix typo in patch1 (Atish)
> >> >> > > - moved to Atish's isa-extension framework
> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
> >> >> > > - change T-Head errata Kconfig text (Atish)
> >> >> >
> >> >> > I was just poking around v6, so I have some minor comments there. None
> >> >> > of those need to block merging this, but I am getting a bunch of build
> >> >> > failures under allmodconfig
> >> >> >
> >> >> > $ make.riscv allmodconfig
> >> >> > #
> >> >> > # configuration written to .config
> >> >> > #
> >> >> > $ make.riscv mm/kasan/init.o
> >> >> > SYNC include/config/auto.conf.cmd
> >> >> > CALL scripts/atomic/check-atomics.sh
> >> >> > CC arch/riscv/kernel/asm-offsets.s
> >> >> > CALL scripts/checksyscalls.sh
> >> >> > CC mm/kasan/init.o
> >> >> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
> >> >> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
> >> >> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
> >> >> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
> >> >> > make: *** [Makefile:1831: mm] Error 2
> >> >> >
> >> >> > Unfortunately my build box just blew up so I haven't had time to confim
> >> >> > this still exists on v7, but nothing's jumping out as a fix. I've put
> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
> >> >> > what's going on but I'm guessing one of the macros has gone off the
> >> >> > rails. I'm going to look at something else (as this one at least
> >> >> > depends on Atish's patches), but LMK if you've got the time to look into
> >> >> > this or if I should.
> >> >>
> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
> >> >> series and some more series I saw on the list), so getting that into a
> >> >> mergeable position would be really great :-)
> >> >>
> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
> >> >> alternatives blocks not matching up in size. While I definitly didn't see
> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
> >> >> that comes from.
> >> >
> >> > Hmm, looking at your branch [0] it seems that you're missing
> >> > patch7 that introduces the no-compressed-instruction thingy
> >> > for alternatives.
> >> >
> >> > And missing that patch will of course cause the size issue.
> >> >
> >> > The patch has made its way to the actual mailing lists [1], so I guess
> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
> >>
> >> Sorry about that, I'm not sure what happened.
> >
> > no worries :-) . And I also have no clue where the hickup happened
> > but am thankful that there is no general problem with mails.
> >
> >
> >> Unfortunately I'm now getting some even trickier failures: a handful of
> >> configurations are failing very early in boot. There doesn't seem to be
> >> much pattern to the configs that fail, but at least rv32 defconfig (on
> >> QEMU's virt board) is doing so. I've tried poking around a bit and
> >> can't figure out what's going on. I'll try and look again tomorrow
> >> morning.
>
> (I guess morning means 2pm these days...)
>
> > Hmm, really strange especially as the whole thing is somewhat
> > limited to 64bit anyway.
> >
> > I guess it would be interesting if it's in the alternative-basics
> > part of the svpbmt implementation.
>
> Oddly enough it seems to be hanging as soon as I call into any of the
> m*id SBI routines, but I'm not entierly sure what's up and I've been
> bouncing between things so I might just be crazy.

You're defintily not crazy here :-) .

I.e. I didn't notice your reply from friday until now and so did the same
stepping through the code myself as well, after finally getting a rv32
build working.

Similarly I ended up at sbi_get_mvendorid() being the first failing function.

_But_ ... sbi isn't at fault here. What is causing the issue is the writes
to the static global variables. And I guess that will also be the issue
you saw on the other platforms.

The early-alternatives-mechanism runs before the kernel relocation,
so likely triggers some memory protection, which I didn't think of.

I'll just rework the code to not use static variables for storing both
the architecture-ids as well as the patch-func, which I think should
solve that issue for all platforms.


Heiko


> I did bisect the rv32-defconfig failure down to the last patch.
>
> >
> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
> > yet, so I'll need to poke that more next week.
>
> There's a bunch of failing cases, not just rv32, but I can't figure out
> what logic there is behind the failing cases. They're all in my
> riscv-system-ci repo, it's a mess but should at least build. I see the
> following hang:
>
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
>
> rv32 defconfig seemed like the simplest, but there's a bunch of rv64
> configs that fail too (though not defconfig, and the earlycon configs
> don't hang).
>
> I'm going to go look at that other stuff I wanted to, but I'll try and
> find some time this weekend if nobody else can figure out what's up.
>
>
> >
> > Heiko
> >
> >
> >> I've put my somewhat messy merged test branch at
> >> kernel.org/palmer/riscv-d1-merge . Happy to hear if you have any
> >> insights, otherwise I'l give it another shot (possibly after looking at
> >> some other patches, there's quite a bit of a queue for this late).
> >>
> >> >
> >> >
> >> > Heiko
> >> >
> >> >
> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
> >> > [1] https://lore.kernel.org/all/[email protected]/
> >> >
> >> >
> >> >> > > changes in v6:
> >> >> > > - rebase onto 5.17-rc1
> >> >> > > - handle sbi null-ptr differently
> >> >> > > - improve commit messages
> >> >> > > - use riscv,mmu as property name
> >> >> > >
> >> >> > > changes in v5:
> >> >> > > - move to use alternatives for runtime-patching
> >> >> > > - add D1 variant
> >> >> > >
> >> >> > >
> >> >> > > [0] https://lore.kernel.org/r/[email protected]
> >> >> > >
> >> >> > >
> >> >> > > Heiko Stuebner (12):
> >> >> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
> >> >> > > riscv: integrate alternatives better into the main architecture
> >> >> > > riscv: allow different stages with alternatives
> >> >> > > riscv: implement module alternatives
> >> >> > > riscv: implement ALTERNATIVE_2 macro
> >> >> > > riscv: extend concatenated alternatives-lines to the same length
> >> >> > > riscv: prevent compressed instructions in alternatives
> >> >> > > riscv: move boot alternatives to after fill_hwcap
> >> >> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> >> >> > > riscv: add cpufeature handling via alternatives
> >> >> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> >> >> > > riscv: add memory-type errata for T-Head
> >> >> > >
> >> >> > > Wei Fu (1):
> >> >> > > riscv: add RISC-V Svpbmt extension support
> >> >> > >
> >> >> > > arch/riscv/Kconfig.erratas | 29 +++--
> >> >> > > arch/riscv/Kconfig.socs | 1 -
> >> >> > > arch/riscv/Makefile | 2 +-
> >> >> > > arch/riscv/errata/Makefile | 2 +-
> >> >> > > arch/riscv/errata/sifive/errata.c | 17 ++-
> >> >> > > arch/riscv/errata/thead/Makefile | 1 +
> >> >> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
> >> >> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
> >> >> > > arch/riscv/include/asm/alternative.h | 16 ++-
> >> >> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
> >> >> > > arch/riscv/include/asm/fixmap.h | 2 -
> >> >> > > arch/riscv/include/asm/hwcap.h | 1 +
> >> >> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
> >> >> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
> >> >> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
> >> >> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
> >> >> > > arch/riscv/include/asm/vendorid_list.h | 1 +
> >> >> > > arch/riscv/kernel/Makefile | 1 +
> >> >> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
> >> >> > > arch/riscv/kernel/cpu.c | 1 +
> >> >> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
> >> >> > > arch/riscv/kernel/module.c | 29 +++++
> >> >> > > arch/riscv/kernel/sbi.c | 10 +-
> >> >> > > arch/riscv/kernel/setup.c | 2 +
> >> >> > > arch/riscv/kernel/smpboot.c | 4 -
> >> >> > > arch/riscv/kernel/traps.c | 2 +-
> >> >> > > arch/riscv/mm/init.c | 1 +
> >> >> > > 27 files changed, 546 insertions(+), 114 deletions(-)
> >> >> > > create mode 100644 arch/riscv/errata/thead/Makefile
> >> >> > > create mode 100644 arch/riscv/errata/thead/errata.c
> >> >> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
> >> >> >
> >> >>
> >> >>
> >>
>

2022-03-24 06:04:16

by Palmer Dabbelt

Subject: Re: [PATCH v7 00/13] riscv: support for Svpbmt and D1 memory types

On Tue, 22 Mar 2022 09:09:04 PDT (-0700), [email protected] wrote:
> Am Freitag, 18. März 2022, 22:50:05 CET schrieb Palmer Dabbelt:
>> On Fri, 18 Mar 2022 09:22:29 PDT (-0700), [email protected] wrote:
>> > Hi Palmer,
>> >
>> > Am Freitag, 18. März 2022, 04:40:23 CET schrieb Palmer Dabbelt:
>> >> On Wed, 09 Mar 2022 14:06:55 PST (-0800), [email protected] wrote:
>> >> > Am Dienstag, 8. März 2022, 12:56:20 CET schrieb Heiko Stübner:
>> >> >> Hi Palmer,
>> >> >>
>> >> >> Am Dienstag, 8. März 2022, 01:47:25 CET schrieb Palmer Dabbelt:
>> >> >> > On Mon, 07 Mar 2022 12:52:57 PST (-0800), [email protected] wrote:
>> >> >> > > Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
>> >> >> > > for things like non-cacheable pages or I/O memory pages.
>> >> >> > >
>> >> >> > >
>> >> >> > > So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
>> >> >> > > types) using the alternatives framework.
>> >> >> > >
>> >> >> > > This includes a number of changes to the alternatives mechanism itself.
>> >> >> > > The biggest one being the move to a more central location, as I expect
>> >> >> > > in the future, nearly every chip needing some sort of patching, be it
>> >> >> > > either for erratas or for optional features (svpbmt or others).
>> >> >> > >
>> >> >> > > Detection of the svpbmt functionality is done via Atish's isa extension
>> >> >> > > handling series [0] and thus does not need any dt-parsing of its own
>> >> >> > > anymore.
>> >> >> > >
>> >> >> > > The series also introduces support for the memory types of the D1
>> >> >> > > which are implemented differently to svpbmt. But when patching anyway
>> >> >> > > it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
>> >> >> > > location.
>> >> >> > >
>> >> >> > > The only slightly bigger difference is that the "normal" type is not 0
>> >> >> > > as with svpbmt, so kernel patches for this PMA type need to be applied
>> >> >> > > even before the MMU is brought up, so the series introduces a separate
>> >> >> > > stage for that.
>> >> >> > >
>> >> >> > >
>> >> >> > > In theory this series is 3 parts:
>> >> >> > > - sbi cache-flush / null-ptr
>> >> >> >
>> >> >> > That first patch looks like an acceptable candidate for fixes. If
>> >> >> > there's a regression that manifests I'm happy to take it, but if it's
>> >> >> > only possible to manifest a crash with the new stuff then I'm OK just
>> >> >> > holding off until the merge window.
>> >> >>
>> >> >> While right now only my poking around the early init via alternatives
>> >> >> is affected, the problem exists for everyone.
>> >> >>
>> >> >> I.e. I do consider flush_icache_all() to be generic enough that we
>> >> >> should expect someone trying to call this in some early code-path
>> >> >> as well.
>> >> >>
>> >> >> But any call to flush_icache_all() before sbi_init() ran will cause the
>> >> >> breakage that is fixed by patch1 .
>> >> >>
>> >> >>
>> >> >> So it doesn't look like any _current_ code path has that issue, but
>> >> >> it might be good to just pick patch1 for the next merge window
>> >> >> individually?
>> >> >>
>> >> >>
>> >> >>
>> >> >> > > - alternatives improvements
>> >> >> > > - svpbmt+d1
>> >> >> > >
>> >> >> > > So expecially patches from the first 2 areas could be applied when
>> >> >> > > deemed ready, I just thought to keep it together to show-case where
>> >> >> > > the end-goal is and not requiring jumping between different series.
>> >> >> > >
>> >> >> > >
>> >> >> > > I picked the recipient list from the previous versions, hopefully
>> >> >> > > I didn't forget anybody.
>> >> >> > >
>> >> >> > > changes in v7:
>> >> >> > > - fix typo in patch1 (Atish)
>> >> >> > > - moved to Atish's isa-extension framework
>> >> >> > > - and therefore move regular boot-alternatives directly behind fill_hwcaps
>> >> >> > > - change T-Head errata Kconfig text (Atish)
>> >> >> >
>> >> >> > I was just poking around v6, so I have some minor comments there. None
>> >> >> > of those need to block merging this, but I am getting a bunch of build
>> >> >> > failures under allmodconfig
>> >> >> >
>> >> >> > $ make.riscv allmodconfig
>> >> >> > #
>> >> >> > # configuration written to .config
>> >> >> > #
>> >> >> > $ make.riscv mm/kasan/init.o
>> >> >> > SYNC include/config/auto.conf.cmd
>> >> >> > CALL scripts/atomic/check-atomics.sh
>> >> >> > CC arch/riscv/kernel/asm-offsets.s
>> >> >> > CALL scripts/checksyscalls.sh
>> >> >> > CC mm/kasan/init.o
>> >> >> > ./arch/riscv/include/asm/pgtable.h: Assembler messages:
>> >> >> > ./arch/riscv/include/asm/pgtable.h:323: Error: attempt to move .org backwards
>> >> >> > make[2]: *** [scripts/Makefile.build:288: mm/kasan/init.o] Error 1
>> >> >> > make[1]: *** [scripts/Makefile.build:550: mm/kasan] Error 2
>> >> >> > make: *** [Makefile:1831: mm] Error 2
>> >> >> >
>> >> >> > Unfortunately my build box just blew up so I haven't had time to confim
>> >> >> > this still exists on v7, but nothing's jumping out as a fix. I've put
>> >> >> > this on the riscv-d1 branch at kernel.org/palmer/linux, not sure exactly
>> >> >> > what's going on but I'm guessing one of the macros has gone off the
>> >> >> > rails. I'm going to look at something else (as this one at least
>> >> >> > depends on Atish's patches), but LMK if you've got the time to look into
>> >> >> > this or if I should.
>> >> >>
>> >> >> Yeah, we now depend on Atish's isa-extension parsing (same for my cmo
>> >> >> series and some more series I saw on the list), so getting that into a
>> >> >> mergeable position would be really great :-)
>> >> >>
>> >> >> "attempt to move .org backwards" seems to be the telltale sign of the
>> >> >> alternatives blocks not matching up in size. While I definitly didn't see
>> >> >> anything like this in my tests on qemu + d1, I'll try to investigate where
>> >> >> that comes from.
>> >> >
>> >> > Hmm, looking at your branch [0] it seems that you're missing
>> >> > patch7 that introduces the no-compressed-instruction thingy
>> >> > for alternatives.
>> >> >
>> >> > And missing that patch will of course cause the size issue.
>> >> >
>> >> > The patch has made its way to the actual mailing lists [1], so I guess
>> >> > it "just" somehow didn't reach your inbox due to some mail hickup?
>> >>
>> >> Sorry about that, I'm not sure what happened.
>> >
>> > no worries :-) . And I also have no clue where the hickup happened
>> > but am thankful that there is no general problem with mails.
>> >
>> >
>> >> Unfortunately I'm now getting some even trickier failures: a handful of
>> >> configurations are failing very early in boot. There doesn't seem to be
>> >> much pattern to the configs that fail, but at least rv32 defconfig (on
>> >> QEMU's virt board) is doing so. I've tried poking around a bit and
>> >> can't figure out what's going on. I'll try and look again tomorrow
>> >> morning.
>>
>> (I guess morning means 2pm these days...)
>>
>> > Hmm, really strange especially as the whole thing is somewhat
>> > limited to 64bit anyway.
>> >
>> > I guess it would be interesting if it's in the alternative-basics
>> > part of the svpbmt implementation.
>>
>> Oddly enough it seems to be hanging as soon as I call into any of the
>> m*id SBI routines, but I'm not entierly sure what's up and I've been
>> bouncing between things so I might just be crazy.
>
> You're defintily not crazy here :-) .
>
> I.e. I didn't notice your reply from friday until now and so did the same
> stepping through the code myself as well, after finally getting a rv32
> build working.
>
> Similarly I ended up at sbi_get_mvendorid() being the first failing function.
>
> _But_ ... sbi isn't at fault here. What is causing the issue is the writes
> to the static global variables. And I guess that will also be the issue
> you saw on the other platforms.
>
> The early-alternatives-mechanism runs before the kernel relocation,
> so likely triggers some memory protection, which I didn't think of.
>
> I'll just rework the code to not use static variables for storing both
> the architecture-ids as well as the patch-func, which I think should
> solve that issue for all platforms.

Awesome, thanks for looking at this.

> Heiko
>
>
>> I did bisect the rv32-defconfig failure down to the last patch.
>>
>> >
>> > My short try on getting a (any) rv32 kernel boot in qemu wasn't sucessful
>> > yet, so I'll need to poke that more next week.
>>
>> There's a bunch of failing cases, not just rv32, but I can't figure out
>> what logic there is behind the failing cases. They're all in my
>> riscv-system-ci repo, it's a mess but should at least build. I see the
>> following hang:
>>
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-strict_rwx/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-strict_rwx/initrd -serial mon:pipe:/tmp/tmp.BM8zYJCKKZ/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab_freelist_random/initrd -serial mon:pipe:/tmp/tmp.x7BL4Y1UsX/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.I9NZ3ow1GY/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.c9UPXaNcfR/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.AkLFnd3IDt/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.TbUWlXHDtO/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.E4h3Gw5Ecv/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-slab/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-slab/initrd -serial mon:pipe:/tmp/tmp.anq8X90A1C/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.4MK3Xys4YL/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-vmap_stack/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-vmap_stack/initrd -serial mon:pipe:/tmp/tmp.fC0b16uUpo/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.t8nlK1Cvkk/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.stV634slMi/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.D0M6BSjwo2/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.x9AoOydj6h/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 8 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp8/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.cYwEP0Xod2/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.EmYY46ZyFw/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.UGF8OoNOXr/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.E540ImVMDZ/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.Hg8iJhkm2R/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 2G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-m2g/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.4KQh2WmFWc/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M spike -m 1G -smp 1 -cpu rv64 -kernel check/qemu-rv64gc-spike/halt-legacy_sbi/kernel -initrd check/qemu-rv64gc-spike/halt-legacy_sbi/initrd -serial mon:pipe:/tmp/tmp.Ore2LcgxNR/guest -bios default -nographic -append console=hvc0
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan/initrd -serial mon:pipe:/tmp/tmp.jnvHnbSJKT/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-medlow/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-medlow/initrd -serial mon:pipe:/tmp/tmp.30Kl16f7mY/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_novmemmmap/initrd -serial mon:pipe:/tmp/tmp.ojW4EsFqOX/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_vmalloc/initrd -serial mon:pipe:/tmp/tmp.iKrvig4P7H/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv64 -M virt -m 8G -smp 4 -cpu rv64 -kernel check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/kernel -initrd check/qemu-rv64gc-virt-smp4/halt-kasan_sparsemem_vmemmmap/initrd -serial mon:pipe:/tmp/tmp.LGrpnHKQXO/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/cpuinfo-defconfig/initrd -serial mon:pipe:/tmp/tmp.0RO7a4EUiB/guest -bios default -nographic
>> qemu/install/bin/qemu-system-riscv32 -M virt -m 1G -smp 4 -cpu rv32 -kernel check/qemu-rv32gc-virt-smp4/halt-defconfig/kernel -initrd check/qemu-rv32gc-virt-smp4/halt-defconfig/initrd -serial mon:pipe:/tmp/tmp.Ltd1s19HqT/guest -bios default -nographic
>>
>> rv32 defconfig seemed like the simplest, but there's a bunch of rv64
>> configs that fail too (though not defconfig, and the earlycon configs
>> don't hang).
>>
>> I'm going to go look at that other stuff I wanted to, but I'll try and
>> find some time this weekend if nobody else can figure out what's up.
>>
>>
>> >
>> > Heiko
>> >
>> >
>> >> I've put my somewhat messy merged test branch at
>> >> kernel.org/palmer/riscv-d1-merge . Happy to hear if you have any
>> >> insights, otherwise I'l give it another shot (possibly after looking at
>> >> some other patches, there's quite a bit of a queue for this late).
>> >>
>> >> >
>> >> >
>> >> > Heiko
>> >> >
>> >> >
>> >> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-d1
>> >> > [1] https://lore.kernel.org/all/[email protected]/
>> >> >
>> >> >
>> >> >> > > changes in v6:
>> >> >> > > - rebase onto 5.17-rc1
>> >> >> > > - handle sbi null-ptr differently
>> >> >> > > - improve commit messages
>> >> >> > > - use riscv,mmu as property name
>> >> >> > >
>> >> >> > > changes in v5:
>> >> >> > > - move to use alternatives for runtime-patching
>> >> >> > > - add D1 variant
>> >> >> > >
>> >> >> > >
>> >> >> > > [0] https://lore.kernel.org/r/[email protected]
>> >> >> > >
>> >> >> > >
>> >> >> > > Heiko Stuebner (12):
>> >> >> > > riscv: prevent null-pointer dereference with sbi_remote_fence_i
>> >> >> > > riscv: integrate alternatives better into the main architecture
>> >> >> > > riscv: allow different stages with alternatives
>> >> >> > > riscv: implement module alternatives
>> >> >> > > riscv: implement ALTERNATIVE_2 macro
>> >> >> > > riscv: extend concatenated alternatives-lines to the same length
>> >> >> > > riscv: prevent compressed instructions in alternatives
>> >> >> > > riscv: move boot alternatives to after fill_hwcap
>> >> >> > > riscv: Fix accessing pfn bits in PTEs for non-32bit variants
>> >> >> > > riscv: add cpufeature handling via alternatives
>> >> >> > > riscv: remove FIXMAP_PAGE_IO and fall back to its default value
>> >> >> > > riscv: add memory-type errata for T-Head
>> >> >> > >
>> >> >> > > Wei Fu (1):
>> >> >> > > riscv: add RISC-V Svpbmt extension support
>> >> >> > >
>> >> >> > > arch/riscv/Kconfig.erratas | 29 +++--
>> >> >> > > arch/riscv/Kconfig.socs | 1 -
>> >> >> > > arch/riscv/Makefile | 2 +-
>> >> >> > > arch/riscv/errata/Makefile | 2 +-
>> >> >> > > arch/riscv/errata/sifive/errata.c | 17 ++-
>> >> >> > > arch/riscv/errata/thead/Makefile | 1 +
>> >> >> > > arch/riscv/errata/thead/errata.c | 85 +++++++++++++++
>> >> >> > > arch/riscv/include/asm/alternative-macros.h | 114 +++++++++++---------
>> >> >> > > arch/riscv/include/asm/alternative.h | 16 ++-
>> >> >> > > arch/riscv/include/asm/errata_list.h | 52 +++++++++
>> >> >> > > arch/riscv/include/asm/fixmap.h | 2 -
>> >> >> > > arch/riscv/include/asm/hwcap.h | 1 +
>> >> >> > > arch/riscv/include/asm/pgtable-32.h | 17 +++
>> >> >> > > arch/riscv/include/asm/pgtable-64.h | 79 +++++++++++++-
>> >> >> > > arch/riscv/include/asm/pgtable-bits.h | 10 --
>> >> >> > > arch/riscv/include/asm/pgtable.h | 53 +++++++--
>> >> >> > > arch/riscv/include/asm/vendorid_list.h | 1 +
>> >> >> > > arch/riscv/kernel/Makefile | 1 +
>> >> >> > > arch/riscv/{errata => kernel}/alternative.c | 48 +++++++--
>> >> >> > > arch/riscv/kernel/cpu.c | 1 +
>> >> >> > > arch/riscv/kernel/cpufeature.c | 80 +++++++++++++-
>> >> >> > > arch/riscv/kernel/module.c | 29 +++++
>> >> >> > > arch/riscv/kernel/sbi.c | 10 +-
>> >> >> > > arch/riscv/kernel/setup.c | 2 +
>> >> >> > > arch/riscv/kernel/smpboot.c | 4 -
>> >> >> > > arch/riscv/kernel/traps.c | 2 +-
>> >> >> > > arch/riscv/mm/init.c | 1 +
>> >> >> > > 27 files changed, 546 insertions(+), 114 deletions(-)
>> >> >> > > create mode 100644 arch/riscv/errata/thead/Makefile
>> >> >> > > create mode 100644 arch/riscv/errata/thead/errata.c
>> >> >> > > rename arch/riscv/{errata => kernel}/alternative.c (59%)
>> >> >> >
>> >> >>
>> >> >>
>> >>
>>