From: Gabriel Fernandez <[email protected]>
v3:
- cosmetic change from Stephen Boyd
- rename some functions in clk-stm32-core
- add missing static for variables or functions
v2:
- Resend because patch 9,10,12,13 has not been sent
- add Reviewed by Krzysztof Kozlowski for patch 1
Gabriel Fernandez (13):
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
clk: stm32mp13: add stm32_mux clock management
clk: stm32mp13: add stm32_gate management
clk: stm32mp13: add stm32 divider clock
clk: stm32mp13: add composite clock
clk: stm32mp13: manage secured clocks
clk: stm32mp13: add all STM32MP13 peripheral clocks
clk: stm32mp13: add all STM32MP13 kernel clocks
clk: stm32mp13: add multi mux function
clk: stm32mp13: add safe mux management
ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
ARM: dts: stm32: add RCC on STM32MP13x SoC family
.../bindings/clock/st,stm32mp1-rcc.yaml | 2 +
arch/arm/boot/dts/stm32mp131.dtsi | 128 +-
arch/arm/boot/dts/stm32mp133.dtsi | 4 +-
arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +-
drivers/clk/Kconfig | 5 +
drivers/clk/Makefile | 1 +
drivers/clk/stm32/Makefile | 1 +
drivers/clk/stm32/clk-stm32-core.c | 695 +++++++
drivers/clk/stm32/clk-stm32-core.h | 188 ++
drivers/clk/stm32/clk-stm32mp13.c | 1620 +++++++++++++++
drivers/clk/stm32/reset-stm32.c | 122 ++
drivers/clk/stm32/reset-stm32.h | 8 +
drivers/clk/stm32/stm32mp13_rcc.h | 1748 +++++++++++++++++
include/dt-bindings/clock/stm32mp13-clks.h | 229 +++
include/dt-bindings/reset/stm32mp13-resets.h | 100 +
15 files changed, 4794 insertions(+), 60 deletions(-)
create mode 100644 drivers/clk/stm32/Makefile
create mode 100644 drivers/clk/stm32/clk-stm32-core.c
create mode 100644 drivers/clk/stm32/clk-stm32-core.h
create mode 100644 drivers/clk/stm32/clk-stm32mp13.c
create mode 100644 drivers/clk/stm32/reset-stm32.c
create mode 100644 drivers/clk/stm32/reset-stm32.h
create mode 100644 drivers/clk/stm32/stm32mp13_rcc.h
create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h
create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Some muxes need to set a the safe position when clock is off.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 54 ++++++++++++++++++++++++++++++
drivers/clk/stm32/clk-stm32-core.h | 1 +
drivers/clk/stm32/clk-stm32mp13.c | 11 +++---
3 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index e5a22bb09495..45a279e73779 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -495,6 +495,54 @@ static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
}
+#define MUX_SAFE_POSITION 0
+
+static int clk_stm32_has_safe_mux(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
+
+ return !!(mux->flags & MUX_SAFE);
+}
+
+static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ if (!clk_stm32_composite_is_enabled(hw)) {
+ unsigned long flags = 0;
+
+ if (composite->clock_data->is_multi_mux) {
+ struct clk_hw *other_mux_hw = NULL;
+
+ other_mux_hw = composite->clock_data->is_multi_mux(hw);
+
+ if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
+ return;
+ }
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ stm32_mux_set_parent(composite->base, composite->clock_data,
+ composite->mux_id, MUX_SAFE_POSITION);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+ }
+}
+
+static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ int sel = clk_hw_get_parent_index(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+}
+
static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
{
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
@@ -516,6 +564,9 @@ static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
clk_stm32_composite_gate_endisable(hw, 1);
+ if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
+ clk_stm32_safe_restore_position_mux(hw);
+
return 0;
}
@@ -527,6 +578,9 @@ static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
return;
clk_stm32_composite_gate_endisable(hw, 0);
+
+ if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
+ clk_stm32_set_safe_position_mux(hw);
}
static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index dab1b65b2537..76cffda02308 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -84,6 +84,7 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
/* MUX define */
#define MUX_NO_RDY 0xFF
+#define MUX_SAFE BIT(7)
/* DIV define */
#define DIV_NO_RDY 0xFF
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 08e3fe05d6d0..1192eee8abe4 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -359,6 +359,9 @@ enum enum_mux_cfg {
#define CFG_MUX(_id, _offset, _shift, _witdh)\
_CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
+#define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\
+ _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, MUX_SAFE)
+
static const struct stm32_mux_cfg stm32mp13_muxes[] = {
CFG_MUX(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
CFG_MUX(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
@@ -394,10 +397,10 @@ static const struct stm32_mux_cfg stm32mp13_muxes[] = {
CFG_MUX(MUX_UART6, RCC_UART6CKSELR, 0, 3),
CFG_MUX(MUX_USBO, RCC_USBCKSELR, 4, 1),
CFG_MUX(MUX_USBPHY, RCC_USBCKSELR, 0, 2),
- CFG_MUX(MUX_FMC, RCC_FMCCKSELR, 0, 2),
- CFG_MUX(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
- CFG_MUX(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3),
- CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
+ CFG_MUX_SAFE(MUX_FMC, RCC_FMCCKSELR, 0, 2),
+ CFG_MUX_SAFE(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
+ CFG_MUX_SAFE(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3),
+ CFG_MUX_SAFE(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
};
struct clk_stm32_securiy {
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Don't register a clock if this clock is secured.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 4 +
drivers/clk/stm32/clk-stm32-core.h | 22 +++--
drivers/clk/stm32/clk-stm32mp13.c | 152 ++++++++++++++++++++++++++++-
3 files changed, 164 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index 69e40c152d2f..70014c15d15f 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -46,6 +46,10 @@ static int stm32_rcc_clock_init(struct device *dev,
const struct clock_config *cfg_clock = &data->tab_clocks[n];
struct clk_hw *hw = ERR_PTR(-ENOENT);
+ if (data->check_security &&
+ data->check_security(base, cfg_clock))
+ continue;
+
if (cfg_clock->func)
hw = (*cfg_clock->func)(dev, data, base, &rlock,
cfg_clock);
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index 6c5c8c08ecbf..5f4c81cce170 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -46,6 +46,7 @@ struct stm32_composite_cfg {
struct clock_config {
unsigned long id;
+ int sec_id;
void *clock_cfg;
struct clk_hw *(*func)(struct device *dev,
@@ -69,6 +70,8 @@ struct stm32_rcc_match_data {
unsigned int maxbinding;
struct clk_stm32_clock_data *clock_data;
u32 clear_offset;
+ int (*check_security)(void __iomem *base,
+ const struct clock_config *cfg);
};
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
@@ -157,25 +160,26 @@ struct clk_hw *clk_stm32_composite_register(struct device *dev,
spinlock_t *lock,
const struct clock_config *cfg);
-#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
+#define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
{\
.id = (_binding),\
+ .sec_id = (_sec_id),\
.clock_cfg = (_struct) {_clk},\
.func = (_register),\
}
-#define STM32_MUX_CFG(_binding, _clk)\
- STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\
+#define STM32_MUX_CFG(_binding, _clk, _sec_id)\
+ STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
&clk_stm32_mux_register)
-#define STM32_GATE_CFG(_binding, _clk)\
- STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_gate *,\
+#define STM32_GATE_CFG(_binding, _clk, _sec_id)\
+ STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
&clk_stm32_gate_register)
-#define STM32_DIV_CFG(_binding, _clk)\
- STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_div *,\
+#define STM32_DIV_CFG(_binding, _clk, _sec_id)\
+ STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
&clk_stm32_div_register)
-#define STM32_COMPOSITE_CFG(_binding, _clk)\
- STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_composite *,\
+#define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
+ STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
&clk_stm32_composite_register)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index af9518a0d262..7c5ae2dada4a 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -400,6 +400,131 @@ static const struct stm32_mux_cfg stm32mp13_muxes[] = {
CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
};
+struct clk_stm32_securiy {
+ u32 offset;
+ u8 bit_idx;
+ unsigned long scmi_id;
+};
+
+enum security_clk {
+ SECF_NONE,
+ SECF_LPTIM2,
+ SECF_LPTIM3,
+ SECF_VREF,
+ SECF_DCMIPP,
+ SECF_USBPHY,
+ SECF_TZC,
+ SECF_ETZPC,
+ SECF_IWDG1,
+ SECF_BSEC,
+ SECF_STGENC,
+ SECF_STGENRO,
+ SECF_USART1,
+ SECF_USART2,
+ SECF_SPI4,
+ SECF_SPI5,
+ SECF_I2C3,
+ SECF_I2C4,
+ SECF_I2C5,
+ SECF_TIM12,
+ SECF_TIM13,
+ SECF_TIM14,
+ SECF_TIM15,
+ SECF_TIM16,
+ SECF_TIM17,
+ SECF_DMA3,
+ SECF_DMAMUX2,
+ SECF_ADC1,
+ SECF_ADC2,
+ SECF_USBO,
+ SECF_TSC,
+ SECF_PKA,
+ SECF_SAES,
+ SECF_CRYP1,
+ SECF_HASH1,
+ SECF_RNG1,
+ SECF_BKPSRAM,
+ SECF_MCE,
+ SECF_FMC,
+ SECF_QSPI,
+ SECF_SDMMC1,
+ SECF_SDMMC2,
+ SECF_ETH1CK,
+ SECF_ETH1TX,
+ SECF_ETH1RX,
+ SECF_ETH1MAC,
+ SECF_ETH1STP,
+ SECF_ETH2CK,
+ SECF_ETH2TX,
+ SECF_ETH2RX,
+ SECF_ETH2MAC,
+ SECF_ETH2STP,
+ SECF_MCO1,
+ SECF_MCO2
+};
+
+#define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\
+ .offset = _offset,\
+ .bit_idx = _bit_idx,\
+ .scmi_id = -1,\
+}
+
+static const struct clk_stm32_securiy stm32mp13_security[] = {
+ SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
+ SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
+ SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
+ SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
+ SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
+ SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
+ SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
+ SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
+ SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
+ SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
+ SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
+ SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
+ SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
+ SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
+ SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
+ SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
+ SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
+ SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
+ SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
+ SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
+ SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
+ SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
+ SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
+ SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
+ SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
+ SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
+ SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
+ SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
+ SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
+ SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
+ SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
+ SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
+ SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
+ SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
+ SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
+ SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
+ SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
+ SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
+ SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
+ SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
+ SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
+ SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
+ SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
+ SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
+ SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
+ SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
+ SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
+ SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
+ SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
+ SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
+ SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
+ SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC),
+ SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC),
+};
+
static const char * const eth12_src[] = {
"pll4_p", "pll3_q"
};
@@ -448,13 +573,29 @@ static struct clk_stm32_composite ck_mco2 = {
};
static const struct clock_config stm32mp13_clock_cfg[] = {
- STM32_MUX_CFG(NO_ID, ck_ker_eth1),
- STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
- STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k),
- STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1),
- STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2),
+ STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
+ STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
+ STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
+ STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1),
+ STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2),
};
+static int stm32mp13_clock_is_provided_by_secure(void __iomem *base,
+ const struct clock_config *cfg)
+{
+ int sec_id = cfg->sec_id;
+
+ if (sec_id != SECF_NONE) {
+ const struct clk_stm32_securiy *secf;
+
+ secf = &stm32mp13_security[sec_id];
+
+ return !!(readl(base + secf->offset) & BIT(secf->bit_idx));
+ }
+
+ return 0;
+}
+
static u16 stm32mp13_cpt_gate[GATE_NB];
static struct clk_stm32_clock_data stm32mp13_clock_data = {
@@ -468,6 +609,7 @@ static const struct stm32_rcc_match_data stm32mp13_data = {
.tab_clocks = stm32mp13_clock_cfg,
.num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
.clock_data = &stm32mp13_clock_data,
+ .check_security = &stm32mp13_clock_is_provided_by_secure,
.maxbinding = STM32MP1_LAST_CLK,
.clear_offset = RCC_CLR_OFFSET,
};
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Just to introduce management of a stm32 gate clock.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 122 +++++++++++++++++++++++++++++
drivers/clk/stm32/clk-stm32-core.h | 21 +++++
drivers/clk/stm32/clk-stm32mp13.c | 6 ++
3 files changed, 149 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index 98699093eb21..ca2605da873d 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -124,6 +124,57 @@ static int stm32_mux_set_parent(void __iomem *base,
return 0;
}
+static void stm32_gate_endisable(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 gate_id, int enable)
+{
+ const struct stm32_gate_cfg *gate = &data->gates[gate_id];
+ void __iomem *addr = base + gate->offset;
+
+ if (enable) {
+ if (data->gate_cpt[gate_id]++ > 0)
+ return;
+
+ if (gate->set_clr != 0)
+ writel(BIT(gate->bit_idx), addr);
+ else
+ writel(readl(addr) | BIT(gate->bit_idx), addr);
+ } else {
+ if (--data->gate_cpt[gate_id] > 0)
+ return;
+
+ if (gate->set_clr != 0)
+ writel(BIT(gate->bit_idx), addr + gate->set_clr);
+ else
+ writel(readl(addr) & ~BIT(gate->bit_idx), addr);
+ }
+}
+
+static void stm32_gate_disable_unused(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 gate_id)
+{
+ const struct stm32_gate_cfg *gate = &data->gates[gate_id];
+ void __iomem *addr = base + gate->offset;
+
+ if (data->gate_cpt[gate_id] > 0)
+ return;
+
+ if (gate->set_clr != 0)
+ writel(BIT(gate->bit_idx), addr + gate->set_clr);
+ else
+ writel(readl(addr) & ~BIT(gate->bit_idx), addr);
+}
+
+static int stm32_gate_is_enabled(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 gate_id)
+{
+ const struct stm32_gate_cfg *gate = &data->gates[gate_id];
+
+ return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
+}
+
static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
{
struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
@@ -150,6 +201,56 @@ const struct clk_ops clk_stm32_mux_ops = {
.set_parent = clk_stm32_mux_set_parent,
};
+static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
+
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_stm32_gate_enable(struct clk_hw *hw)
+{
+ clk_stm32_gate_endisable(hw, 1);
+
+ return 0;
+}
+
+static void clk_stm32_gate_disable(struct clk_hw *hw)
+{
+ clk_stm32_gate_endisable(hw, 0);
+}
+
+static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
+{
+ struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
+
+ return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
+}
+
+static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
+{
+ struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
+
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+const struct clk_ops clk_stm32_gate_ops = {
+ .enable = clk_stm32_gate_enable,
+ .disable = clk_stm32_gate_disable,
+ .is_enabled = clk_stm32_gate_is_enabled,
+ .disable_unused = clk_stm32_gate_disable_unused,
+};
+
struct clk_hw *clk_stm32_mux_register(struct device *dev,
const struct stm32_rcc_match_data *data,
void __iomem *base,
@@ -170,3 +271,24 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev,
return hw;
}
+
+struct clk_hw *clk_stm32_gate_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg)
+{
+ struct clk_stm32_gate *gate = cfg->clock_cfg;
+ struct clk_hw *hw = &gate->hw;
+ int err;
+
+ gate->base = base;
+ gate->lock = lock;
+ gate->clock_data = data->clock_data;
+
+ err = clk_hw_register(dev, hw);
+ if (err)
+ return ERR_PTR(err);
+
+ return hw;
+}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index 8563e6e1c91a..f958ef610f72 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -94,8 +94,19 @@ struct clk_stm32_mux {
#define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
+struct clk_stm32_gate {
+ u16 gate_id;
+ struct clk_hw hw;
+ void __iomem *base;
+ struct clk_stm32_clock_data *clock_data;
+ spinlock_t *lock; /* spin lock */
+};
+
+#define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
+
/* Clock operators */
extern const struct clk_ops clk_stm32_mux_ops;
+extern const struct clk_ops clk_stm32_gate_ops;
/* Clock registering */
struct clk_hw *clk_stm32_mux_register(struct device *dev,
@@ -104,6 +115,12 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev,
spinlock_t *lock,
const struct clock_config *cfg);
+struct clk_hw *clk_stm32_gate_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg);
+
#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
{\
.id = (_binding),\
@@ -114,3 +131,7 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev,
#define STM32_MUX_CFG(_binding, _clk)\
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\
&clk_stm32_mux_register)
+
+#define STM32_GATE_CFG(_binding, _clk)\
+ STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_gate *,\
+ &clk_stm32_gate_register)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 40568a676111..55326d4d34dd 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -410,8 +410,14 @@ static struct clk_stm32_mux ck_ker_eth1 = {
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
};
+static struct clk_stm32_gate eth1ck_k = {
+ .gate_id = GATE_ETH1CK,
+ .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
+};
+
static const struct clock_config stm32mp13_clock_cfg[] = {
STM32_MUX_CFG(NO_ID, ck_ker_eth1),
+ STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
};
static u16 stm32mp13_cpt_gate[GATE_NB];
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Enables Reset and Clocks Controller on STM32MP13
Signed-off-by: Gabriel Fernandez <[email protected]>
---
arch/arm/boot/dts/stm32mp131.dtsi | 107 +++++++++++------------------
arch/arm/boot/dts/stm32mp133.dtsi | 4 +-
arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +-
3 files changed, 46 insertions(+), 68 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index 78eac53224d4..d7300b00ec19 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -4,6 +4,8 @@
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
@@ -64,54 +66,8 @@ scmi_reset: protocol@16 {
};
};
};
- clocks {
- clk_axi: clk-axi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <266500000>;
- };
-
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_pclk3: clk-pclk3 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <104438965>;
- };
- clk_pclk4: clk-pclk4 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <133250000>;
- };
-
- clk_pll4_p: clk-pll4_p {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- clk_pll4_r: clk-pll4_r {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <99000000>;
- };
+ clocks {
};
intc: interrupt-controller@a0021000 {
@@ -148,7 +104,8 @@ uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_hsi>;
+ clocks = <&rcc UART4_K>;
+ resets = <&rcc UART4_R>;
status = "disabled";
};
@@ -163,7 +120,8 @@ dma1: dma-controller@48000000 {
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -180,7 +138,8 @@ dma2: dma-controller@48001000 {
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -189,13 +148,29 @@ dma2: dma-controller@48001000 {
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x40>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMAMUX1>;
+ resets = <&rcc DMAMUX1_R>;
#dma-cells = <3>;
dma-masters = <&dma1 &dma2>;
dma-requests = <128>;
dma-channels = <16>;
};
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@@ -206,14 +181,14 @@ exti: interrupt-controller@5000d000 {
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
- clocks = <&clk_pclk3>;
+ clocks = <&rcc SYSCFG>;
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
@@ -225,8 +200,9 @@ sdmmc1: mmc@58005000 {
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&clk_pll4_p>;
+ clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@@ -239,8 +215,9 @@ sdmmc2: mmc@58007000 {
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&clk_pll4_p>;
+ clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@@ -250,7 +227,7 @@ sdmmc2: mmc@58007000 {
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
- clocks = <&clk_pclk4>, <&clk_lsi>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
@@ -289,7 +266,7 @@ gpioa: gpio@50002000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
@@ -301,7 +278,7 @@ gpiob: gpio@50003000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
@@ -313,7 +290,7 @@ gpioc: gpio@50004000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
@@ -325,7 +302,7 @@ gpiod: gpio@50005000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
@@ -337,7 +314,7 @@ gpioe: gpio@50006000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
@@ -349,7 +326,7 @@ gpiof: gpio@50007000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
@@ -361,7 +338,7 @@ gpiog: gpio@50008000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
@@ -373,7 +350,7 @@ gpioh: gpio@50009000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
@@ -385,7 +362,7 @@ gpioi: gpio@5000a000 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index 0fb1386257cf..531c263c9f46 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -15,7 +15,7 @@ m_can1: can@4400e000 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&clk_hse>, <&clk_pll4_r>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@@ -28,7 +28,7 @@ m_can2: can@4400f000 {
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&clk_hse>, <&clk_pll4_r>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index fa6889e30591..4d00e7592882 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -10,7 +10,8 @@ cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_axi>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Just to introduce management of stm32 composite clock.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 174 +++++++++++++++++++++++++++++
drivers/clk/stm32/clk-stm32-core.h | 23 ++++
drivers/clk/stm32/clk-stm32mp13.c | 28 +++++
3 files changed, 225 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index da38eca2b8c5..69e40c152d2f 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -389,6 +389,159 @@ const struct clk_ops clk_stm32_divider_ops = {
.set_rate = clk_stm32_divider_set_rate,
};
+static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ unsigned long flags = 0;
+ int ret;
+
+ if (composite->div_id == NO_STM32_DIV)
+ return rate;
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ ret = stm32_divider_set_rate(composite->base, composite->clock_data,
+ composite->div_id, rate, parent_rate);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+
+ return ret;
+}
+
+static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ if (composite->div_id == NO_STM32_DIV)
+ return parent_rate;
+
+ return stm32_divider_get_rate(composite->base, composite->clock_data,
+ composite->div_id, parent_rate);
+}
+
+static long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ const struct stm32_div_cfg *divider;
+
+ if (composite->div_id == NO_STM32_DIV)
+ return rate;
+
+ divider = &composite->clock_data->dividers[composite->div_id];
+
+ /* if read only, just return current value */
+ if (divider->flags & CLK_DIVIDER_READ_ONLY) {
+ u32 val;
+
+ val = readl(composite->base + divider->offset) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_ro_round_rate(hw, rate, prate, divider->table,
+ divider->width, divider->flags,
+ val);
+ }
+
+ return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
+ rate, prate, divider->table,
+ divider->width, divider->flags);
+}
+
+static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
+}
+
+static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+
+ return 0;
+}
+
+static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ if (composite->gate_id == NO_STM32_GATE)
+ return (__clk_get_enable_count(hw->clk) > 0);
+
+ return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
+}
+
+static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+}
+
+static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ if (composite->gate_id == NO_STM32_GATE)
+ return 0;
+
+ clk_stm32_composite_gate_endisable(hw, 1);
+
+ return 0;
+}
+
+static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+
+ if (composite->gate_id == NO_STM32_GATE)
+ return;
+
+ clk_stm32_composite_gate_endisable(hw, 0);
+}
+
+static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
+{
+ struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
+ unsigned long flags = 0;
+
+ if (composite->gate_id == NO_STM32_GATE)
+ return;
+
+ spin_lock_irqsave(composite->lock, flags);
+
+ stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
+
+ spin_unlock_irqrestore(composite->lock, flags);
+}
+
+const struct clk_ops clk_stm32_composite_ops = {
+ .set_rate = clk_stm32_composite_set_rate,
+ .recalc_rate = clk_stm32_composite_recalc_rate,
+ .round_rate = clk_stm32_composite_round_rate,
+ .get_parent = clk_stm32_composite_get_parent,
+ .set_parent = clk_stm32_composite_set_parent,
+ .enable = clk_stm32_composite_gate_enable,
+ .disable = clk_stm32_composite_gate_disable,
+ .is_enabled = clk_stm32_composite_is_enabled,
+ .disable_unused = clk_stm32_composite_disable_unused,
+};
+
struct clk_hw *clk_stm32_mux_register(struct device *dev,
const struct stm32_rcc_match_data *data,
void __iomem *base,
@@ -451,3 +604,24 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
return hw;
}
+
+struct clk_hw *clk_stm32_composite_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg)
+{
+ struct clk_stm32_composite *composite = cfg->clock_cfg;
+ struct clk_hw *hw = &composite->hw;
+ int err;
+
+ composite->base = base;
+ composite->lock = lock;
+ composite->clock_data = data->clock_data;
+
+ err = clk_hw_register(dev, hw);
+ if (err)
+ return ERR_PTR(err);
+
+ return hw;
+}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index c2de58a22aa8..6c5c8c08ecbf 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -114,10 +114,23 @@ struct clk_stm32_div {
#define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
+struct clk_stm32_composite {
+ u16 gate_id;
+ u16 mux_id;
+ u16 div_id;
+ struct clk_hw hw;
+ void __iomem *base;
+ struct clk_stm32_clock_data *clock_data;
+ spinlock_t *lock; /* spin lock */
+};
+
+#define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
+
/* Clock operators */
extern const struct clk_ops clk_stm32_mux_ops;
extern const struct clk_ops clk_stm32_gate_ops;
extern const struct clk_ops clk_stm32_divider_ops;
+extern const struct clk_ops clk_stm32_composite_ops;
/* Clock registering */
struct clk_hw *clk_stm32_mux_register(struct device *dev,
@@ -138,6 +151,12 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
spinlock_t *lock,
const struct clock_config *cfg);
+struct clk_hw *clk_stm32_composite_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg);
+
#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
{\
.id = (_binding),\
@@ -156,3 +175,7 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
#define STM32_DIV_CFG(_binding, _clk)\
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_div *,\
&clk_stm32_div_register)
+
+#define STM32_COMPOSITE_CFG(_binding, _clk)\
+ STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_composite *,\
+ &clk_stm32_composite_register)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index d93d92b5fe82..af9518a0d262 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -404,6 +404,14 @@ static const char * const eth12_src[] = {
"pll4_p", "pll3_q"
};
+static const char * const mco1_src[] = {
+ "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
+};
+
+static const char * const mco2_src[] = {
+ "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
+};
+
static struct clk_stm32_mux ck_ker_eth1 = {
.mux_id = MUX_ETH1,
.hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
@@ -421,10 +429,30 @@ static struct clk_stm32_div eth1ptp_k = {
CLK_SET_RATE_NO_REPARENT),
};
+static struct clk_stm32_composite ck_mco1 = {
+ .gate_id = GATE_MCO1,
+ .mux_id = MUX_MCO1,
+ .div_id = DIV_MCO1,
+ .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops,
+ CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
+ CLK_IGNORE_UNUSED),
+};
+
+static struct clk_stm32_composite ck_mco2 = {
+ .gate_id = GATE_MCO2,
+ .mux_id = MUX_MCO2,
+ .div_id = DIV_MCO2,
+ .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops,
+ CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
+ CLK_IGNORE_UNUSED),
+};
+
static const struct clock_config stm32mp13_clock_cfg[] = {
STM32_MUX_CFG(NO_ID, ck_ker_eth1),
STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k),
+ STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1),
+ STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2),
};
static u16 stm32mp13_cpt_gate[GATE_NB];
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Just to introduce management of a stm32 mux clock.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 79 ++++++++++++++++++++++++++++++
drivers/clk/stm32/clk-stm32-core.h | 24 +++++++++
drivers/clk/stm32/clk-stm32mp13.c | 11 +++++
3 files changed, 114 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index 0fab4a5a8c66..98699093eb21 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -91,3 +91,82 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
return 0;
}
+
+static u8 stm32_mux_get_parent(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 mux_id)
+{
+ const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
+ u32 mask = BIT(mux->width) - 1;
+ u32 val;
+
+ val = readl(base + mux->offset) >> mux->shift;
+ val &= mask;
+
+ return val;
+}
+
+static int stm32_mux_set_parent(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 mux_id, u8 index)
+{
+ const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
+
+ u32 mask = BIT(mux->width) - 1;
+ u32 reg = readl(base + mux->offset);
+ u32 val = index << mux->shift;
+
+ reg &= ~(mask << mux->shift);
+ reg |= val;
+
+ writel(reg, base + mux->offset);
+
+ return 0;
+}
+
+static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
+{
+ struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
+
+ return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
+}
+
+static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
+ unsigned long flags = 0;
+
+ spin_lock_irqsave(mux->lock, flags);
+
+ stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
+
+ spin_unlock_irqrestore(mux->lock, flags);
+
+ return 0;
+}
+
+const struct clk_ops clk_stm32_mux_ops = {
+ .get_parent = clk_stm32_mux_get_parent,
+ .set_parent = clk_stm32_mux_set_parent,
+};
+
+struct clk_hw *clk_stm32_mux_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg)
+{
+ struct clk_stm32_mux *mux = cfg->clock_cfg;
+ struct clk_hw *hw = &mux->hw;
+ int err;
+
+ mux->base = base;
+ mux->lock = lock;
+ mux->clock_data = data->clock_data;
+
+ err = clk_hw_register(dev, hw);
+ if (err)
+ return ERR_PTR(err);
+
+ return hw;
+}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index 519723ae97eb..8563e6e1c91a 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -83,10 +83,34 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
/* DIV define */
#define DIV_NO_RDY 0xFF
+/* Definition of clock structure */
+struct clk_stm32_mux {
+ u16 mux_id;
+ struct clk_hw hw;
+ void __iomem *base;
+ struct clk_stm32_clock_data *clock_data;
+ spinlock_t *lock; /* spin lock */
+};
+
+#define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
+
+/* Clock operators */
+extern const struct clk_ops clk_stm32_mux_ops;
+
/* Clock registering */
+struct clk_hw *clk_stm32_mux_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg);
+
#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
{\
.id = (_binding),\
.clock_cfg = (_struct) {_clk},\
.func = (_register),\
}
+
+#define STM32_MUX_CFG(_binding, _clk)\
+ STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_mux *,\
+ &clk_stm32_mux_register)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index a2a6bbb4ace5..40568a676111 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -400,7 +400,18 @@ static const struct stm32_mux_cfg stm32mp13_muxes[] = {
CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
};
+static const char * const eth12_src[] = {
+ "pll4_p", "pll3_q"
+};
+
+static struct clk_stm32_mux ck_ker_eth1 = {
+ .mux_id = MUX_ETH1,
+ .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
+ CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
+};
+
static const struct clock_config stm32mp13_clock_cfg[] = {
+ STM32_MUX_CFG(NO_ID, ck_ker_eth1),
};
static u16 stm32mp13_cpt_gate[GATE_NB];
--
2.25.1
From: Gabriel Fernandez <[email protected]>
All peripheral clocks are mainly based on stm32_gate clock.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32mp13.c | 360 ++++++++++++++++++++++++++++++
1 file changed, 360 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 7c5ae2dada4a..b543474d5074 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -537,6 +537,303 @@ static const char * const mco2_src[] = {
"ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
};
+/* Timer clocks */
+static struct clk_stm32_gate tim2_k = {
+ .gate_id = GATE_TIM2,
+ .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim3_k = {
+ .gate_id = GATE_TIM3,
+ .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim4_k = {
+ .gate_id = GATE_TIM4,
+ .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim5_k = {
+ .gate_id = GATE_TIM5,
+ .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim6_k = {
+ .gate_id = GATE_TIM6,
+ .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim7_k = {
+ .gate_id = GATE_TIM7,
+ .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim1_k = {
+ .gate_id = GATE_TIM1,
+ .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim8_k = {
+ .gate_id = GATE_TIM8,
+ .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim12_k = {
+ .gate_id = GATE_TIM12,
+ .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim13_k = {
+ .gate_id = GATE_TIM13,
+ .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim14_k = {
+ .gate_id = GATE_TIM14,
+ .hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim15_k = {
+ .gate_id = GATE_TIM15,
+ .hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim16_k = {
+ .gate_id = GATE_TIM16,
+ .hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+static struct clk_stm32_gate tim17_k = {
+ .gate_id = GATE_TIM17,
+ .hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
+};
+
+/* Peripheral clocks */
+static struct clk_stm32_gate sai1 = {
+ .gate_id = GATE_SAI1,
+ .hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate sai2 = {
+ .gate_id = GATE_SAI2,
+ .hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate syscfg = {
+ .gate_id = GATE_SYSCFG,
+ .hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate vref = {
+ .gate_id = GATE_VREF,
+ .hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dts = {
+ .gate_id = GATE_DTS,
+ .hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate pmbctrl = {
+ .gate_id = GATE_PMBCTRL,
+ .hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate hdp = {
+ .gate_id = GATE_HDP,
+ .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate iwdg2 = {
+ .gate_id = GATE_IWDG2APB,
+ .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate stgenro = {
+ .gate_id = GATE_STGENRO,
+ .hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpioa = {
+ .gate_id = GATE_GPIOA,
+ .hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpiob = {
+ .gate_id = GATE_GPIOB,
+ .hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpioc = {
+ .gate_id = GATE_GPIOC,
+ .hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpiod = {
+ .gate_id = GATE_GPIOD,
+ .hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpioe = {
+ .gate_id = GATE_GPIOE,
+ .hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpiof = {
+ .gate_id = GATE_GPIOF,
+ .hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpiog = {
+ .gate_id = GATE_GPIOG,
+ .hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpioh = {
+ .gate_id = GATE_GPIOH,
+ .hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate gpioi = {
+ .gate_id = GATE_GPIOI,
+ .hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate tsc = {
+ .gate_id = GATE_TSC,
+ .hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate ddrperfm = {
+ .gate_id = GATE_DDRPERFM,
+ .hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate tzpc = {
+ .gate_id = GATE_TZC,
+ .hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate iwdg1 = {
+ .gate_id = GATE_IWDG1APB,
+ .hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate bsec = {
+ .gate_id = GATE_BSEC,
+ .hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dma1 = {
+ .gate_id = GATE_DMA1,
+ .hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dma2 = {
+ .gate_id = GATE_DMA2,
+ .hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dmamux1 = {
+ .gate_id = GATE_DMAMUX1,
+ .hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dma3 = {
+ .gate_id = GATE_DMA3,
+ .hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate dmamux2 = {
+ .gate_id = GATE_DMAMUX2,
+ .hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate adc1 = {
+ .gate_id = GATE_ADC1,
+ .hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate adc2 = {
+ .gate_id = GATE_ADC2,
+ .hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate pka = {
+ .gate_id = GATE_PKA,
+ .hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate cryp1 = {
+ .gate_id = GATE_CRYP1,
+ .hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate hash1 = {
+ .gate_id = GATE_HASH1,
+ .hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate bkpsram = {
+ .gate_id = GATE_BKPSRAM,
+ .hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate mdma = {
+ .gate_id = GATE_MDMA,
+ .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth1tx = {
+ .gate_id = GATE_ETH1TX,
+ .hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth1rx = {
+ .gate_id = GATE_ETH1RX,
+ .hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth1mac = {
+ .gate_id = GATE_ETH1MAC,
+ .hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth2tx = {
+ .gate_id = GATE_ETH2TX,
+ .hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth2rx = {
+ .gate_id = GATE_ETH2RX,
+ .hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth2mac = {
+ .gate_id = GATE_ETH2MAC,
+ .hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate crc1 = {
+ .gate_id = GATE_CRC1,
+ .hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate usbh = {
+ .gate_id = GATE_USBH,
+ .hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth1stp = {
+ .gate_id = GATE_ETH1STP,
+ .hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate eth2stp = {
+ .gate_id = GATE_ETH2STP,
+ .hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
+};
+
static struct clk_stm32_mux ck_ker_eth1 = {
.mux_id = MUX_ETH1,
.hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
@@ -573,6 +870,69 @@ static struct clk_stm32_composite ck_mco2 = {
};
static const struct clock_config stm32mp13_clock_cfg[] = {
+ /* Timer clocks */
+ STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
+ STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
+ STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
+ STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
+ STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
+ STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
+ STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
+ STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
+ STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
+ STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
+ STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
+ STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
+ STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
+ STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
+
+ /* Peripheral clocks */
+ STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
+ STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
+ STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
+ STM32_GATE_CFG(VREF, vref, SECF_VREF),
+ STM32_GATE_CFG(DTS, dts, SECF_NONE),
+ STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
+ STM32_GATE_CFG(HDP, hdp, SECF_NONE),
+ STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
+ STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
+ STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
+ STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
+ STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
+ STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
+ STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
+ STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
+ STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
+ STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
+ STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
+ STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
+ STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
+ STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
+ STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
+ STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
+ STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
+ STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
+ STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
+ STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
+ STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
+ STM32_GATE_CFG(TSC, tsc, SECF_TZC),
+ STM32_GATE_CFG(PKA, pka, SECF_PKA),
+ STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
+ STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
+ STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
+ STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
+ STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
+ STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
+ STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
+ STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
+ STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
+ STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
+ STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
+ STM32_GATE_CFG(USBH, usbh, SECF_NONE),
+ STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
+ STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
+ STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
+
STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
--
2.25.1
From: Gabriel Fernandez <[email protected]>
Just to introduce management of a stm32 divider clock
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/stm32/clk-stm32-core.c | 159 +++++++++++++++++++++++++++++
drivers/clk/stm32/clk-stm32-core.h | 21 ++++
drivers/clk/stm32/clk-stm32mp13.c | 7 ++
3 files changed, 187 insertions(+)
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index ca2605da873d..da38eca2b8c5 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -175,6 +175,80 @@ static int stm32_gate_is_enabled(void __iomem *base,
return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
}
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flags, u8 width)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+static unsigned long stm32_divider_get_rate(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 div_id,
+ unsigned long parent_rate)
+{
+ const struct stm32_div_cfg *divider = &data->dividers[div_id];
+ unsigned int val;
+ unsigned int div;
+
+ val = readl(base + divider->offset) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+ div = _get_div(divider->table, val, divider->flags, divider->width);
+
+ if (!div) {
+ WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
+ "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+ div_id);
+ return parent_rate;
+ }
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static int stm32_divider_set_rate(void __iomem *base,
+ struct clk_stm32_clock_data *data,
+ u16 div_id, unsigned long rate,
+ unsigned long parent_rate)
+{
+ const struct stm32_div_cfg *divider = &data->dividers[div_id];
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = readl(base + divider->offset);
+ val &= ~(clk_div_mask(divider->width) << divider->shift);
+ }
+
+ val |= (u32)value << divider->shift;
+
+ writel(val, base + divider->offset);
+
+ return 0;
+}
+
static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
{
struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
@@ -251,6 +325,70 @@ const struct clk_ops clk_stm32_gate_ops = {
.disable_unused = clk_stm32_gate_disable_unused,
};
+static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_stm32_div *div = to_clk_stm32_divider(hw);
+ unsigned long flags = 0;
+ int ret;
+
+ if (div->div_id == NO_STM32_DIV)
+ return rate;
+
+ spin_lock_irqsave(div->lock, flags);
+
+ ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
+
+ spin_unlock_irqrestore(div->lock, flags);
+
+ return ret;
+}
+
+static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_stm32_div *div = to_clk_stm32_divider(hw);
+ const struct stm32_div_cfg *divider;
+
+ if (div->div_id == NO_STM32_DIV)
+ return rate;
+
+ divider = &div->clock_data->dividers[div->div_id];
+
+ /* if read only, just return current value */
+ if (divider->flags & CLK_DIVIDER_READ_ONLY) {
+ u32 val;
+
+ val = readl(div->base + divider->offset) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_ro_round_rate(hw, rate, prate, divider->table,
+ divider->width, divider->flags,
+ val);
+ }
+
+ return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
+ rate, prate, divider->table,
+ divider->width, divider->flags);
+}
+
+static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_stm32_div *div = to_clk_stm32_divider(hw);
+
+ if (div->div_id == NO_STM32_DIV)
+ return parent_rate;
+
+ return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
+}
+
+const struct clk_ops clk_stm32_divider_ops = {
+ .recalc_rate = clk_stm32_divider_recalc_rate,
+ .round_rate = clk_stm32_divider_round_rate,
+ .set_rate = clk_stm32_divider_set_rate,
+};
+
struct clk_hw *clk_stm32_mux_register(struct device *dev,
const struct stm32_rcc_match_data *data,
void __iomem *base,
@@ -292,3 +430,24 @@ struct clk_hw *clk_stm32_gate_register(struct device *dev,
return hw;
}
+
+struct clk_hw *clk_stm32_div_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg)
+{
+ struct clk_stm32_div *div = cfg->clock_cfg;
+ struct clk_hw *hw = &div->hw;
+ int err;
+
+ div->base = base;
+ div->lock = lock;
+ div->clock_data = data->clock_data;
+
+ err = clk_hw_register(dev, hw);
+ if (err)
+ return ERR_PTR(err);
+
+ return hw;
+}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
index f958ef610f72..c2de58a22aa8 100644
--- a/drivers/clk/stm32/clk-stm32-core.h
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -104,9 +104,20 @@ struct clk_stm32_gate {
#define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
+struct clk_stm32_div {
+ u16 div_id;
+ struct clk_hw hw;
+ void __iomem *base;
+ struct clk_stm32_clock_data *clock_data;
+ spinlock_t *lock; /* spin lock */
+};
+
+#define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
+
/* Clock operators */
extern const struct clk_ops clk_stm32_mux_ops;
extern const struct clk_ops clk_stm32_gate_ops;
+extern const struct clk_ops clk_stm32_divider_ops;
/* Clock registering */
struct clk_hw *clk_stm32_mux_register(struct device *dev,
@@ -121,6 +132,12 @@ struct clk_hw *clk_stm32_gate_register(struct device *dev,
spinlock_t *lock,
const struct clock_config *cfg);
+struct clk_hw *clk_stm32_div_register(struct device *dev,
+ const struct stm32_rcc_match_data *data,
+ void __iomem *base,
+ spinlock_t *lock,
+ const struct clock_config *cfg);
+
#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
{\
.id = (_binding),\
@@ -135,3 +152,7 @@ struct clk_hw *clk_stm32_gate_register(struct device *dev,
#define STM32_GATE_CFG(_binding, _clk)\
STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_gate *,\
&clk_stm32_gate_register)
+
+#define STM32_DIV_CFG(_binding, _clk)\
+ STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_div *,\
+ &clk_stm32_div_register)
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 55326d4d34dd..d93d92b5fe82 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -415,9 +415,16 @@ static struct clk_stm32_gate eth1ck_k = {
.hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
};
+static struct clk_stm32_div eth1ptp_k = {
+ .div_id = DIV_ETH1PTP,
+ .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
+ CLK_SET_RATE_NO_REPARENT),
+};
+
static const struct clock_config stm32mp13_clock_cfg[] = {
STM32_MUX_CFG(NO_ID, ck_ker_eth1),
STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
+ STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k),
};
static u16 stm32mp13_cpt_gate[GATE_NB];
--
2.25.1
Hi Gabriel,
On 3/16/22 14:09, [email protected] wrote:
> From: Gabriel Fernandez <[email protected]>
>
> v3:
> - cosmetic change from Stephen Boyd
> - rename some functions in clk-stm32-core
> - add missing static for variables or functions
>
> v2:
> - Resend because patch 9,10,12,13 has not been sent
> - add Reviewed by Krzysztof Kozlowski for patch 1
>
> Gabriel Fernandez (13):
> dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
> clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
> clk: stm32mp13: add stm32_mux clock management
> clk: stm32mp13: add stm32_gate management
> clk: stm32mp13: add stm32 divider clock
> clk: stm32mp13: add composite clock
> clk: stm32mp13: manage secured clocks
> clk: stm32mp13: add all STM32MP13 peripheral clocks
> clk: stm32mp13: add all STM32MP13 kernel clocks
> clk: stm32mp13: add multi mux function
> clk: stm32mp13: add safe mux management
> ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
> ARM: dts: stm32: add RCC on STM32MP13x SoC family
>
DT patches look good for me. I'll apply them on stm32-next as soon as
dt-bindings + drivers patch are applied.
cheers
Alex
> .../bindings/clock/st,stm32mp1-rcc.yaml | 2 +
> arch/arm/boot/dts/stm32mp131.dtsi | 128 +-
> arch/arm/boot/dts/stm32mp133.dtsi | 4 +-
> arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +-
> drivers/clk/Kconfig | 5 +
> drivers/clk/Makefile | 1 +
> drivers/clk/stm32/Makefile | 1 +
> drivers/clk/stm32/clk-stm32-core.c | 695 +++++++
> drivers/clk/stm32/clk-stm32-core.h | 188 ++
> drivers/clk/stm32/clk-stm32mp13.c | 1620 +++++++++++++++
> drivers/clk/stm32/reset-stm32.c | 122 ++
> drivers/clk/stm32/reset-stm32.h | 8 +
> drivers/clk/stm32/stm32mp13_rcc.h | 1748 +++++++++++++++++
> include/dt-bindings/clock/stm32mp13-clks.h | 229 +++
> include/dt-bindings/reset/stm32mp13-resets.h | 100 +
> 15 files changed, 4794 insertions(+), 60 deletions(-)
> create mode 100644 drivers/clk/stm32/Makefile
> create mode 100644 drivers/clk/stm32/clk-stm32-core.c
> create mode 100644 drivers/clk/stm32/clk-stm32-core.h
> create mode 100644 drivers/clk/stm32/clk-stm32mp13.c
> create mode 100644 drivers/clk/stm32/reset-stm32.c
> create mode 100644 drivers/clk/stm32/reset-stm32.h
> create mode 100644 drivers/clk/stm32/stm32mp13_rcc.h
> create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h
> create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h
>
On 3/16/22 14:10, [email protected] wrote:
> From: Gabriel Fernandez <[email protected]>
>
> Enables Reset and Clocks Controller on STM32MP13
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
> arch/arm/boot/dts/stm32mp131.dtsi | 107 +++++++++++------------------
> arch/arm/boot/dts/stm32mp133.dtsi | 4 +-
> arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +-
> 3 files changed, 46 insertions(+), 68 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
> index 78eac53224d4..d7300b00ec19 100644
> --- a/arch/arm/boot/dts/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
> @@ -4,6 +4,8 @@
> * Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
> */
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/stm32mp13-clks.h>
> +#include <dt-bindings/reset/stm32mp13-resets.h>
>
> / {
> #address-cells = <1>;
> @@ -64,54 +66,8 @@ scmi_reset: protocol@16 {
> };
> };
> };
> - clocks {
> - clk_axi: clk-axi {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <266500000>;
> - };
> -
> - clk_hse: clk-hse {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <24000000>;
> - };
> -
> - clk_hsi: clk-hsi {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <64000000>;
> - };
> -
> - clk_lsi: clk-lsi {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32000>;
> - };
> -
> - clk_pclk3: clk-pclk3 {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <104438965>;
> - };
>
> - clk_pclk4: clk-pclk4 {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <133250000>;
> - };
> -
> - clk_pll4_p: clk-pll4_p {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <50000000>;
> - };
> -
> - clk_pll4_r: clk-pll4_r {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <99000000>;
> - };
> + clocks {
> };
>
> intc: interrupt-controller@a0021000 {
> @@ -148,7 +104,8 @@ uart4: serial@40010000 {
> compatible = "st,stm32h7-uart";
> reg = <0x40010000 0x400>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk_hsi>;
> + clocks = <&rcc UART4_K>;
> + resets = <&rcc UART4_R>;
> status = "disabled";
> };
>
> @@ -163,7 +120,8 @@ dma1: dma-controller@48000000 {
> <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc DMA1>;
> + resets = <&rcc DMA1_R>;
> #dma-cells = <4>;
> st,mem2mem;
> dma-requests = <8>;
> @@ -180,7 +138,8 @@ dma2: dma-controller@48001000 {
> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc DMA2>;
> + resets = <&rcc DMA2_R>;
> #dma-cells = <4>;
> st,mem2mem;
> dma-requests = <8>;
> @@ -189,13 +148,29 @@ dma2: dma-controller@48001000 {
> dmamux1: dma-router@48002000 {
> compatible = "st,stm32h7-dmamux";
> reg = <0x48002000 0x40>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc DMAMUX1>;
> + resets = <&rcc DMAMUX1_R>;
> #dma-cells = <3>;
> dma-masters = <&dma1 &dma2>;
> dma-requests = <128>;
> dma-channels = <16>;
> };
>
> + rcc: rcc@50000000 {
> + compatible = "st,stm32mp13-rcc", "syscon";
> + reg = <0x50000000 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +
> + clock-names = "hse", "hsi", "csi", "lse", "lsi";
> +
It doesn't match with current yaml description. I'm preparing a patch to
update rcc yaml file. You will have to check that it matches with this node.
> + clocks = <&scmi_clk CK_SCMI_HSE>,
> + <&scmi_clk CK_SCMI_HSI>,
> + <&scmi_clk CK_SCMI_CSI>,
> + <&scmi_clk CK_SCMI_LSE>,
> + <&scmi_clk CK_SCMI_LSI>;
> + };
> +
> exti: interrupt-controller@5000d000 {
> compatible = "st,stm32mp13-exti", "syscon";
> interrupt-controller;
> @@ -206,14 +181,14 @@ exti: interrupt-controller@5000d000 {
> syscfg: syscon@50020000 {
> compatible = "st,stm32mp157-syscfg", "syscon";
> reg = <0x50020000 0x400>;
> - clocks = <&clk_pclk3>;
> + clocks = <&rcc SYSCFG>;
> };
>
> mdma: dma-controller@58000000 {
> compatible = "st,stm32h7-mdma";
> reg = <0x58000000 0x1000>;
> interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc MDMA>;
> #dma-cells = <5>;
> dma-channels = <32>;
> dma-requests = <48>;
> @@ -225,8 +200,9 @@ sdmmc1: mmc@58005000 {
> reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "cmd_irq";
> - clocks = <&clk_pll4_p>;
> + clocks = <&rcc SDMMC1_K>;
> clock-names = "apb_pclk";
> + resets = <&rcc SDMMC1_R>;
> cap-sd-highspeed;
> cap-mmc-highspeed;
> max-frequency = <130000000>;
> @@ -239,8 +215,9 @@ sdmmc2: mmc@58007000 {
> reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "cmd_irq";
> - clocks = <&clk_pll4_p>;
> + clocks = <&rcc SDMMC2_K>;
> clock-names = "apb_pclk";
> + resets = <&rcc SDMMC2_R>;
> cap-sd-highspeed;
> cap-mmc-highspeed;
> max-frequency = <130000000>;
> @@ -250,7 +227,7 @@ sdmmc2: mmc@58007000 {
> iwdg2: watchdog@5a002000 {
> compatible = "st,stm32mp1-iwdg";
> reg = <0x5a002000 0x400>;
> - clocks = <&clk_pclk4>, <&clk_lsi>;
> + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
> clock-names = "pclk", "lsi";
> status = "disabled";
> };
> @@ -289,7 +266,7 @@ gpioa: gpio@50002000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x0 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOA>;
> st,bank-name = "GPIOA";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 0 16>;
> @@ -301,7 +278,7 @@ gpiob: gpio@50003000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x1000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOB>;
> st,bank-name = "GPIOB";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 16 16>;
> @@ -313,7 +290,7 @@ gpioc: gpio@50004000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x2000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOC>;
> st,bank-name = "GPIOC";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 32 16>;
> @@ -325,7 +302,7 @@ gpiod: gpio@50005000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x3000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOD>;
> st,bank-name = "GPIOD";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 48 16>;
> @@ -337,7 +314,7 @@ gpioe: gpio@50006000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x4000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOE>;
> st,bank-name = "GPIOE";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 64 16>;
> @@ -349,7 +326,7 @@ gpiof: gpio@50007000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x5000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOF>;
> st,bank-name = "GPIOF";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 80 16>;
> @@ -361,7 +338,7 @@ gpiog: gpio@50008000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x6000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOG>;
> st,bank-name = "GPIOG";
> ngpios = <16>;
> gpio-ranges = <&pinctrl 0 96 16>;
> @@ -373,7 +350,7 @@ gpioh: gpio@50009000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x7000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOH>;
> st,bank-name = "GPIOH";
> ngpios = <15>;
> gpio-ranges = <&pinctrl 0 112 15>;
> @@ -385,7 +362,7 @@ gpioi: gpio@5000a000 {
> interrupt-controller;
> #interrupt-cells = <2>;
> reg = <0x8000 0x400>;
> - clocks = <&clk_pclk4>;
> + clocks = <&rcc GPIOI>;
> st,bank-name = "GPIOI";
> ngpios = <8>;
> gpio-ranges = <&pinctrl 0 128 8>;
> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
> index 0fb1386257cf..531c263c9f46 100644
> --- a/arch/arm/boot/dts/stm32mp133.dtsi
> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
> @@ -15,7 +15,7 @@ m_can1: can@4400e000 {
> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "int0", "int1";
> - clocks = <&clk_hse>, <&clk_pll4_r>;
> + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
> clock-names = "hclk", "cclk";
> bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
> status = "disabled";
> @@ -28,7 +28,7 @@ m_can2: can@4400f000 {
> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "int0", "int1";
> - clocks = <&clk_hse>, <&clk_pll4_r>;
> + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
> clock-names = "hclk", "cclk";
> bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
> status = "disabled";
> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
> index fa6889e30591..4d00e7592882 100644
> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
> @@ -10,7 +10,8 @@ cryp: crypto@54002000 {
> compatible = "st,stm32mp1-cryp";
> reg = <0x54002000 0x400>;
> interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk_axi>;
> + clocks = <&rcc CRYP1>;
> + resets = <&rcc CRYP1_R>;
> status = "disabled";
> };
> };
On 4/21/22 17:26, Alexandre TORGUE wrote:
> On 3/16/22 14:10, [email protected] wrote:
>> From: Gabriel Fernandez <[email protected]>
>>
>> Enables Reset and Clocks Controller on STM32MP13
>>
>> Signed-off-by: Gabriel Fernandez <[email protected]>
>> ---
>> arch/arm/boot/dts/stm32mp131.dtsi | 107 +++++++++++------------------
>> arch/arm/boot/dts/stm32mp133.dtsi | 4 +-
>> arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +-
>> 3 files changed, 46 insertions(+), 68 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi
>> b/arch/arm/boot/dts/stm32mp131.dtsi
>> index 78eac53224d4..d7300b00ec19 100644
>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>> @@ -4,6 +4,8 @@
>> * Author: Alexandre Torgue <[email protected]> for
>> STMicroelectronics.
>> */
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/stm32mp13-clks.h>
>> +#include <dt-bindings/reset/stm32mp13-resets.h>
>> / {
>> #address-cells = <1>;
>> @@ -64,54 +66,8 @@ scmi_reset: protocol@16 {
>> };
>> };
>> };
>> - clocks {
>> - clk_axi: clk-axi {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <266500000>;
>> - };
>> -
>> - clk_hse: clk-hse {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <24000000>;
>> - };
>> -
>> - clk_hsi: clk-hsi {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <64000000>;
>> - };
>> -
>> - clk_lsi: clk-lsi {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <32000>;
>> - };
>> -
>> - clk_pclk3: clk-pclk3 {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <104438965>;
>> - };
>> - clk_pclk4: clk-pclk4 {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <133250000>;
>> - };
>> -
>> - clk_pll4_p: clk-pll4_p {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <50000000>;
>> - };
>> -
>> - clk_pll4_r: clk-pll4_r {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <99000000>;
>> - };
>> + clocks {
>> };
>> intc: interrupt-controller@a0021000 {
>> @@ -148,7 +104,8 @@ uart4: serial@40010000 {
>> compatible = "st,stm32h7-uart";
>> reg = <0x40010000 0x400>;
>> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&clk_hsi>;
>> + clocks = <&rcc UART4_K>;
>> + resets = <&rcc UART4_R>;
>> status = "disabled";
>> };
>> @@ -163,7 +120,8 @@ dma1: dma-controller@48000000 {
>> <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc DMA1>;
>> + resets = <&rcc DMA1_R>;
>> #dma-cells = <4>;
>> st,mem2mem;
>> dma-requests = <8>;
>> @@ -180,7 +138,8 @@ dma2: dma-controller@48001000 {
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc DMA2>;
>> + resets = <&rcc DMA2_R>;
>> #dma-cells = <4>;
>> st,mem2mem;
>> dma-requests = <8>;
>> @@ -189,13 +148,29 @@ dma2: dma-controller@48001000 {
>> dmamux1: dma-router@48002000 {
>> compatible = "st,stm32h7-dmamux";
>> reg = <0x48002000 0x40>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc DMAMUX1>;
>> + resets = <&rcc DMAMUX1_R>;
>> #dma-cells = <3>;
>> dma-masters = <&dma1 &dma2>;
>> dma-requests = <128>;
>> dma-channels = <16>;
>> };
>> + rcc: rcc@50000000 {
>> + compatible = "st,stm32mp13-rcc", "syscon";
>> + reg = <0x50000000 0x1000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> +
>> + clock-names = "hse", "hsi", "csi", "lse", "lsi";
>> +
>
> It doesn't match with current yaml description. I'm preparing a patch
> to update rcc yaml file. You will have to check that it matches with
> this node.
>
ok
Thank's Alex
>> + clocks = <&scmi_clk CK_SCMI_HSE>,
>> + <&scmi_clk CK_SCMI_HSI>,
>> + <&scmi_clk CK_SCMI_CSI>,
>> + <&scmi_clk CK_SCMI_LSE>,
>> + <&scmi_clk CK_SCMI_LSI>;
>> + };
>> +
>> exti: interrupt-controller@5000d000 {
>> compatible = "st,stm32mp13-exti", "syscon";
>> interrupt-controller;
>> @@ -206,14 +181,14 @@ exti: interrupt-controller@5000d000 {
>> syscfg: syscon@50020000 {
>> compatible = "st,stm32mp157-syscfg", "syscon";
>> reg = <0x50020000 0x400>;
>> - clocks = <&clk_pclk3>;
>> + clocks = <&rcc SYSCFG>;
>> };
>> mdma: dma-controller@58000000 {
>> compatible = "st,stm32h7-mdma";
>> reg = <0x58000000 0x1000>;
>> interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc MDMA>;
>> #dma-cells = <5>;
>> dma-channels = <32>;
>> dma-requests = <48>;
>> @@ -225,8 +200,9 @@ sdmmc1: mmc@58005000 {
>> reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-names = "cmd_irq";
>> - clocks = <&clk_pll4_p>;
>> + clocks = <&rcc SDMMC1_K>;
>> clock-names = "apb_pclk";
>> + resets = <&rcc SDMMC1_R>;
>> cap-sd-highspeed;
>> cap-mmc-highspeed;
>> max-frequency = <130000000>;
>> @@ -239,8 +215,9 @@ sdmmc2: mmc@58007000 {
>> reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-names = "cmd_irq";
>> - clocks = <&clk_pll4_p>;
>> + clocks = <&rcc SDMMC2_K>;
>> clock-names = "apb_pclk";
>> + resets = <&rcc SDMMC2_R>;
>> cap-sd-highspeed;
>> cap-mmc-highspeed;
>> max-frequency = <130000000>;
>> @@ -250,7 +227,7 @@ sdmmc2: mmc@58007000 {
>> iwdg2: watchdog@5a002000 {
>> compatible = "st,stm32mp1-iwdg";
>> reg = <0x5a002000 0x400>;
>> - clocks = <&clk_pclk4>, <&clk_lsi>;
>> + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
>> clock-names = "pclk", "lsi";
>> status = "disabled";
>> };
>> @@ -289,7 +266,7 @@ gpioa: gpio@50002000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x0 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOA>;
>> st,bank-name = "GPIOA";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 0 16>;
>> @@ -301,7 +278,7 @@ gpiob: gpio@50003000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x1000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOB>;
>> st,bank-name = "GPIOB";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 16 16>;
>> @@ -313,7 +290,7 @@ gpioc: gpio@50004000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x2000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOC>;
>> st,bank-name = "GPIOC";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 32 16>;
>> @@ -325,7 +302,7 @@ gpiod: gpio@50005000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x3000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOD>;
>> st,bank-name = "GPIOD";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 48 16>;
>> @@ -337,7 +314,7 @@ gpioe: gpio@50006000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x4000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOE>;
>> st,bank-name = "GPIOE";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 64 16>;
>> @@ -349,7 +326,7 @@ gpiof: gpio@50007000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x5000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOF>;
>> st,bank-name = "GPIOF";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 80 16>;
>> @@ -361,7 +338,7 @@ gpiog: gpio@50008000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x6000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOG>;
>> st,bank-name = "GPIOG";
>> ngpios = <16>;
>> gpio-ranges = <&pinctrl 0 96 16>;
>> @@ -373,7 +350,7 @@ gpioh: gpio@50009000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x7000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOH>;
>> st,bank-name = "GPIOH";
>> ngpios = <15>;
>> gpio-ranges = <&pinctrl 0 112 15>;
>> @@ -385,7 +362,7 @@ gpioi: gpio@5000a000 {
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> reg = <0x8000 0x400>;
>> - clocks = <&clk_pclk4>;
>> + clocks = <&rcc GPIOI>;
>> st,bank-name = "GPIOI";
>> ngpios = <8>;
>> gpio-ranges = <&pinctrl 0 128 8>;
>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi
>> b/arch/arm/boot/dts/stm32mp133.dtsi
>> index 0fb1386257cf..531c263c9f46 100644
>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>> @@ -15,7 +15,7 @@ m_can1: can@4400e000 {
>> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-names = "int0", "int1";
>> - clocks = <&clk_hse>, <&clk_pll4_r>;
>> + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
>> clock-names = "hclk", "cclk";
>> bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
>> status = "disabled";
>> @@ -28,7 +28,7 @@ m_can2: can@4400f000 {
>> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>> interrupt-names = "int0", "int1";
>> - clocks = <&clk_hse>, <&clk_pll4_r>;
>> + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
>> clock-names = "hclk", "cclk";
>> bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>> status = "disabled";
>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi
>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> index fa6889e30591..4d00e7592882 100644
>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> @@ -10,7 +10,8 @@ cryp: crypto@54002000 {
>> compatible = "st,stm32mp1-cryp";
>> reg = <0x54002000 0x400>;
>> interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&clk_axi>;
>> + clocks = <&rcc CRYP1>;
>> + resets = <&rcc CRYP1_R>;
>> status = "disabled";
>> };
>> };
>