Add mmio mdio mux nodes from the on-board FPGA.
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls2080a-qds.dts | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index f6c3ee78ace0..c3caca1c0ab6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -23,3 +23,72 @@ chosen {
stdout-path = "serial0:115200n8";
};
};
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+ phy-handle = <&mdio0_phy12>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac10 {
+ phy-handle = <&mdio0_phy13>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac11 {
+ phy-handle = <&mdio0_phy14>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac12 {
+ phy-handle = <&mdio0_phy15>;
+ phy-connection-type = "sgmii";
+};
+
+&ifc {
+ boardctrl: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
+ reg = <3 0 0x300>;
+ ranges = <0 3 0 0x300>;
+
+ mdio_mux_emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&emdio1>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1_MDIO */
+
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ /* Child MDIO buses, one for each riser card:
+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+ * VSC8234 PHYs on the riser cards.
+ */
+
+ mdio_mux3: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio0_phy12: mdio_phy0@1c {
+ reg = <0x1c>;
+ };
+
+ mdio0_phy13: mdio_phy1@1d {
+ reg = <0x1d>;
+ };
+
+ mdio0_phy14: mdio_phy2@1e {
+ reg = <0x1e>;
+ };
+
+ mdio0_phy15: mdio_phy3@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+ };
+};
+
--
2.25.1
Add mmio mdio mux nodes from the on-board FPGA.
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls2088a-qds.dts | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
index 7c17b1bd4529..d36cf7f3432b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
@@ -22,3 +22,71 @@ chosen {
stdout-path = "serial0:115200n8";
};
};
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+ phy-handle = <&mdio0_phy12>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac10 {
+ phy-handle = <&mdio0_phy13>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac11 {
+ phy-handle = <&mdio0_phy14>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac12 {
+ phy-handle = <&mdio0_phy15>;
+ phy-connection-type = "sgmii";
+};
+
+&ifc {
+ boardctrl: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
+ reg = <3 0 0x300>;
+ ranges = <0 3 0 0x300>;
+
+ mdio_mux_emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&emdio1>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1_MDIO */
+
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ /* Child MDIO buses, one for each riser card:
+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+ * VSC8234 PHYs on the riser cards.
+ */
+
+ mdio_mux3: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio0_phy12: mdio_phy0@1c {
+ reg = <0x1c>;
+ };
+
+ mdio0_phy13: mdio_phy1@1d {
+ reg = <0x1d>;
+ };
+
+ mdio0_phy14: mdio_phy2@1e {
+ reg = <0x1e>;
+ };
+
+ mdio0_phy15: mdio_phy3@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+ };
+};
--
2.25.1
Define PHY nodes on the board.
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls2080a-rdb.dts | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index 44894356059c..1c8c99a74071 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -23,3 +23,71 @@ chosen {
stdout-path = "serial1:115200n8";
};
};
+
+&dpmac5 {
+ phy-handle = <&mdio2_phy1>;
+ phy-connection-type = "10gbase-r";
+};
+
+&dpmac6 {
+ phy-handle = <&mdio2_phy2>;
+ phy-connection-type = "10gbase-r";
+};
+
+&dpmac7 {
+ phy-handle = <&mdio2_phy3>;
+ phy-connection-type = "10gbase-r";
+};
+
+&dpmac8 {
+ phy-handle = <&mdio2_phy4>;
+ phy-connection-type = "10gbase-r";
+};
+
+&emdio1 {
+ status = "disabled";
+
+ /* CS4340 PHYs */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x10>;
+ };
+
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x11>;
+ };
+
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x12>;
+ };
+
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x13>;
+ };
+};
+
+&emdio2 {
+ /* AQR405 PHYs */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 1 0x4>; /* Level high type */
+ reg = <0x0>;
+ };
+
+ mdio2_phy2: emdio2_phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>; /* Level high type */
+ reg = <0x1>;
+ };
+
+ mdio2_phy3: emdio2_phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 4 0x4>; /* Level high type */
+ reg = <0x2>;
+ };
+
+ mdio2_phy4: emdio2_phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 5 0x4>; /* Level high type */
+ reg = <0x3>;
+ };
+};
--
2.25.1
From: Priyanka Jain <[email protected]>
This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional
perspective both are same. Hence,ls2088a SoC dtsi files are included
from ls2081ARDB dts
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Signed-off-by: Tao Yang <[email protected]>
Signed-off-by: Yogesh Gaur <[email protected]>
Signed-off-by: Abhimanyu Saini <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/fsl-ls2081a-rdb.dts | 131 ++++++++++++++++++
2 files changed, 132 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6d8f0a532587..1b5cb71a6828 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
new file mode 100644
index 000000000000..908b9aff0489
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for NXP LS2081A RDB Board.
+ *
+ * Copyright 2017 NXP
+ *
+ * Priyanka Jain <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2088a.dtsi"
+
+/ {
+ model = "NXP Layerscape 2081A RDB Board";
+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
+
+&dspi {
+ status = "okay";
+
+ n25q512a: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <3000000>;
+ reg = <0>;
+ };
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&ifc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547: mux@75 {
+ compatible = "nxp,pca9547";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x01>;
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <500>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ adt7481@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ s25fs512s0: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+
+ s25fs512s1: flash@1 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
2.25.1
On Thu, Mar 17, 2022 at 02:01:04PM -0500, Li Yang wrote:
> Add mmio mdio mux nodes from the on-board FPGA.
>
> Signed-off-by: Li Yang <[email protected]>
> ---
> .../boot/dts/freescale/fsl-ls2080a-qds.dts | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> index f6c3ee78ace0..c3caca1c0ab6 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
> @@ -23,3 +23,72 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
> };
> +
> +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
> +&dpmac9 {
> + phy-handle = <&mdio0_phy12>;
> + phy-connection-type = "sgmii";
> +};
> +
> +&dpmac10 {
> + phy-handle = <&mdio0_phy13>;
> + phy-connection-type = "sgmii";
> +};
> +
> +&dpmac11 {
> + phy-handle = <&mdio0_phy14>;
> + phy-connection-type = "sgmii";
> +};
> +
> +&dpmac12 {
> + phy-handle = <&mdio0_phy15>;
> + phy-connection-type = "sgmii";
> +};
> +
> +&ifc {
> + boardctrl: board-control@3,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
> + reg = <3 0 0x300>;
> + ranges = <0 3 0 0x300>;
> +
> + mdio_mux_emi1 {
> + compatible = "mdio-mux-mmioreg", "mdio-mux";
> + mdio-parent-bus = <&emdio1>;
> + reg = <0x54 1>; /* BRDCFG4 */
Please ensure the patch doesn't introduce additional DTC warnings. I
think 'reg' should present only in nodes with a matching unit-address.
Shawn
> + mux-mask = <0xe0>; /* EMI1_MDIO */
> +
> + #address-cells=<1>;
> + #size-cells = <0>;
> +
> + /* Child MDIO buses, one for each riser card:
> + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
> + * VSC8234 PHYs on the riser cards.
> + */
> +
> + mdio_mux3: mdio@60 {
> + reg = <0x60>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mdio0_phy12: mdio_phy0@1c {
> + reg = <0x1c>;
> + };
> +
> + mdio0_phy13: mdio_phy1@1d {
> + reg = <0x1d>;
> + };
> +
> + mdio0_phy14: mdio_phy2@1e {
> + reg = <0x1e>;
> + };
> +
> + mdio0_phy15: mdio_phy3@1f {
> + reg = <0x1f>;
> + };
> + };
> + };
> + };
> +};
> +
> --
> 2.25.1
>
On Thu, Mar 17, 2022 at 02:01:07PM -0500, Li Yang wrote:
> From: Priyanka Jain <[email protected]>
>
> This patch add support for NXP LS2081ARDB board which has
> LS2081A SoC.
>
> LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional
... SoC. So, ...?
> perspective both are same. Hence,ls2088a SoC dtsi files are included
Hence, ls2088a ...
> from ls2081ARDB dts
LS2081ARDB dts.
I won't review the patch content until the commit log looks good.
Shawn
>
> Signed-off-by: Priyanka Jain <[email protected]>
> Signed-off-by: Santan Kumar <[email protected]>
> Signed-off-by: Tao Yang <[email protected]>
> Signed-off-by: Yogesh Gaur <[email protected]>
> Signed-off-by: Abhimanyu Saini <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 131 ++++++++++++++++++
> 2 files changed, 132 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 6d8f0a532587..1b5cb71a6828 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> new file mode 100644
> index 000000000000..908b9aff0489
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for NXP LS2081A RDB Board.
> + *
> + * Copyright 2017 NXP
> + *
> + * Priyanka Jain <[email protected]>
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-ls2088a.dtsi"
> +
> +/ {
> + model = "NXP Layerscape 2081A RDB Board";
> + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
> +
> + aliases {
> + serial0 = &serial0;
> + serial1 = &serial1;
> + };
> +
> + chosen {
> + stdout-path = "serial1:115200n8";
> + };
> +};
> +
> +&dspi {
> + status = "okay";
> +
> + n25q512a: flash@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <3000000>;
> + reg = <0>;
> + };
> +};
> +
> +&esdhc {
> + status = "okay";
> +};
> +
> +&ifc {
> + status = "disabled";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + pca9547: mux@75 {
> + compatible = "nxp,pca9547";
> + reg = <0x75>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x01>;
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + };
> + };
> +
> + i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x02>;
> +
> + ina220@40 {
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <500>;
> + };
> + };
> +
> + i2c@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x3>;
> +
> + adt7481@4c {
> + compatible = "adi,adt7461";
> + reg = <0x4c>;
> + };
> + };
> + };
> +};
> +
> +&qspi {
> + status = "okay";
> +
> + s25fs512s0: flash@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <4>;
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + };
> +
> + s25fs512s1: flash@1 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <4>;
> + spi-max-frequency = <20000000>;
> + reg = <1>;
> + };
> +};
> +
> +&sata0 {
> + status = "okay";
> +};
> +
> +&sata1 {
> + status = "okay";
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> --
> 2.25.1
>
On Thu, Mar 17, 2022 at 02:01:06PM -0500, Li Yang wrote:
> Define PHY nodes on the board.
>
> Signed-off-by: Li Yang <[email protected]>
> ---
> .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> index 44894356059c..1c8c99a74071 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
> @@ -23,3 +23,71 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
> };
> +
> +&dpmac5 {
> + phy-handle = <&mdio2_phy1>;
> + phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac6 {
> + phy-handle = <&mdio2_phy2>;
> + phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac7 {
> + phy-handle = <&mdio2_phy3>;
> + phy-connection-type = "10gbase-r";
> +};
> +
> +&dpmac8 {
> + phy-handle = <&mdio2_phy4>;
> + phy-connection-type = "10gbase-r";
> +};
> +
> +&emdio1 {
> + status = "disabled";
> +
> + /* CS4340 PHYs */
> + mdio1_phy1: emdio1_phy@1 {
We prefer hyphen rather than underscore in node name.
Shawn
> + reg = <0x10>;
> + };
> +
> + mdio1_phy2: emdio1_phy@2 {
> + reg = <0x11>;
> + };
> +
> + mdio1_phy3: emdio1_phy@3 {
> + reg = <0x12>;
> + };
> +
> + mdio1_phy4: emdio1_phy@4 {
> + reg = <0x13>;
> + };
> +};
> +
> +&emdio2 {
> + /* AQR405 PHYs */
> + mdio2_phy1: emdio2_phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + interrupts = <0 1 0x4>; /* Level high type */
> + reg = <0x0>;
> + };
> +
> + mdio2_phy2: emdio2_phy@2 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + interrupts = <0 2 0x4>; /* Level high type */
> + reg = <0x1>;
> + };
> +
> + mdio2_phy3: emdio2_phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + interrupts = <0 4 0x4>; /* Level high type */
> + reg = <0x2>;
> + };
> +
> + mdio2_phy4: emdio2_phy@4 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + interrupts = <0 5 0x4>; /* Level high type */
> + reg = <0x3>;
> + };
> +};
> --
> 2.25.1
>