Add description to support Axis, ARTPEC-8 SoC.
ARTPEC-8 is the SoC platform of Axis Communications
and PCIe phy is designed based on SAMSUNG PHY.
Signed-off-by: Wangseok Lee <[email protected]>
---
.../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
new file mode 100644
index 0000000..f5f4166
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Jesper Nilsson <[email protected]>
+
+properties:
+ compatible:
+ const: axis,artpec8-pcie-phy
+
+ reg:
+ items:
+ - description: PHY registers.
+ - description: PHY coding sublayer registers.
+
+ reg-names:
+ items:
+ - const: phy
+ - const: pcs
+
+ clocks:
+ items:
+ - description: PCIe PHY reference clock
+
+ clock-names:
+ items:
+ - const: ref_clk
+
+required:
+ - compatible
+ - "#phy-cells"
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,fsys-sysreg
+ - num-lanes
+
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ artec8 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie_phy: pcie-phy@16c80000 {
+ compatible = "samsung,artpec8-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x16c80000 0x0 0x2000>,
+ <0x0 0x16c90000 0x0 0x1000>;
+ reg-names = "phy", "pcs";
+ clocks = <&clock_cmu_fsys 53>;
+ clock-names = "ref_clk";
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ num-lanes = <2>;
+ };
+ };
+...
--
2.9.5
On Mon, 28 Mar 2022 17:43:19 +0900, 이왕석 wrote:
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe phy is designed based on SAMSUNG PHY.
>
> Signed-off-by: Wangseok Lee <[email protected]>
> ---
> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.example.dt.yaml:0:0: /example-0/artec8/pcie-phy@16c80000: failed to match any schema with compatible: ['samsung,artpec8-pcie-phy']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1610068
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 28/03/2022 10:43, 이왕석 wrote:
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe phy is designed based on SAMSUNG PHY.
>
> Signed-off-by: Wangseok Lee <[email protected]>
> ---
> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> new file mode 100644
> index 0000000..f5f4166
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings
s/Device Tree Bindings//
> +
> +maintainers:
> + - Jesper Nilsson <[email protected]>
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie-phy
> +
> + reg:
> + items:
> + - description: PHY registers.
> + - description: PHY coding sublayer registers.
> +
> + reg-names:
> + items:
> + - const: phy
> + - const: pcs
> +
> + clocks:
> + items:
> + - description: PCIe PHY reference clock
> +
> + clock-names:
> + items:
> + - const: ref_clk
> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - samsung,fsys-sysreg
It seems you copied some things from some other bindings, so please
clean it up to really fit your device.
Best regards,
Krzysztof
> --------- Original Message ---------
> Sender : Rob Herring <[email protected]>
> Date : 2022-03-28 21:51 (GMT+9)
> Title : Re: [PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
>
> On Mon, 28 Mar 2022 17:43:19 +0900, �댁���� wrote:
>> Add description to support Axis, ARTPEC-8 SoC.
>> ARTPEC-8 is the SoC platform of Axis Communications
>> and PCIe phy is designed based on SAMSUNG PHY.
>>
>> Signed-off-by: Wangseok Lee <[email protected]>
>> ---
>> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++
>> 1 file changed, 67 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.example.dt.yaml:0:0: /example-0/artec8/pcie-phy@16c80000: failed to match any schema with compatible: ['samsung,artpec8-pcie-phy']
>
> doc reference errors (make refcheckdocs):
>
> See https://protect2.fireeye.com/v1/url?k=0fdd5edc-6f3fc381-0fdcd593-000babd9f1ba-cd731013fdd72389&q=1&e=df20f229-606a-4e6a-bcb2-2cbdc399248e&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F1610068
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Hello Rob Herring
Thanks for your review.
I wrote the wrong "compatible" value.
so i will modify this part and summit it again.
also i checked the result by performing
"make dt_binding_check DT_SCHEMA_FILES=
Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml".
Thanks.