From: Frank Wunderlich <[email protected]>
This series adds Rockchip PCIe V3 support found on rk3568 SOC.
It is based on "Enable rk356x PCIe controller" series of Peter Geis
v7: https://patchwork.kernel.org/project/linux-rockchip/cover/[email protected]/
Compared to PCIeV2 which uses the Naneng combphy, pciev3
uses a dedicated pci-phy.
Frank Wunderlich (6):
dt-bindings: phy: rockchip: add pcie3 phy
dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
phy: rockchip: Support pcie v3
PCI: rockchip-dwc: add pcie bifurcation
arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
.../bindings/phy/rockchip-pcie3-phy.yaml | 77 +++++
.../devicetree/bindings/soc/rockchip/grf.yaml | 2 +
.../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 79 +++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 ++++++++
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 11 +
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile | 1 +
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 278 ++++++++++++++++++
include/dt-bindings/phy/phy-snps-pcie3.h | 21 ++
include/linux/phy/pcie.h | 12 +
10 files changed, 612 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
create mode 100644 include/dt-bindings/phy/phy-snps-pcie3.h
create mode 100644 include/linux/phy/pcie.h
--
2.25.1
From: Frank Wunderlich <[email protected]>
Add compatibles for PCIe v3 General Register Files.
Signed-off-by: Frank Wunderlich <[email protected]>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 3be3cfd52f7b..ae48b58bd062 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -14,6 +14,8 @@ properties:
oneOf:
- items:
- enum:
+ - rockchip,pcie30-phy-grf
+ - rockchip,pcie30-pipe-grf
- rockchip,rk3288-sgrf
- rockchip,rk3566-pipe-grf
- rockchip,rk3568-usb2phy-grf
--
2.25.1
From: Frank Wunderlich <[email protected]>
PCIe Lanes can be split to 2 slots with bifurcation.
Add support for this in existing pcie driver.
Co-developed-by: Peter Geis <[email protected]>
Signed-off-by: Frank Wunderlich <[email protected]>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 863374604fb1..1b0c2115b32e 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <linux/phy/pcie.h>
#include "pcie-designware.h"
@@ -59,6 +60,7 @@ struct rockchip_pcie {
struct regulator *vpcie3v3;
struct irq_domain *irq_domain;
raw_spinlock_t irq_lock;
+ bool bifurcation;
};
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
@@ -273,6 +275,12 @@ static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
return dev_err_probe(dev, PTR_ERR(rockchip->phy),
"missing PHY\n");
+ if (rockchip->bifurcation) {
+ ret = phy_set_mode_ext(rockchip->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_BIFURCATION);
+ if (ret)
+ return ret;
+ }
+
ret = phy_init(rockchip->phy);
if (ret < 0)
return ret;
@@ -345,6 +353,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
}
}
+ if (device_property_read_bool(dev, "rockchip,bifurcation"))
+ rockchip->bifurcation = true;
+
ret = rockchip_pcie_phy_init(rockchip);
if (ret)
goto disable_regulator;
--
2.25.1
On 16/04/2022 15:54, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Add compatibles for PCIe v3 General Register Files.
>
> Signed-off-by: Frank Wunderlich <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> index 3be3cfd52f7b..ae48b58bd062 100644
> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> @@ -14,6 +14,8 @@ properties:
> oneOf:
> - items:
> - enum:
> + - rockchip,pcie30-phy-grf
> + - rockchip,pcie30-pipe-grf
These are without SoC parts. Are these PCIe v3 General Register Files
part of some PCIe spec?
> - rockchip,rk3288-sgrf
> - rockchip,rk3566-pipe-grf
> - rockchip,rk3568-usb2phy-grf
Best regards,
Krzysztof
On Sat, Apr 16, 2022 at 03:54:56PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> PCIe Lanes can be split to 2 slots with bifurcation.
> Add support for this in existing pcie driver.
Please s/pcie/PCIe/ in subject and above to be consistent. You also
have kind of a random usage in other patches.
Mention the DT property used for this in the commit log.
Is the "rockchip,bifurcation" DT property something that should be
generalized so it's not rockchip-specific? Other controllers are
likely to support similar functionality.
> Co-developed-by: Peter Geis <[email protected]>
> Signed-off-by: Frank Wunderlich <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 863374604fb1..1b0c2115b32e 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -20,6 +20,7 @@
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> +#include <linux/phy/pcie.h>
>
> #include "pcie-designware.h"
>
> @@ -59,6 +60,7 @@ struct rockchip_pcie {
> struct regulator *vpcie3v3;
> struct irq_domain *irq_domain;
> raw_spinlock_t irq_lock;
> + bool bifurcation;
> };
>
> static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
> @@ -273,6 +275,12 @@ static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
> return dev_err_probe(dev, PTR_ERR(rockchip->phy),
> "missing PHY\n");
>
> + if (rockchip->bifurcation) {
> + ret = phy_set_mode_ext(rockchip->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_BIFURCATION);
> + if (ret)
> + return ret;
> + }
> +
> ret = phy_init(rockchip->phy);
> if (ret < 0)
> return ret;
> @@ -345,6 +353,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> }
> }
>
> + if (device_property_read_bool(dev, "rockchip,bifurcation"))
> + rockchip->bifurcation = true;
> +
> ret = rockchip_pcie_phy_init(rockchip);
> if (ret)
> goto disable_regulator;
> --
> 2.25.1
>
>
> --
> linux-phy mailing list
> [email protected]
> https://lists.infradead.org/mailman/listinfo/linux-phy
> Gesendet: Montag, 18. April 2022 um 17:54 Uhr
> Von: "Krzysztof Kozlowski" <[email protected]>
> > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > @@ -14,6 +14,8 @@ properties:
> > oneOf:
> > - items:
> > - enum:
> > + - rockchip,pcie30-phy-grf
> > + - rockchip,pcie30-pipe-grf
>
> These are without SoC parts. Are these PCIe v3 General Register Files
> part of some PCIe spec?
imho they are shared across SoCs rk3568 and rk3588, but have only seen rk3568 implementation yet.
PCIe driver currently supports these 2 Soc (different offsets in the Phy-GRF), but can only test rk3568.
pipe-grf seems only be used for rk35688 (offset used in probe is defined for this SoC), which i cannot test.
so i have left them SoC independed.
> > - rockchip,rk3288-sgrf
> > - rockchip,rk3566-pipe-grf
> > - rockchip,rk3568-usb2phy-grf
regards Frank
Am 11. Mai 2022 21:26:09 MESZ schrieb Piotr Oniszczuk <[email protected]>:
>Frank, Peter
>
>FYI:
>This series gives me nicely working PCI-e WiFi M2 iwl7265 module on
>rock3-a.
>Great work!
Hi,
Peter recently made some fixes and improvements. I plan to send new version soon.
You're welcome to test it on your board and give a Tested-by tag
regards Frank
> Wiadomość napisana przez Frank Wunderlich <[email protected]> w dniu 16.04.2022, o godz. 15:54:
>
> From: Frank Wunderlich <[email protected]>
>
> This series adds Rockchip PCIe V3 support found on rk3568 SOC.
>
> It is based on "Enable rk356x PCIe controller" series of Peter Geis
> v7: https://patchwork.kernel.org/project/linux-rockchip/cover/[email protected]/
>
> Compared to PCIeV2 which uses the Naneng combphy, pciev3
> uses a dedicated pci-phy.
>
> Frank Wunderlich (6):
> dt-bindings: phy: rockchip: add pcie3 phy
> dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
> phy: rockchip: Support pcie v3
> PCI: rockchip-dwc: add pcie bifurcation
> arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
> arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
Frank, Peter
FYI:
This series gives me nicely working PCI-e WiFi M2 iwl7265 module on rock3-a.
Great work!