Hi All,
The RZ/G2L Interrupt Controller is a front-end for the GIC found on
Renesas RZ/G2L SoC's with below pins:
- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
- GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
maximum of only 32 can be mapped to 32 GIC SPI interrupts,
- NMI edge select.
_____________
| GIC |
| ________ |
____________ | | | |
NMI ------------------------------------>| | SPI0-479 | | GIC-600| |
_______ | |------------>| | |
| | | | PPI16-31 | | | |
| | IRQ0-IRQ7 | IRQC |------------>| | |
P0_P48_4 ------>| GPIO |---------------->| | | |________| |
| |GPIOINT0-122 | | | |
| |---------------->| TINT0-31 | | |
|______| |__________| |____________|
The proposed patches add hierarchical IRQ domain, one in IRQC driver and another in
pinctrl driver. Upon interrupt requests map the interrupt to GIC. Out of GPIOINT0-122
only 32 can be mapped to GIC SPI, this mapping is handled by the pinctrl and IRQC driver.
Cheers,
Prabhakar
Changes for RFCV4 -> V1:
* Used unevaluatedProperties.
* Altered the sequence of reg property
* Set the parent type
* Used raw_spin_lock() instead of raw_spin_lock_irqsave()
* Simplified parsing IRQ map.
* Will send the GPIO and pinctrl changes as part of separate series
Changes for v4:
* Used locking while RMW
* Now using interrupts property instead of interrupt-map
* Patch series depends on [0]
* Updated binding doc
* Fixed comments pointed by Andy
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
[email protected]/
Changes for v3:
-> Re-structured the driver as a hierarchical irq domain instead of chained
-> made use of IRQCHIP_* macros
-> dropped locking
-> Added support for IRQ0-7 interrupts
-> Introduced 2 new patches for GPIOLIB
-> Switched to using GPIOLIB for irqdomains in pinctrl
RFC v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
[email protected]/
RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/
[email protected]/
Lad Prabhakar (2):
dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt
Controller
irqchip: Add RZ/G2L IA55 Interrupt Controller driver
.../renesas,rzg2l-irqc.yaml | 131 +++++
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-rzg2l.c | 447 ++++++++++++++++++
4 files changed, 587 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c
--
2.17.1
Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
Signed-off-by: Lad Prabhakar <[email protected]>
---
.../renesas,rzg2l-irqc.yaml | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
new file mode 100644
index 000000000000..5f2e1dd1d42a
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
+
+maintainers:
+ - Lad Prabhakar <[email protected]>
+ - Geert Uytterhoeven <[email protected]>
+
+description: |
+ IA55 performs various interrupt controls including synchronization for the external
+ interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
+ interrupts output by each IP. And it notifies the interrupt to the GIC
+ - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
+ - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
+ - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
+ stand-up edge detection interrupts)
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-irqc # RZ/G2L
+ - const: renesas,rzg2l-irqc
+
+ '#interrupt-cells':
+ const: 2
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 41
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: clk
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
+ reg = <0x110a0000 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
+ };
--
2.17.1
Hi Prabhakar,
On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
<[email protected]> wrote:
> Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -0,0 +1,131 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
> +
> +maintainers:
> + - Lad Prabhakar <[email protected]>
> + - Geert Uytterhoeven <[email protected]>
> +
> +description: |
> + IA55 performs various interrupt controls including synchronization for the external
> + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
> + interrupts output by each IP. And it notifies the interrupt to the GIC
> + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
> + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> + stand-up edge detection interrupts)
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-irqc # RZ/G2L
> + - const: renesas,rzg2l-irqc
> +
> + '#interrupt-cells':
> + const: 2
What is the meaning of the cells? IRQ number + flags, I assume?
How are the numbers mapped, do you need a DT bindings header?
Perhaps it would make sense to increase to 3 cells, so you can use
one cell for the type (cfr. e.g. GIC_SPI), and the second for the
plain index within the type?
The rest LGTM, but I'm not an interrupt expert, so I'm curious in
hearing Marc's opinion.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Fri, Apr 29, 2022 at 10:38 AM Lad, Prabhakar
<[email protected]> wrote:
> On Thu, Apr 28, 2022 at 10:32 AM Geert Uytterhoeven
> > On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
> > <[email protected]> wrote:
> > > Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > @@ -0,0 +1,131 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
> > > +
> > > +maintainers:
> > > + - Lad Prabhakar <[email protected]>
> > > + - Geert Uytterhoeven <[email protected]>
> > > +
> > > +description: |
> > > + IA55 performs various interrupt controls including synchronization for the external
> > > + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
> > > + interrupts output by each IP. And it notifies the interrupt to the GIC
> > > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
> > > + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > > + stand-up edge detection interrupts)
> > > +
> > > +allOf:
> > > + - $ref: /schemas/interrupt-controller.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-irqc # RZ/G2L
> > > + - const: renesas,rzg2l-irqc
> > > +
> > > + '#interrupt-cells':
> > > + const: 2
> >
> > What is the meaning of the cells? IRQ number + flags, I assume?
> IRQ number and the type.
>
> > How are the numbers mapped, do you need a DT bindings header?
> No, just plain numbers are used (driver handles the validation of the
> interrupt numbering), for example like below,
>
> ð0 {
> ...
> status = "okay";
>
> phy0: ethernet-phy@7 {
> compatible = "ethernet-phy-id0022.1640",
> "ethernet-phy-ieee802.3-c22";
> reg = <7>;
> interrupt-parent = <&irqc>;
> interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
OK, so the number must be an external interrupt number (0..7).
> ...
> };
> };
>
> And for the GPIO:
>
> key-1 {
> gpios = <&pinctrl RZG2L_GPIO(43, 0) GPIO_ACTIVE_HIGH>;
> linux,code = <KEY_1>;
> linux,input-type = <EV_KEY>;
> wakeup-source;
> label = "SW1";
> };
OK, so in this case the interrupt number is obtained implicitly, and
no interrupts property is used.
> > Perhaps it would make sense to increase to 3 cells, so you can use
> > one cell for the type (cfr. e.g. GIC_SPI), and the second for the
> > plain index within the type?
> >
> Could you please elaborate on this. Are you referring to the type here
> as the type to be set up in the GIC?
Please ignore, you don't need the type, as it's always an external
interrupt number, right?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Thu, Apr 28, 2022 at 10:32 AM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
> <[email protected]> wrote:
> > Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -0,0 +1,131 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
> > +
> > +maintainers:
> > + - Lad Prabhakar <[email protected]>
> > + - Geert Uytterhoeven <[email protected]>
> > +
> > +description: |
> > + IA55 performs various interrupt controls including synchronization for the external
> > + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
> > + interrupts output by each IP. And it notifies the interrupt to the GIC
> > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
> > + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > + stand-up edge detection interrupts)
> > +
> > +allOf:
> > + - $ref: /schemas/interrupt-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-irqc # RZ/G2L
> > + - const: renesas,rzg2l-irqc
> > +
> > + '#interrupt-cells':
> > + const: 2
>
> What is the meaning of the cells? IRQ number + flags, I assume?
IRQ number and the type.
> How are the numbers mapped, do you need a DT bindings header?
No, just plain numbers are used (driver handles the validation of the
interrupt numbering), for example like below,
ð0 {
...
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
...
};
};
And for the GPIO:
key-1 {
gpios = <&pinctrl RZG2L_GPIO(43, 0) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_1>;
linux,input-type = <EV_KEY>;
wakeup-source;
label = "SW1";
};
> Perhaps it would make sense to increase to 3 cells, so you can use
> one cell for the type (cfr. e.g. GIC_SPI), and the second for the
> plain index within the type?
>
Could you please elaborate on this. Are you referring to the type here
as the type to be set up in the GIC?
Cheers,
Prabhakar
> The rest LGTM, but I'm not an interrupt expert, so I'm curious in
> hearing Marc's opinion.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
On Thu, 21 Apr 2022 23:11:58 +0100, Lad Prabhakar wrote:
> Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> .../renesas,rzg2l-irqc.yaml | 131 ++++++++++++++++++
> 1 file changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
>
Reviewed-by: Rob Herring <[email protected]>
Hi Geert,
On Fri, Apr 29, 2022 at 9:44 AM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Fri, Apr 29, 2022 at 10:38 AM Lad, Prabhakar
> <[email protected]> wrote:
> > On Thu, Apr 28, 2022 at 10:32 AM Geert Uytterhoeven
> > > On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
> > > <[email protected]> wrote:
> > > > Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
> > > >
> > > > Signed-off-by: Lad Prabhakar <[email protected]>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > > @@ -0,0 +1,131 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
> > > > +
> > > > +maintainers:
> > > > + - Lad Prabhakar <[email protected]>
> > > > + - Geert Uytterhoeven <[email protected]>
> > > > +
> > > > +description: |
> > > > + IA55 performs various interrupt controls including synchronization for the external
> > > > + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
> > > > + interrupts output by each IP. And it notifies the interrupt to the GIC
> > > > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > > > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
> > > > + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > > > + stand-up edge detection interrupts)
> > > > +
> > > > +allOf:
> > > > + - $ref: /schemas/interrupt-controller.yaml#
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-irqc # RZ/G2L
> > > > + - const: renesas,rzg2l-irqc
> > > > +
> > > > + '#interrupt-cells':
> > > > + const: 2
> > >
> > > What is the meaning of the cells? IRQ number + flags, I assume?
> > IRQ number and the type.
> >
> > > How are the numbers mapped, do you need a DT bindings header?
> > No, just plain numbers are used (driver handles the validation of the
> > interrupt numbering), for example like below,
> >
> > ð0 {
> > ...
> > status = "okay";
> >
> > phy0: ethernet-phy@7 {
> > compatible = "ethernet-phy-id0022.1640",
> > "ethernet-phy-ieee802.3-c22";
> > reg = <7>;
> > interrupt-parent = <&irqc>;
> > interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>
> OK, so the number must be an external interrupt number (0..7).
>
Yep that's right.
> > ...
> > };
> > };
> >
> > And for the GPIO:
> >
> > key-1 {
> > gpios = <&pinctrl RZG2L_GPIO(43, 0) GPIO_ACTIVE_HIGH>;
> > linux,code = <KEY_1>;
> > linux,input-type = <EV_KEY>;
> > wakeup-source;
> > label = "SW1";
> > };
>
> OK, so in this case the interrupt number is obtained implicitly, and
> no interrupts property is used.
>
Indeed.
> > > Perhaps it would make sense to increase to 3 cells, so you can use
> > > one cell for the type (cfr. e.g. GIC_SPI), and the second for the
> > > plain index within the type?
> > >
> > Could you please elaborate on this. Are you referring to the type here
> > as the type to be set up in the GIC?
>
> Please ignore, you don't need the type, as it's always an external
> interrupt number, right?
>
Yep that's right.
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds