This patch queue addresses the power sequence of the display controller
of the imx8mm SoC. The sequence mentioned in example code 5 in section
5.2.9.5 of reference manual imx-8MMini-yhsc.pdf was not being performed.
This meant that the display controller was not coming up.
Viraj Shah (4):
soc: imx: gpcv2: Power sequence for DISP
soc: imx: imx8m-blk-ctrl: Display Power ON sequence
soc: imx: imx8m-blk-ctrl: Add reset bits for mipi dsi phy
arm64: dts: imx8mm.dtsi: Add resets for dispmix power domain.
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
drivers/soc/imx/gpcv2.c | 36 +++++++++++++++++++----
drivers/soc/imx/imx8m-blk-ctrl.c | 9 ++++--
3 files changed, 38 insertions(+), 8 deletions(-)
--
2.20.1
The resets are controlled from src. From reference manual page
959, display controller needs DISP_RESET bit to be set to reset
dispmix.
Signed-off-by: Viraj Shah <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1ee05677c2dd..11a6cae5bb99 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -734,6 +734,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <200000000>;
+ resets = <&src IMX8MQ_RESET_DISP_RESET>;
};
pgc_mipi: power-domain@11 {
--
2.20.1