2022-06-16 02:08:07

by Stephen Boyd

[permalink] [raw]
Subject: Re: [RESEND v8 02/19] clk: mediatek: reset: Fix written reset bit offset

Quoting Rex-BC Chen (2022-05-23 02:33:29)
> Original assert/deassert bit is BIT(0), but it's more resonable to modify
> them to BIT(id % 32) which is based on id.
>
> This patch will not influence any previous driver because the reset is
> only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.
>
> Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
> Signed-off-by: Rex-BC Chen <[email protected]>
> Reviewed-by: Chen-Yu Tsai <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> Reviewed-by: NĂ­colas F. R. A. Prado <[email protected]>
> Tested-by: NĂ­colas F. R. A. Prado <[email protected]>
> ---

Applied to clk-next