2022-06-24 14:47:56

by Clément Léger

Subject: [PATCH net-next v9 15/16] ARM: dts: r9a06g032-rzn1d400-db: add switch description

Add description for the switch, GMAC2 and MII converter. With these
definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
RZ/N1D-DB board.

Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
---
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 117 ++++++++++++++++++++
1 file changed, 117 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 3f8f3ce87e12..4227aba70c30 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -8,6 +8,8 @@

/dts-v1/;

+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+#include <dt-bindings/net/pcs-rzn1-miic.h>
#include "r9a06g032.dtsi"

/ {
@@ -31,3 +33,118 @@ &wdt0 {
timeout-sec = <60>;
status = "okay";
};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "gmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&switch {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>;
+
+ dsa,member = <0 0>;
+
+ mdio {
+ clock-frequency = <2500000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy4: ethernet-phy@4 {
+ reg = <4>;
+ micrel,led-mode = <1>;
+ };
+
+ switch0phy5: ethernet-phy@5 {
+ reg = <5>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&switch_port0 {
+ label = "lan0";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy5>;
+ status = "okay";
+};
+
+&switch_port1 {
+ label = "lan1";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy4>;
+ status = "okay";
+};
+
+&switch_port4 {
+ status = "okay";
+};
+
+&eth_miic {
+ status = "okay";
+ renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
+};
+
+&mii_conv4 {
+ renesas,miic-input = <MIIC_SWITCH_PORTB>;
+ status = "okay";
+};
+
+&mii_conv5 {
+ renesas,miic-input = <MIIC_SWITCH_PORTA>;
+ status = "okay";
+};
+
+&pinctrl{
+ pins_mdio1: pins_mdio1 {
+ pinmux = <
+ RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)
+ RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)
+ >;
+ };
+ pins_eth3: pins_eth3 {
+ pinmux = <
+ RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ >;
+ drive-strength = <6>;
+ bias-disable;
+ };
+ pins_eth4: pins_eth4 {
+ pinmux = <
+ RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)
+ >;
+ drive-strength = <6>;
+ bias-disable;
+ };
+};
--
2.36.1

2022-06-25 02:42:01

by Florian Fainelli

Subject: Re: [PATCH net-next v9 15/16] ARM: dts: r9a06g032-rzn1d400-db: add switch description

On 6/24/2022 7:40 AM, Clément Léger wrote:
> Add description for the switch, GMAC2 and MII converter. With these
> definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
> RZ/N1D-DB board.
>
> Signed-off-by: Clément Léger <[email protected]>
> Reviewed-by: Vladimir Oltean <[email protected]>
> ---

[snip]

> + pinctrl-names = "default";
> + pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>;
> +
> + dsa,member = <0 0>;

Does not hurt to have it, but not required at this point. Not a reson to
spin a v10 though:

Reviewed-by: Florian Fainelli <[email protected]>
--
Florian

2022-06-28 15:46:42

by Geert Uytterhoeven

Subject: Re: [PATCH net-next v9 15/16] ARM: dts: r9a06g032-rzn1d400-db: add switch description

Hi Clément,

On Fri, Jun 24, 2022 at 4:42 PM Clément Léger <[email protected]> wrote:
> Add description for the switch, GMAC2 and MII converter. With these
> definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
> RZ/N1D-DB board.
>
> Signed-off-by: Clément Léger <[email protected]>
> Reviewed-by: Vladimir Oltean <[email protected]>

Thanks for your patch!

> --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> @@ -31,3 +33,118 @@ &wdt0 {
> timeout-sec = <60>;
> status = "okay";
> };
> +
> +&gmac2 {

Please keep the nodes sorted (everywhere).

> +&pinctrl{
> + pins_mdio1: pins_mdio1 {
> + pinmux = <
> + RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)
> + RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)
> + >;

This is not a single value, but an array of 2 values. Hence they
should be grouped using angular brackets, to enable automatic
validation.

I will fix the above while applying, so no need to resend.

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.20.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-06-28 16:32:48

by Clément Léger

Subject: Re: [PATCH net-next v9 15/16] ARM: dts: r9a06g032-rzn1d400-db: add switch description

Le Tue, 28 Jun 2022 17:34:31 +0200,
Geert Uytterhoeven <[email protected]> a écrit :

> > +&gmac2 {
>
> Please keep the nodes sorted (everywhere).

Arg sorry, again, the previous nodes seems not to be ordered.
I'll be more careful next time.

>
> > +&pinctrl{
> > + pins_mdio1: pins_mdio1 {
> > + pinmux = <
> > + RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)
> > + RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)
> > + >;
>
> This is not a single value, but an array of 2 values. Hence they
> should be grouped using angular brackets, to enable automatic
> validation.

Good to know, noted for next time.

>
> I will fix the above while applying, so no need to resend.

Thanks Geert,

Clément

>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> i.e. will queue in renesas-devel for v5.20.
>
> Gr{oetje,eeting}s,
>
> Geert


--
Clément Léger,
Embedded Linux and Kernel engineer at Bootlin
https://bootlin.com