Subject: [PATCH 07/11] arm64: dts: mediatek: cherry: Enable I2C and SPI controllers

This platform uses eight I2C controllers and one SPI controller:
in preparation for enabling devices attached to these controllers,
add basic configuration to enable the busses.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 150 ++++++++++++++++++
1 file changed, 150 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 2f70341bba91..23a86d07274c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -9,6 +9,13 @@

/ {
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c7 = &i2c7;
mmc0 = &mmc0;
serial0 = &uart0;
};
@@ -88,6 +95,65 @@ ppvar_sys: regulator-ppvar-sys {
};
};

+&i2c0 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pin>;
+};
+
+&i2c1 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ i2c-scl-internal-delay-ns = <12500>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pin>;
+};
+
+&i2c2 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pin>;
+};
+
+&i2c3 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pin>;
+};
+
+&i2c4 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pin>;
+};
+
+&i2c5 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pin>;
+};
+
+&i2c7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pin>;
+};
+
&mmc0 {
status = "okay";

@@ -300,6 +366,68 @@ &pio {
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_MISO";

+ i2c0_pin: i2c0-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-disable;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c1_pin: i2c1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <1000>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c2_pin: i2c2-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
+ <PINMUX_GPIO13__FUNC_SCL2>;
+ bias-disable;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c3_pin: i2c3-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
+ <PINMUX_GPIO15__FUNC_SCL3>;
+ bias-pull-up = <1000>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c4_pin: i2c4-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <1000>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ i2c5_pin: i2c5-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
+ <PINMUX_GPIO30__FUNC_SDA5>;
+ bias-disable;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c7_pin: i2c7-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
+ <PINMUX_GPIO28__FUNC_SDA7>;
+ bias-disable;
+ };
+ };
+
mmc0_pins_default: mmc0-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
@@ -407,12 +535,34 @@ pins-low-power-pupd {
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
};
+
+ spi0_pins: spi0-default-pins {
+ pins-cs-mosi-clk {
+ pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
+ <PINMUX_GPIO134__FUNC_SPIM0_MO>,
+ <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
+ bias-disable;
+ };
+
+ pins-miso {
+ pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
+ bias-pull-down;
+ };
+ };
};

&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};

+&spi0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ mediatek,pad-select = <0>;
+};
+
&uart0 {
status = "okay";
};
--
2.35.1


2022-07-01 23:01:30

by Nícolas F. R. A. Prado

[permalink] [raw]
Subject: Re: [PATCH 07/11] arm64: dts: mediatek: cherry: Enable I2C and SPI controllers

On Thu, Jun 30, 2022 at 05:33:12PM +0200, AngeloGioacchino Del Regno wrote:
> This platform uses eight I2C controllers and one SPI controller:
> in preparation for enabling devices attached to these controllers,
> add basic configuration to enable the busses.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 2f70341bba91..23a86d07274c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -9,6 +9,13 @@
>
> / {
> aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c7 = &i2c7;
> mmc0 = &mmc0;
> serial0 = &uart0;
> };
> @@ -88,6 +95,65 @@ ppvar_sys: regulator-ppvar-sys {
> };
> };
>
> +&i2c0 {
> + status = "okay";
> +
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pin>;

Very nitpicky: you could name it "i2c0_pins" to be consistent with the others
(including SPI on this patch).

> +};
[..]
> +&i2c7 {
> + #address-cells = <1>;
> + #size-cells = <0>;

These *-cells are already defined in the parent dtsi, so drop.

Reviewed-by: N?colas F. R. A. Prado <[email protected]>

Thanks,
N?colas