2022-07-01 06:59:41

by Liu Ying

[permalink] [raw]
Subject: [PATCH 0/3] drm/bridge: fsl-ldb: A few fixes

Hi,

This series contains three fixes for the fsl-ldb bridge driver.

Patch 1/3 fixes mode clock rate validation.
Patch 2/3 fixes LVDS dual link mode.
Patch 3/3 fixes input data enable signal polarity.

Liu Ying (3):
drm/bridge: fsl-ldb: Fix mode clock rate validation
drm/bridge: fsl-ldb: Enable split mode for LVDS dual link
drm/bridge: fsl-ldb: Drop DE signal polarity inversion

drivers/gpu/drm/bridge/fsl-ldb.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)

--
2.25.1


2022-07-01 06:59:49

by Liu Ying

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Subject: [PATCH 2/3] drm/bridge: fsl-ldb: Enable split mode for LVDS dual link

When LVDS dual link is used, we have to enable the LDB_CTRL_SPLIT_MODE bit.

Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Jonas Karlman <[email protected]>
Cc: Jernej Skrabec <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
drivers/gpu/drm/bridge/fsl-ldb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 3cb3b310e283..d4f005eef6f6 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -153,7 +153,7 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
reg = LDB_CTRL_CH0_ENABLE;

if (fsl_ldb->lvds_dual_link)
- reg |= LDB_CTRL_CH1_ENABLE;
+ reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE;

if (lvds_format_24bpp) {
reg |= LDB_CTRL_CH0_DATA_WIDTH;
--
2.25.1

2022-07-01 07:11:18

by Liu Ying

[permalink] [raw]
Subject: [PATCH 3/3] drm/bridge: fsl-ldb: Drop DE signal polarity inversion

It's unnecessary to invert input data enable signal polarity
according to the output one. Let's drop the inversion.
Since ->atomic_check() does nothing more than the inversion,
it can be dropped entirely as well.

Without this patch, 'koe,tx26d202vm0bwa' LVDS panel connected
with i.MX8MP EVK board does not show any data on screen.

Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Jonas Karlman <[email protected]>
Cc: Jernej Skrabec <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
drivers/gpu/drm/bridge/fsl-ldb.c | 17 -----------------
1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index d4f005eef6f6..4b503c544256 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -74,22 +74,6 @@ static int fsl_ldb_attach(struct drm_bridge *bridge,
bridge, flags);
}

-static int fsl_ldb_atomic_check(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- /* Invert DE signal polarity. */
- bridge_state->input_bus_cfg.flags &= ~(DRM_BUS_FLAG_DE_LOW |
- DRM_BUS_FLAG_DE_HIGH);
- if (bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW)
- bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH;
- else if (bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_HIGH)
- bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_LOW;
-
- return 0;
-}
-
static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
@@ -241,7 +225,6 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,

static const struct drm_bridge_funcs funcs = {
.attach = fsl_ldb_attach,
- .atomic_check = fsl_ldb_atomic_check,
.atomic_enable = fsl_ldb_atomic_enable,
.atomic_disable = fsl_ldb_atomic_disable,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
--
2.25.1

2022-07-01 07:19:31

by Liu Ying

[permalink] [raw]
Subject: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation

With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.

Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Jonas Karlman <[email protected]>
Cc: Jernej Skrabec <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
drivers/gpu/drm/bridge/fsl-ldb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index b2675c769a55..3cb3b310e283 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -233,7 +233,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,
{
struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);

- if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000))
+ if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
return MODE_CLOCK_HIGH;

return MODE_OK;
--
2.25.1

2022-07-01 11:07:17

by Marek Vasut

[permalink] [raw]
Subject: Re: [PATCH 3/3] drm/bridge: fsl-ldb: Drop DE signal polarity inversion

On 7/1/22 08:56, Liu Ying wrote:
> It's unnecessary to invert input data enable signal polarity
> according to the output one. Let's drop the inversion.
> Since ->atomic_check() does nothing more than the inversion,
> it can be dropped entirely as well.
>
> Without this patch, 'koe,tx26d202vm0bwa' LVDS panel connected
> with i.MX8MP EVK board does not show any data on screen.

I send exactly the same change yesterday:
[PATCH] drm: bridge: ldb: Drop DE flip from Freescale i.MX8MP LDB bridge

So either can be applied.

Reviewed-by: Marek Vasut <[email protected]>

2022-07-01 11:07:26

by Marek Vasut

[permalink] [raw]
Subject: Re: [PATCH 2/3] drm/bridge: fsl-ldb: Enable split mode for LVDS dual link

On 7/1/22 08:56, Liu Ying wrote:
> When LVDS dual link is used, we have to enable the LDB_CTRL_SPLIT_MODE bit.
>
> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
> Cc: Andrzej Hajda <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Robert Foss <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Jonas Karlman <[email protected]>
> Cc: Jernej Skrabec <[email protected]>
> Cc: David Airlie <[email protected]>
> Cc: Daniel Vetter <[email protected]>
> Cc: Sam Ravnborg <[email protected]>
> Cc: Marek Vasut <[email protected]>
> Cc: NXP Linux Team <[email protected]>
> Signed-off-by: Liu Ying <[email protected]>

Reviewed-by: Marek Vasut <[email protected]>

2022-07-01 11:26:04

by Marek Vasut

[permalink] [raw]
Subject: Re: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation

On 7/1/22 08:56, Liu Ying wrote:
> With LVDS dual link, up to 160MHz mode clock rate is supported.
> With LVDS single link, up to 80MHz mode clock rate is supported.
> Fix mode clock rate validation by swapping the maximum mode clock
> rates of the two link modes.
>
> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
> Cc: Andrzej Hajda <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Robert Foss <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Jonas Karlman <[email protected]>
> Cc: Jernej Skrabec <[email protected]>
> Cc: David Airlie <[email protected]>
> Cc: Daniel Vetter <[email protected]>
> Cc: Sam Ravnborg <[email protected]>
> Cc: Marek Vasut <[email protected]>
> Cc: NXP Linux Team <[email protected]>
> Signed-off-by: Liu Ying <[email protected]>

Reviewed-by: Marek Vasut <[email protected]>

2022-07-04 14:34:40

by Neil Armstrong

[permalink] [raw]
Subject: Re: [PATCH 0/3] drm/bridge: fsl-ldb: A few fixes

Hi,

On Fri, 1 Jul 2022 14:56:31 +0800, Liu Ying wrote:
> This series contains three fixes for the fsl-ldb bridge driver.
>
> Patch 1/3 fixes mode clock rate validation.
> Patch 2/3 fixes LVDS dual link mode.
> Patch 3/3 fixes input data enable signal polarity.
>
> Liu Ying (3):
> drm/bridge: fsl-ldb: Fix mode clock rate validation
> drm/bridge: fsl-ldb: Enable split mode for LVDS dual link
> drm/bridge: fsl-ldb: Drop DE signal polarity inversion
>
> [...]

Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)

[1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=591129d3db266648823bb953ebbc28c92e059bf3
[2/3] drm/bridge: fsl-ldb: Enable split mode for LVDS dual link
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=57ef278ef125e9188474a164f35dcffc69836d01
[3/3] drm/bridge: fsl-ldb: Drop DE signal polarity inversion
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=1dbc790b4d416dacb124a6acd05f88a0bcf3be39

--
Neil

2022-07-06 13:41:34

by Robert Foss

[permalink] [raw]
Subject: Re: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation

On Fri, 1 Jul 2022 at 13:00, Marek Vasut <[email protected]> wrote:
>
> On 7/1/22 08:56, Liu Ying wrote:
> > With LVDS dual link, up to 160MHz mode clock rate is supported.
> > With LVDS single link, up to 80MHz mode clock rate is supported.
> > Fix mode clock rate validation by swapping the maximum mode clock
> > rates of the two link modes.
> >
> > Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
> > Cc: Andrzej Hajda <[email protected]>
> > Cc: Neil Armstrong <[email protected]>
> > Cc: Robert Foss <[email protected]>
> > Cc: Laurent Pinchart <[email protected]>
> > Cc: Jonas Karlman <[email protected]>
> > Cc: Jernej Skrabec <[email protected]>
> > Cc: David Airlie <[email protected]>
> > Cc: Daniel Vetter <[email protected]>
> > Cc: Sam Ravnborg <[email protected]>
> > Cc: Marek Vasut <[email protected]>
> > Cc: NXP Linux Team <[email protected]>
> > Signed-off-by: Liu Ying <[email protected]>
>
> Reviewed-by: Marek Vasut <[email protected]>

Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it
was submitted first and is identical.

2022-07-07 08:40:26

by Neil Armstrong

[permalink] [raw]
Subject: Re: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation

Hi,

On 06/07/2022 15:34, Robert Foss wrote:
> On Fri, 1 Jul 2022 at 13:00, Marek Vasut <[email protected]> wrote:
>>
>> On 7/1/22 08:56, Liu Ying wrote:
>>> With LVDS dual link, up to 160MHz mode clock rate is supported.
>>> With LVDS single link, up to 80MHz mode clock rate is supported.
>>> Fix mode clock rate validation by swapping the maximum mode clock
>>> rates of the two link modes.
>>>
>>> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
>>> Cc: Andrzej Hajda <[email protected]>
>>> Cc: Neil Armstrong <[email protected]>
>>> Cc: Robert Foss <[email protected]>
>>> Cc: Laurent Pinchart <[email protected]>
>>> Cc: Jonas Karlman <[email protected]>
>>> Cc: Jernej Skrabec <[email protected]>
>>> Cc: David Airlie <[email protected]>
>>> Cc: Daniel Vetter <[email protected]>
>>> Cc: Sam Ravnborg <[email protected]>
>>> Cc: Marek Vasut <[email protected]>
>>> Cc: NXP Linux Team <[email protected]>
>>> Signed-off-by: Liu Ying <[email protected]>
>>
>> Reviewed-by: Marek Vasut <[email protected]>
>
> Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it
> was submitted first and is identical.

Seems we'll have a conflict when drm-misc-fixes is backmerged in drm-misc-next !

Neil