From: Nandhini Srikandan <[email protected]>
Hi,
This patch enables support for DW SPI on Intel Thunder Bay.
This patch set also enables master mode for latest Designware SPI versions.
Patch 1: Fixed dw_spi_ip_is macro with the missing underscore.
Patch 2: DW SPI DT bindings for Intel Thunder Bay SoC.
Patch 3: Adds master mode support for Designware SPI controller.
Patch 4: Adds support for Designware SPI on Intel Thunder Bay SoC.
The driver is tested on Keem Bay and Thunder Bay evaluation board
Summary:
Changes from v4:
1) Reordered master mode selection patch and Thunder Bay support patch.
2) The typo fix for macro dw_spi_ip_is is made into seperate patch.
Changes from v3:
1) Dropped SSTE support in this patch.
2) Rebased to the latest code.
Changes from v2:
1) SSTE support made using dt and created seperate patches.
2) SPI controller master mode selection made common to all DW SPI controllers.
3) Using a common init function for both keem bay and thunder bay.
Changes from v1:
1) Designware CR0 specific macros are named in a generic way.
2) SPI CAP macros are named in generic way rather than naming project specific.
3) SPI KEEM BAY specific macros are replaced by generic macros.
4) Resued the existing SPI deassert API instead of adding another reset
Changes in patches:
Patch 1:
--------
Changes from v4:
1) Newly introduced in v5 as seperate patch.
Patch 2:
--------
Changes from v4/v3/v2/v1:
1) No change in this patch.
Patch 3:
--------
Changes from v4:
1) Reordered the patch.
2) Setting CTRLR0 BIT31 is done conditionally for 1.02a version.
Changes from v3:
1) Corrected dw_spi_ip_is macro with the missing underscore.
2) Setting CTRLR0 BIT31 without any condition check as in older version of
DW SPI controller this bit is reserved.
Changes from v2/v1:
1)Newly introduced in v3 to make master mode selection as seperate patch
Patch 4:
--------
Changes from v4:
1) Reordered the patch.
Changes from v3:
1) No changes.
Changes from v2:
1) Init function is made common for Keem Bay and Thunder Bay.
Thanks & Regards,
Nandhini
Nandhini Srikandan (4):
spi: dw: Fix IP-core versions macro
dt-bindings: spi: Add bindings for Intel Thunder Bay SoC
spi: dw: Add support for master mode selection for DWC SSI controller
spi: dw: Add support for Intel Thunder Bay SPI controller
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
drivers/spi/spi-dw-core.c | 5 +++--
drivers/spi/spi-dw-mmio.c | 8 ++++----
drivers/spi/spi-dw.h | 13 +++----------
4 files changed, 12 insertions(+), 16 deletions(-)
--
2.17.1
From: Nandhini Srikandan <[email protected]>
Add support for Intel Thunder Bay SPI controller, which uses DesignWare
DWC_ssi core and also add common init function for both Keem Bay and
Thunder Bay.
Signed-off-by: Nandhini Srikandan <[email protected]>
---
drivers/spi/spi-dw-mmio.c | 8 ++++----
drivers/spi/spi-dw.h | 3 +--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 5101c4c6017b..26c40ea6dd12 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev,
return 0;
}
-static int dw_spi_keembay_init(struct platform_device *pdev,
- struct dw_spi_mmio *dwsmmio)
+static int dw_spi_intel_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
{
dwsmmio->dws.ip = DW_HSSI_ID;
- dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;
return 0;
}
@@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
- { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
+ { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
+ { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
{ /* end of table */}
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 8b8f924ac410..9e8eb2b52d5c 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -31,8 +31,7 @@
/* DW SPI controller capabilities */
#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
-#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
-#define DW_SPI_CAP_DFS32 BIT(2)
+#define DW_SPI_CAP_DFS32 BIT(1)
/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
#define DW_SPI_CTRLR0 0x00
--
2.17.1
From: Nandhini Srikandan <[email protected]>
Add documentation for SPI controller in Intel Thunder Bay SoC.
Signed-off-by: Nandhini Srikandan <[email protected]>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index d7e08b03e204..5ecd996ebf33 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -61,6 +61,8 @@ properties:
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
+ - description: Intel Thunder Bay SPI Controller
+ const: intel,thunderbay-ssi
- description: Baikal-T1 SPI Controller
const: baikal,bt1-ssi
- description: Baikal-T1 System Boot SPI Controller
--
2.17.1
From: Nandhini Srikandan <[email protected]>
Add support to select the controller mode as master mode by setting
Bit 31 of CTRLR0 register. This feature is supported for controller
versions above v1.02.
Signed-off-by: Nandhini Srikandan <[email protected]>
---
drivers/spi/spi-dw-core.c | 5 +++--
drivers/spi/spi-dw.h | 8 +-------
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index ecea471ff42c..41ae21e1b879 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
if (spi->mode & SPI_LOOP)
cr0 |= DW_HSSI_CTRLR0_SRL;
- if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
- cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
+ /* CTRLR0[31] MST */
+ if (dw_spi_ver_is_ge(dws, HSSI, 102A))
+ cr0 |= DW_HSSI_CTRLR0_MST;
}
return cr0;
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 79d853f6d192..8b8f924ac410 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -94,13 +94,7 @@
#define DW_HSSI_CTRLR0_SCPOL BIT(9)
#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
#define DW_HSSI_CTRLR0_SRL BIT(13)
-
-/*
- * For Keem Bay, CTRLR0[31] is used to select controller mode.
- * 0: SSI is slave
- * 1: SSI is master
- */
-#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
+#define DW_HSSI_CTRLR0_MST BIT(31)
/* Bit fields in CTRLR1 */
#define DW_SPI_NDF_MASK GENMASK(15, 0)
--
2.17.1
On Wed, 06 Jul 2022 12:20:37 +0800, [email protected] wrote:
> From: Nandhini Srikandan <[email protected]>
>
> Add documentation for SPI controller in Intel Thunder Bay SoC.
>
> Signed-off-by: Nandhini Srikandan <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Wed, Jul 06, 2022 at 12:20:38PM +0800, [email protected] wrote:
> From: Nandhini Srikandan <[email protected]>
>
> Add support to select the controller mode as master mode by setting
> Bit 31 of CTRLR0 register. This feature is supported for controller
> versions above v1.02.
>
> Signed-off-by: Nandhini Srikandan <[email protected]>
Acked-by: Serge Semin <[email protected]>
-Sergey
> ---
> drivers/spi/spi-dw-core.c | 5 +++--
> drivers/spi/spi-dw.h | 8 +-------
> 2 files changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index ecea471ff42c..41ae21e1b879 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
> if (spi->mode & SPI_LOOP)
> cr0 |= DW_HSSI_CTRLR0_SRL;
>
> - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
> - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
> + /* CTRLR0[31] MST */
> + if (dw_spi_ver_is_ge(dws, HSSI, 102A))
> + cr0 |= DW_HSSI_CTRLR0_MST;
> }
>
> return cr0;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 79d853f6d192..8b8f924ac410 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -94,13 +94,7 @@
> #define DW_HSSI_CTRLR0_SCPOL BIT(9)
> #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
> #define DW_HSSI_CTRLR0_SRL BIT(13)
> -
> -/*
> - * For Keem Bay, CTRLR0[31] is used to select controller mode.
> - * 0: SSI is slave
> - * 1: SSI is master
> - */
> -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
> +#define DW_HSSI_CTRLR0_MST BIT(31)
>
> /* Bit fields in CTRLR1 */
> #define DW_SPI_NDF_MASK GENMASK(15, 0)
> --
> 2.17.1
>
On Wed, Jul 06, 2022 at 12:20:37PM +0800, [email protected] wrote:
> From: Nandhini Srikandan <[email protected]>
>
> Add documentation for SPI controller in Intel Thunder Bay SoC.
>
> Signed-off-by: Nandhini Srikandan <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Serge Semin <[email protected]>
-Sergey
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index d7e08b03e204..5ecd996ebf33 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -61,6 +61,8 @@ properties:
> - const: snps,dw-apb-ssi
> - description: Intel Keem Bay SPI Controller
> const: intel,keembay-ssi
> + - description: Intel Thunder Bay SPI Controller
> + const: intel,thunderbay-ssi
> - description: Baikal-T1 SPI Controller
> const: baikal,bt1-ssi
> - description: Baikal-T1 System Boot SPI Controller
> --
> 2.17.1
>
On Wed, Jul 06, 2022 at 12:20:39PM +0800, [email protected] wrote:
> From: Nandhini Srikandan <[email protected]>
>
> Add support for Intel Thunder Bay SPI controller, which uses DesignWare
> DWC_ssi core and also add common init function for both Keem Bay and
> Thunder Bay.
>
> Signed-off-by: Nandhini Srikandan <[email protected]>
Acked-by: Serge Semin <[email protected]>
-Sergey
> ---
> drivers/spi/spi-dw-mmio.c | 8 ++++----
> drivers/spi/spi-dw.h | 3 +--
> 2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 5101c4c6017b..26c40ea6dd12 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev,
> return 0;
> }
>
> -static int dw_spi_keembay_init(struct platform_device *pdev,
> - struct dw_spi_mmio *dwsmmio)
> +static int dw_spi_intel_init(struct platform_device *pdev,
> + struct dw_spi_mmio *dwsmmio)
> {
> dwsmmio->dws.ip = DW_HSSI_ID;
> - dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;
>
> return 0;
> }
> @@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
> { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
> { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
> { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
> - { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
> + { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
> + { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
> { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
> { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
> { /* end of table */}
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 8b8f924ac410..9e8eb2b52d5c 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -31,8 +31,7 @@
>
> /* DW SPI controller capabilities */
> #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
> -#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
> -#define DW_SPI_CAP_DFS32 BIT(2)
> +#define DW_SPI_CAP_DFS32 BIT(1)
>
> /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
> #define DW_SPI_CTRLR0 0x00
> --
> 2.17.1
>