From: Conor Dooley <[email protected]>
Hey Uwe, all,
(~same cover as v5)
Added some extra patches so I have a cover letter this time.
You pointed out that I was overriding npwmcells in the driver and I
realised that the dt & binding were not correct so I have added two
simple patches to deal with that. The dts patch I will take in my tree
once the binding is applied.
For the maintainers entry, I mentioned before that I have several
changes in-flight for it. We are late~(ish)~ in the cycle so I doubt
you'll be applying this for v5.20, but in the off chance you do - I
would be happy to send it (with your Ack) alongside an i2c addition
that is "deferred". I rebased it ~today~ on top of an additional change
so it may not apply for you.
In your review of v3, you had a lot of comments about the period and
duty cycle calculations, so I have had another run at them. I converted
the period calculation to "search" from the bottom up for the suitable
prescale value. The duty cycle calculation has been fixed - the problem
was exactly what I suspected in my replies to your review. I had to block
the use of a 0xFF period_steps register value (which I think should be
covered by the updated comment and limitation #2).
Beyond that, I have rebased on -next and converted to the devm_ stuff
in probe that was recently added & dropped remove() - as requested.
I added locking to protect the period racing, changed the #defines and
switched to returning -EINVAL when the period is locked to a value
greater than that requested.
I'll take the dts change myself once the rest is merged.
Thanks,
Conor.
Changes from v6:
- Dropped an unused variable that I'd missed
- Actually check the return values of the mutex lock()s
- Re-rebased on -next for the MAINTAINERS patch (again...)
Changes from v5:
- switched to a mutex b/c we must sleep with the lock taken
- simplified the locking in apply() and added locking to get_state()
- reworked apply() as requested
- removed the loop in the period calculation (thanks Uwe!)
- add a copy of the enable registers in the driver to save on reads.
- remove the second (useless) write to sync_update
- added some missing rounding in get_state()
- couple other minor cleanups as requested in:
https://lore.kernel.org/linux-riscv/[email protected]/
Changes from v4:
- dropped some accidentally added files
Conor Dooley (4):
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: fix the icicle's #pwm-cells
pwm: add microchip soft ip corePWM driver
MAINTAINERS: add pwm to PolarFire SoC entry
.../bindings/pwm/microchip,corepwm.yaml | 4 +-
MAINTAINERS | 1 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 371 ++++++++++++++++++
6 files changed, 387 insertions(+), 2 deletions(-)
create mode 100644 drivers/pwm/pwm-microchip-core.c
base-commit: a3fd3ca134d9485a0f9a7bdcffd7f8bae27f79d3
--
2.37.1
From: Conor Dooley <[email protected]>
corePWM is capable of inverted operation but the binding requires
\#pwm-cells of 2. Expand the binding to support setting the polarity.
Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding")
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
index a7fae1772a81..cd8e9a8907f8 100644
--- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -30,7 +30,9 @@ properties:
maxItems: 1
"#pwm-cells":
- const: 2
+ enum: [2, 3]
+ description:
+ The only flag supported by the controller is PWM_POLARITY_INVERTED.
microchip,sync-update-mask:
description: |
--
2.37.1
From: Conor Dooley <[email protected]>
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support inverted operation, so update the entry to correctly report its
capabilities.
Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 0d28858b83f2..e09a13aef268 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
clocks = <&fabric_clk3>;
status = "disabled";
};
--
2.37.1
From: Conor Dooley <[email protected]>
Add a driver that supports the Microchip FPGA "soft" PWM IP core.
Signed-off-by: Conor Dooley <[email protected]>
---
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 371 +++++++++++++++++++++++++++++++
3 files changed, 382 insertions(+)
create mode 100644 drivers/pwm/pwm-microchip-core.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 904de8d61828..007ea5750e73 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -383,6 +383,16 @@ config PWM_MEDIATEK
To compile this driver as a module, choose M here: the module
will be called pwm-mediatek.
+config PWM_MICROCHIP_CORE
+ tristate "Microchip corePWM PWM support"
+ depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
+ depends on HAS_IOMEM && OF
+ help
+ PWM driver for Microchip FPGA soft IP core.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-microchip-core.
+
config PWM_MXS
tristate "Freescale MXS PWM support"
depends on ARCH_MXS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 5c08bdb817b4..43feb7cfc66a 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o
obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
+obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-core.c
new file mode 100644
index 000000000000..2d12248f86b8
--- /dev/null
+++ b/drivers/pwm/pwm-microchip-core.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * corePWM driver for Microchip "soft" FPGA IP cores.
+ *
+ * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
+ * Author: Conor Dooley <[email protected]>
+ * Documentation:
+ * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
+ *
+ * Limitations:
+ * - If the IP block is configured without "shadow registers", all register
+ * writes will take effect immediately, causing glitches on the output.
+ * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" register
+ * notifies the core that it needs to update the registers defining the
+ * waveform from the contents of the "shadow registers".
+ * - The IP block has no concept of a duty cycle, only rising/falling edges of
+ * the waveform. Unfortunately, if the rising & falling edges registers have
+ * the same value written to them the IP block will do whichever of a rising
+ * or a falling edge is possible. I.E. a 50% waveform at twice the requested
+ * period. Therefore to get a 0% waveform, the output is set the max high/low
+ * time depending on polarity.
+ * - The PWM period is set for the whole IP block not per channel. The driver
+ * will only change the period if no other PWM output is enabled.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/math.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#define PREG_TO_VAL(PREG) ((PREG) + 1)
+
+#define MCHPCOREPWM_PRESCALE_MAX 0x100
+#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff
+#define MCHPCOREPWM_PERIOD_MAX 0xff00
+
+#define MCHPCOREPWM_PRESCALE 0x00
+#define MCHPCOREPWM_PERIOD 0x04
+#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */
+#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */
+#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */
+#define MCHPCOREPWM_SYNC_UPD 0xe4
+
+struct mchp_core_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct mutex lock; /* protect the shared period */
+ void __iomem *base;
+ u32 sync_update_mask;
+ u16 channel_enabled;
+};
+
+static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip)
+{
+ return container_of(chip, struct mchp_core_pwm_chip, chip);
+}
+
+static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
+ bool enable, u64 period)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u8 channel_enable, reg_offset, shift;
+
+ /*
+ * There are two adjacent 8 bit control regs, the lower reg controls
+ * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
+ * and if so, offset by the bus width.
+ */
+ reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
+ shift = pwm->hwpwm & 7;
+
+ channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
+ channel_enable &= ~(1 << shift);
+ channel_enable |= (enable << shift);
+
+ writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
+ mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
+ mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
+
+ /*
+ * Notify the block to update the waveform from the shadow registers.
+ * The updated values will not appear on the bus until they have been
+ * applied to the waveform at the beginning of the next period. We must
+ * write these registers and wait for them to be applied before calling
+ * enable().
+ */
+ if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) {
+ writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
+ usleep_range(period, period * 2);
+ }
+}
+
+static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state, u8 prescale, u8 period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u64 duty_steps, period, tmp;
+ u16 prescale_val = PREG_TO_VAL(prescale);
+ u8 period_steps_val = PREG_TO_VAL(period_steps);
+
+ period = period_steps_val * prescale_val * NSEC_PER_SEC;
+ period = DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk));
+
+ /*
+ * Calculate the duty cycle in multiples of the prescaled period:
+ * duty_steps = duty_in_ns / step_in_ns
+ * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
+ * The code below is rearranged slightly to only divide once.
+ */
+ duty_steps = state->duty_cycle * clk_get_rate(mchp_core_pwm->clk);
+ tmp = prescale_val * NSEC_PER_SEC;
+ return div64_u64(duty_steps, tmp);
+}
+
+static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state, u64 duty_steps, u8 period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u8 posedge, negedge;
+ u8 period_steps_val = PREG_TO_VAL(period_steps);
+
+ /*
+ * Turn the output on unless posedge == negedge, in which case the
+ * duty is intended to be 0, but limitations of the IP block don't
+ * allow a zero length duty cycle - so just set the max high/low time
+ * respectively.
+ */
+ if (state->polarity == PWM_POLARITY_INVERSED) {
+ negedge = !duty_steps ? period_steps_val : 0u;
+ posedge = duty_steps;
+ } else {
+ posedge = !duty_steps ? period_steps_val : 0u;
+ negedge = duty_steps;
+ }
+
+ writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
+ writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
+}
+
+static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct pwm_state *state,
+ u8 *prescale, u8 *period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u64 tmp, clk_rate;
+
+ /*
+ * Calculate the period cycles and prescale values.
+ * The registers are each 8 bits wide & multiplied to compute the period
+ * using the formula:
+ * (clock_period) * (prescale + 1) * (period_steps + 1)
+ * so the maximum period that can be generated is 0x10000 times the
+ * period of the input clock.
+ * However, due to the design of the "hardware", it is not possible to
+ * attain a 100% duty cycle if the full range of period_steps is used.
+ * Therefore period_steps is restricted to 0xFE and the maximum multiple
+ * of the clock period attainable is 0xFF00.
+ */
+ clk_rate = clk_get_rate(mchp_core_pwm->clk);
+
+ /*
+ * If clk_rate is too big, the following multiplication might overflow.
+ * However this is implausible, as the fabric of current FPGAs cannot
+ * provide clocks at a rate high enough.
+ */
+ if (clk_rate >= NSEC_PER_SEC)
+ return -EINVAL;
+
+ tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
+
+ if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
+ *prescale = MCHPCOREPWM_PRESCALE_MAX - 1;
+ *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1;
+ return 0;
+ }
+
+ *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX);
+ /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */
+ *period_steps = div_u64(tmp, PREG_TO_VAL((u32)*prescale)) - 1;
+
+ return 0;
+}
+
+static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm,
+ u8 prescale, u8 period_steps)
+{
+ writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+}
+
+static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ struct pwm_state current_state = pwm->state;
+ bool period_locked;
+ u64 duty_steps;
+ u8 prescale, period_steps, hw_prescale, hw_period_steps;
+ int ret;
+
+ ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
+ if (ret)
+ return ret;
+
+ if (!state->enabled) {
+ mchp_core_pwm_enable(chip, pwm, false, current_state.period);
+ mutex_unlock(&mchp_core_pwm->lock);
+ return 0;
+ }
+
+ /*
+ * If the only thing that has changed is the duty cycle or the polarity,
+ * we can shortcut the calculations and just compute/apply the new duty
+ * cycle pos & neg edges
+ * As all the channels share the same period, do not allow it to be
+ * changed if any other channels are enabled.
+ * If the period is locked, it may not be possible to use a period
+ * less than that requested. In that case, we just abort.
+ */
+ period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
+
+ if (period_locked) {
+ mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
+ hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+
+ if ((period_steps * prescale) < (hw_period_steps * hw_prescale)) {
+ mutex_unlock(&mchp_core_pwm->lock);
+ return -EINVAL;
+ }
+
+ prescale = hw_prescale;
+ period_steps = hw_period_steps;
+ } else if (!current_state.enabled || current_state.period != state->period) {
+ ret = mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
+ if (ret) {
+ mutex_unlock(&mchp_core_pwm->lock);
+ return ret;
+ }
+ mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
+ } else {
+ prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+ }
+
+ duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps);
+
+ /*
+ * Because the period is per channel, it is possible that the requested
+ * duty cycle is longer than the period, in which case cap it to the
+ * period, IOW a 100% duty cycle.
+ */
+ if (duty_steps > period_steps)
+ duty_steps = period_steps + 1;
+
+ mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
+
+ mchp_core_pwm_enable(chip, pwm, true, state->period);
+
+ mutex_unlock(&mchp_core_pwm->lock);
+
+ return 0;
+}
+
+static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u16 prescale;
+ u8 period_steps, duty_steps, posedge, negedge;
+ int ret;
+
+ ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
+ if (ret)
+ return;
+
+ if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
+ state->enabled = true;
+ else
+ state->enabled = false;
+
+ prescale = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE));
+
+ period_steps = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD));
+ state->period = period_steps * prescale * NSEC_PER_SEC;
+ state->period = DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_core_pwm->clk));
+
+ posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
+ negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
+
+ if (negedge == posedge) {
+ state->duty_cycle = state->period / 2;
+ } else {
+ duty_steps = abs((s16)posedge - (s16)negedge);
+ state->duty_cycle = duty_steps * prescale * NSEC_PER_SEC;
+ state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle,
+ clk_get_rate(mchp_core_pwm->clk));
+ }
+
+ state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+
+ mutex_unlock(&mchp_core_pwm->lock);
+}
+
+static const struct pwm_ops mchp_core_pwm_ops = {
+ .apply = mchp_core_pwm_apply,
+ .get_state = mchp_core_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id mchp_core_of_match[] = {
+ {
+ .compatible = "microchip,corepwm-rtl-v4",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mchp_core_of_match);
+
+static int mchp_core_pwm_probe(struct platform_device *pdev)
+{
+ struct mchp_core_pwm_chip *mchp_pwm;
+ struct resource *regs;
+ int ret;
+
+ mchp_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL);
+ if (!mchp_pwm)
+ return -ENOMEM;
+
+ mchp_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
+ if (IS_ERR(mchp_pwm->base))
+ return PTR_ERR(mchp_pwm->base);
+
+ mchp_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(mchp_pwm->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(mchp_pwm->clk),
+ "failed to get PWM clock\n");
+
+ if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
+ &mchp_pwm->sync_update_mask))
+ mchp_pwm->sync_update_mask = 0u;
+
+ mutex_init(&mchp_pwm->lock);
+
+ mchp_pwm->chip.dev = &pdev->dev;
+ mchp_pwm->chip.ops = &mchp_core_pwm_ops;
+ mchp_pwm->chip.npwm = 16;
+
+ ret = devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
+
+ return 0;
+}
+
+static struct platform_driver mchp_core_pwm_driver = {
+ .driver = {
+ .name = "mchp-core-pwm",
+ .of_match_table = mchp_core_of_match,
+ },
+ .probe = mchp_core_pwm_probe,
+};
+module_platform_driver(mchp_core_pwm_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Conor Dooley <[email protected]>");
+MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");
--
2.37.1
From: Conor Dooley <[email protected]>
Add the newly introduced pwm driver to the existing PolarFire SoC entry.
Signed-off-by: Conor Dooley <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7d14a446df13..c785765c66b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17510,6 +17510,7 @@ F: drivers/char/hw_random/mpfs-rng.c
F: drivers/clk/microchip/clk-mpfs.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/pcie-microchip-host.c
+F: drivers/pwm/pwm-microchip-core.c
F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: drivers/spi/spi-microchip-core.c
--
2.37.1
On Thu, Jul 21, 2022 at 06:21:08PM +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
> blindly overridden by the (out of tree) driver anyway. The core can
> support inverted operation, so update the entry to correctly report its
> capabilities.
>
> Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> index 0d28858b83f2..e09a13aef268 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 {
> compatible = "microchip,corepwm-rtl-v4";
> reg = <0x0 0x41000000 0x0 0xF0>;
> microchip,sync-update-mask = /bits/ 32 <0>;
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> clocks = <&fabric_clk3>;
> status = "disabled";
> };
I checked there are no consumers that need adaption, so:
Reviewed-by: Uwe Kleine-K?nig <[email protected]>
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On Thu, Jul 21, 2022 at 06:21:07PM +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> corePWM is capable of inverted operation but the binding requires
> \#pwm-cells of 2. Expand the binding to support setting the polarity.
>
> Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding")
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
I'm surprised by myself I didn't notice this when acking df77f7735786,
*shrug*.
Acked-by: Uwe Kleine-K?nig <[email protected]>
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Hello,
On Thu, Jul 21, 2022 at 06:21:09PM +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Add a driver that supports the Microchip FPGA "soft" PWM IP core.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> drivers/pwm/Kconfig | 10 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-microchip-core.c | 371 +++++++++++++++++++++++++++++++
> 3 files changed, 382 insertions(+)
> create mode 100644 drivers/pwm/pwm-microchip-core.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 904de8d61828..007ea5750e73 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -383,6 +383,16 @@ config PWM_MEDIATEK
> To compile this driver as a module, choose M here: the module
> will be called pwm-mediatek.
>
> +config PWM_MICROCHIP_CORE
> + tristate "Microchip corePWM PWM support"
> + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
> + depends on HAS_IOMEM && OF
> + help
> + PWM driver for Microchip FPGA soft IP core.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-microchip-core.
> +
> config PWM_MXS
> tristate "Freescale MXS PWM support"
> depends on ARCH_MXS || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 5c08bdb817b4..43feb7cfc66a 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
> obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
> obj-$(CONFIG_PWM_MESON) += pwm-meson.o
> obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
> +obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
> obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
> obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
> obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
> diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-core.c
> new file mode 100644
> index 000000000000..2d12248f86b8
> --- /dev/null
> +++ b/drivers/pwm/pwm-microchip-core.c
> @@ -0,0 +1,371 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * corePWM driver for Microchip "soft" FPGA IP cores.
> + *
> + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
> + * Author: Conor Dooley <[email protected]>
> + * Documentation:
> + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
> + *
> + * Limitations:
> + * - If the IP block is configured without "shadow registers", all register
> + * writes will take effect immediately, causing glitches on the output.
> + * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" register
> + * notifies the core that it needs to update the registers defining the
> + * waveform from the contents of the "shadow registers".
> + * - The IP block has no concept of a duty cycle, only rising/falling edges of
> + * the waveform. Unfortunately, if the rising & falling edges registers have
> + * the same value written to them the IP block will do whichever of a rising
> + * or a falling edge is possible. I.E. a 50% waveform at twice the requested
> + * period. Therefore to get a 0% waveform, the output is set the max high/low
> + * time depending on polarity.
> + * - The PWM period is set for the whole IP block not per channel. The driver
> + * will only change the period if no other PWM output is enabled.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/math.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +
> +#define PREG_TO_VAL(PREG) ((PREG) + 1)
> +
> +#define MCHPCOREPWM_PRESCALE_MAX 0x100
> +#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff
> +#define MCHPCOREPWM_PERIOD_MAX 0xff00
> +
> +#define MCHPCOREPWM_PRESCALE 0x00
> +#define MCHPCOREPWM_PERIOD 0x04
> +#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */
> +#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */
> +#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */
> +#define MCHPCOREPWM_SYNC_UPD 0xe4
> +
> +struct mchp_core_pwm_chip {
> + struct pwm_chip chip;
> + struct clk *clk;
> + struct mutex lock; /* protect the shared period */
> + void __iomem *base;
> + u32 sync_update_mask;
> + u16 channel_enabled;
> +};
> +
> +static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip)
> +{
> + return container_of(chip, struct mchp_core_pwm_chip, chip);
> +}
> +
> +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
> + bool enable, u64 period)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u8 channel_enable, reg_offset, shift;
> +
> + /*
> + * There are two adjacent 8 bit control regs, the lower reg controls
> + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
> + * and if so, offset by the bus width.
> + */
> + reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
> + shift = pwm->hwpwm & 7;
> +
> + channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
> + channel_enable &= ~(1 << shift);
> + channel_enable |= (enable << shift);
> +
> + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
> + mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
> + mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
> +
> + /*
> + * Notify the block to update the waveform from the shadow registers.
> + * The updated values will not appear on the bus until they have been
> + * applied to the waveform at the beginning of the next period. We must
> + * write these registers and wait for them to be applied before calling
> + * enable().
What does "calling enable()" mean? There is no such function or callback
with that name?!
> + */
> + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) {
> + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
> + usleep_range(period, period * 2);
So if period = 5000 *ns* you sleep between 5000 and 10000 *us* here?
> + }
> +}
> +
> +static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state, u8 prescale, u8 period_steps)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u64 duty_steps, period, tmp;
> + u16 prescale_val = PREG_TO_VAL(prescale);
> + u8 period_steps_val = PREG_TO_VAL(period_steps);
Can it happen that period_steps is 0xff? Then period_steps_val ends up
being 0.
> +
> + period = period_steps_val * prescale_val * NSEC_PER_SEC;
> + period = DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk));
The value you are calculating for period isn't used?!
> +
> + /*
> + * Calculate the duty cycle in multiples of the prescaled period:
> + * duty_steps = duty_in_ns / step_in_ns
> + * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
> + * The code below is rearranged slightly to only divide once.
> + */
> + duty_steps = state->duty_cycle * clk_get_rate(mchp_core_pwm->clk);
> + tmp = prescale_val * NSEC_PER_SEC;
> + return div64_u64(duty_steps, tmp);
> +}
> +
> +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state, u64 duty_steps, u8 period_steps)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u8 posedge, negedge;
> + u8 period_steps_val = PREG_TO_VAL(period_steps);
> +
> + /*
> + * Turn the output on unless posedge == negedge, in which case the
> + * duty is intended to be 0, but limitations of the IP block don't
> + * allow a zero length duty cycle - so just set the max high/low time
> + * respectively.
> + */
I don't understand that comment. Maybe you mean?:
/*
* Setting posedge == negedge doesn't yield a constant output,
* so that's an unsuitable setting to model duty_steps = 0.
* In that case set the unwanted edge to a value that never
* triggers.
*/
> + if (state->polarity == PWM_POLARITY_INVERSED) {
> + negedge = !duty_steps ? period_steps_val : 0u;
> + posedge = duty_steps;
> + } else {
> + posedge = !duty_steps ? period_steps_val : 0u;
> + negedge = duty_steps;
> + }
> +
> + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
> + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
> +}
> +
> +static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct pwm_state *state,
> + u8 *prescale, u8 *period_steps)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u64 tmp, clk_rate;
> +
> + /*
> + * Calculate the period cycles and prescale values.
> + * The registers are each 8 bits wide & multiplied to compute the period
> + * using the formula:
> + * (clock_period) * (prescale + 1) * (period_steps + 1)
> + * so the maximum period that can be generated is 0x10000 times the
> + * period of the input clock.
> + * However, due to the design of the "hardware", it is not possible to
> + * attain a 100% duty cycle if the full range of period_steps is used.
> + * Therefore period_steps is restricted to 0xFE and the maximum multiple
> + * of the clock period attainable is 0xFF00.
> + */
> + clk_rate = clk_get_rate(mchp_core_pwm->clk);
> +
> + /*
> + * If clk_rate is too big, the following multiplication might overflow.
> + * However this is implausible, as the fabric of current FPGAs cannot
> + * provide clocks at a rate high enough.
> + */
> + if (clk_rate >= NSEC_PER_SEC)
> + return -EINVAL;
> +
> + tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
> +
> + if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
> + *prescale = MCHPCOREPWM_PRESCALE_MAX - 1;
why -1 here?
> + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1;
> + return 0;
> + }
> +
> + *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX);
> + /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */
That should explain the cast to u32? If this were really necessary
(hint: it isn't) it would IMHO be better to hide that cast in the macro.
> + *period_steps = div_u64(tmp, PREG_TO_VAL((u32)*prescale)) - 1;
> +
> + return 0;
> +}
> +
> +static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm,
> + u8 prescale, u8 period_steps)
> +{
> + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
> + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
> +}
> +
> +static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + struct pwm_state current_state = pwm->state;
> + bool period_locked;
> + u64 duty_steps;
> + u8 prescale, period_steps, hw_prescale, hw_period_steps;
> + int ret;
> +
> + ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
> + if (ret)
> + return ret;
I would have used mutex_lock() here. Why should a signal prevent
reconfiguration of the PWM?
> +
> + if (!state->enabled) {
> + mchp_core_pwm_enable(chip, pwm, false, current_state.period);
> + mutex_unlock(&mchp_core_pwm->lock);
> + return 0;
> + }
> +
> + /*
> + * If the only thing that has changed is the duty cycle or the polarity,
> + * we can shortcut the calculations and just compute/apply the new duty
> + * cycle pos & neg edges
> + * As all the channels share the same period, do not allow it to be
> + * changed if any other channels are enabled.
> + * If the period is locked, it may not be possible to use a period
> + * less than that requested. In that case, we just abort.
> + */
> + period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
> +
> + if (period_locked) {
> + mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
> + hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
> + hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
> +
> + if ((period_steps * prescale) < (hw_period_steps * hw_prescale)) {
You need
if ((period_steps + 1) * (prescale + 1) < (hw_period_steps + 1) * (hw_prescale + 1))
here, don't you?
> + mutex_unlock(&mchp_core_pwm->lock);
> + return -EINVAL;
> + }
> +
> + prescale = hw_prescale;
> + period_steps = hw_period_steps;
The two hw_* variables are only used in this branch. So their
declaration can move into here.
> + } else if (!current_state.enabled || current_state.period != state->period) {
> + ret = mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
> + if (ret) {
> + mutex_unlock(&mchp_core_pwm->lock);
> + return ret;
> + }
> + mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
> + } else {
> + prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
> + period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
> + }
> +
> + duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps);
> +
> + /*
> + * Because the period is per channel, it is possible that the requested
> + * duty cycle is longer than the period, in which case cap it to the
> + * period, IOW a 100% duty cycle.
> + */
> + if (duty_steps > period_steps)
> + duty_steps = period_steps + 1;
> +
> + mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
> +
> + mchp_core_pwm_enable(chip, pwm, true, state->period);
> +
> + mutex_unlock(&mchp_core_pwm->lock);
> +
> + return 0;
> +}
> +
> +static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
> + struct pwm_state *state)
> +{
> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
> + u16 prescale;
> + u8 period_steps, duty_steps, posedge, negedge;
> + int ret;
> +
> + ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
> + if (ret)
> + return;
> +
> + if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
channel_enabled is initialized to 0 in .probe(), so a PWM is never
diagnosed to be running when the core initially wants to determine the
current state.
> + state->enabled = true;
> + else
> + state->enabled = false;
> +
> + prescale = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE));
> +
> + period_steps = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD));
> + state->period = period_steps * prescale * NSEC_PER_SEC;
> + state->period = DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_core_pwm->clk));
> +
> + posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
> + negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
> +
> + if (negedge == posedge) {
> + state->duty_cycle = state->period / 2;
I thought that's:
state->duty_cycle = state->period;
state->period *= 2;
?
> + } else {
> + duty_steps = abs((s16)posedge - (s16)negedge);
> + state->duty_cycle = duty_steps * prescale * NSEC_PER_SEC;
> + state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle,
> + clk_get_rate(mchp_core_pwm->clk));
> + }
> +
> + state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
> +
> + mutex_unlock(&mchp_core_pwm->lock);
> +}
> +
> +static const struct pwm_ops mchp_core_pwm_ops = {
> + .apply = mchp_core_pwm_apply,
> + .get_state = mchp_core_pwm_get_state,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct of_device_id mchp_core_of_match[] = {
> + {
> + .compatible = "microchip,corepwm-rtl-v4",
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mchp_core_of_match);
> +
> +static int mchp_core_pwm_probe(struct platform_device *pdev)
> +{
> + struct mchp_core_pwm_chip *mchp_pwm;
> + struct resource *regs;
> + int ret;
> +
> + mchp_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL);
> + if (!mchp_pwm)
> + return -ENOMEM;
> +
> + mchp_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
> + if (IS_ERR(mchp_pwm->base))
> + return PTR_ERR(mchp_pwm->base);
> +
> + mchp_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
> + if (IS_ERR(mchp_pwm->clk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(mchp_pwm->clk),
> + "failed to get PWM clock\n");
> +
> + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
> + &mchp_pwm->sync_update_mask))
> + mchp_pwm->sync_update_mask = 0u;
> +
> + mutex_init(&mchp_pwm->lock);
> +
> + mchp_pwm->chip.dev = &pdev->dev;
> + mchp_pwm->chip.ops = &mchp_core_pwm_ops;
> + mchp_pwm->chip.npwm = 16;
> +
> + ret = devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
> +
> + return 0;
> +}
> +
> +static struct platform_driver mchp_core_pwm_driver = {
> + .driver = {
> + .name = "mchp-core-pwm",
> + .of_match_table = mchp_core_of_match,
> + },
> + .probe = mchp_core_pwm_probe,
> +};
> +module_platform_driver(mchp_core_pwm_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Conor Dooley <[email protected]>");
> +MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 02/08/2022 09:46, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Jul 21, 2022 at 06:21:09PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add a driver that supports the Microchip FPGA "soft" PWM IP core.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> +static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
>> + bool enable, u64 period)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + u8 channel_enable, reg_offset, shift;
>> +
>> + /*
>> + * There are two adjacent 8 bit control regs, the lower reg controls
>> + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
>> + * and if so, offset by the bus width.
>> + */
>> + reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
>> + shift = pwm->hwpwm & 7;
>> +
>> + channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
>> + channel_enable &= ~(1 << shift);
>> + channel_enable |= (enable << shift);
>> +
>> + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
>> + mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
>> + mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
>> +
>> + /*
>> + * Notify the block to update the waveform from the shadow registers.
>> + * The updated values will not appear on the bus until they have been
>> + * applied to the waveform at the beginning of the next period. We must
>> + * write these registers and wait for them to be applied before calling
>> + * enable().
>
> What does "calling enable()" mean? There is no such function or callback
> with that name?!
I relocated the comment but forgot to proof read it!
s/calling enable()/considering the channel enabled/
I'm not sure where it comes from, but I keep thinking that there is an
enable() callback...
>
>> + */
>> + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) {
>> + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
>> + usleep_range(period, period * 2);
>
> So if period = 5000 *ns* you sleep between 5000 and 10000 *us* here?
/facepalm
>
>> + }
>> +}
>> +
>> +static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_device *pwm,
>> + const struct pwm_state *state, u8 prescale, u8 period_steps)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + u64 duty_steps, period, tmp;
>> + u16 prescale_val = PREG_TO_VAL(prescale);
>> + u8 period_steps_val = PREG_TO_VAL(period_steps);
>
> Can it happen that period_steps is 0xff? Then period_steps_val ends up
> being 0.
I guess that register could have a value it in from the bootloader etc and
therefore handling it is a good idea - but not in this function since it
is never used...
>
>> +
>> + period = period_steps_val * prescale_val * NSEC_PER_SEC;
>> + period = DIV64_U64_ROUND_UP(period, clk_get_rate(mchp_core_pwm->clk));
>
> The value you are calculating for period isn't used?!
huh, I am surprised that this was not caught by a W=1 C=1 build. Or maybe it
was and I just didn't notice - but I am 99% sure I made sure there were none.
>
>> +
>> + /*
>> + * Calculate the duty cycle in multiples of the prescaled period:
>> + * duty_steps = duty_in_ns / step_in_ns
>> + * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
>> + * The code below is rearranged slightly to only divide once.
>> + */
>> + duty_steps = state->duty_cycle * clk_get_rate(mchp_core_pwm->clk);
>> + tmp = prescale_val * NSEC_PER_SEC;
>> + return div64_u64(duty_steps, tmp);
>> +}
>> +
>> +static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
>> + const struct pwm_state *state, u64 duty_steps, u8 period_steps)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + u8 posedge, negedge;
>> + u8 period_steps_val = PREG_TO_VAL(period_steps);
>> +
>> + /*
>> + * Turn the output on unless posedge == negedge, in which case the
>> + * duty is intended to be 0, but limitations of the IP block don't
>> + * allow a zero length duty cycle - so just set the max high/low time
>> + * respectively.
>> + */
>
> I don't understand that comment. Maybe you mean?:
>
> /*
> * Setting posedge == negedge doesn't yield a constant output,
> * so that's an unsuitable setting to model duty_steps = 0.
> * In that case set the unwanted edge to a value that never
> * triggers.
> */
Yeah, this is a better comment. Thanks.
>
>> + if (state->polarity == PWM_POLARITY_INVERSED) {
>> + negedge = !duty_steps ? period_steps_val : 0u;
>> + posedge = duty_steps;
>> + } else {
>> + posedge = !duty_steps ? period_steps_val : 0u;
>> + negedge = duty_steps;
>> + }
>> +
>> + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
>> + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
>> +}
>> +
>> +static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct pwm_state *state,
>> + u8 *prescale, u8 *period_steps)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + u64 tmp, clk_rate;
>> +
>> + /*
>> + * Calculate the period cycles and prescale values.
>> + * The registers are each 8 bits wide & multiplied to compute the period
>> + * using the formula:
>> + * (clock_period) * (prescale + 1) * (period_steps + 1)
>> + * so the maximum period that can be generated is 0x10000 times the
>> + * period of the input clock.
>> + * However, due to the design of the "hardware", it is not possible to
>> + * attain a 100% duty cycle if the full range of period_steps is used.
>> + * Therefore period_steps is restricted to 0xFE and the maximum multiple
>> + * of the clock period attainable is 0xFF00.
>> + */
>> + clk_rate = clk_get_rate(mchp_core_pwm->clk);
>> +
>> + /*
>> + * If clk_rate is too big, the following multiplication might overflow.
>> + * However this is implausible, as the fabric of current FPGAs cannot
>> + * provide clocks at a rate high enough.
>> + */
>> + if (clk_rate >= NSEC_PER_SEC)
>> + return -EINVAL;
>> +
>> + tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
>> +
>> + if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
>> + *prescale = MCHPCOREPWM_PRESCALE_MAX - 1;
>
> why -1 here?
Because the hardware adds 1 to the register value. I had tried to explain
in the large comment above, but I will reword the comment for v8.
>
>> + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1;
>> + return 0;
>> + }
>> +
>> + *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX);
>> + /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */
>
> That should explain the cast to u32? If this were really necessary
> (hint: it isn't) it would IMHO be better to hide that cast in the macro.
>
>> + *period_steps = div_u64(tmp, PREG_TO_VAL((u32)*prescale)) - 1;
>> +
>> + return 0;
>> +}
>> +
>> +static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm,
>> + u8 prescale, u8 period_steps)
>> +{
>> + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
>> + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
>> +}
>> +
>> +static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> + const struct pwm_state *state)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + struct pwm_state current_state = pwm->state;
>> + bool period_locked;
>> + u64 duty_steps;
>> + u8 prescale, period_steps, hw_prescale, hw_period_steps;
>> + int ret;
>> +
>> + ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
>> + if (ret)
>> + return ret;
>
> I would have used mutex_lock() here. Why should a signal prevent
> reconfiguration of the PWM?
Cool, willdo.
>
>> +
>> + if (!state->enabled) {
>> + mchp_core_pwm_enable(chip, pwm, false, current_state.period);
>> + mutex_unlock(&mchp_core_pwm->lock);
>> + return 0;
>> + }
>> +
>> + /*
>> + * If the only thing that has changed is the duty cycle or the polarity,
>> + * we can shortcut the calculations and just compute/apply the new duty
>> + * cycle pos & neg edges
>> + * As all the channels share the same period, do not allow it to be
>> + * changed if any other channels are enabled.
>> + * If the period is locked, it may not be possible to use a period
>> + * less than that requested. In that case, we just abort.
>> + */
>> + period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
>> +
>> + if (period_locked) {
>> + mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
>> + hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
>> + hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
>> +
>> + if ((period_steps * prescale) < (hw_period_steps * hw_prescale)) {
>
> You need
>
> if ((period_steps + 1) * (prescale + 1) < (hw_period_steps + 1) * (hw_prescale + 1))
>
> here, don't you?
Yikes, yeah...
>
>> + mutex_unlock(&mchp_core_pwm->lock);
>> + return -EINVAL;
>> + }
>> +
>> + prescale = hw_prescale;
>> + period_steps = hw_period_steps;
>
> The two hw_* variables are only used in this branch. So their
> declaration can move into here.
>
>> + } else if (!current_state.enabled || current_state.period != state->period) {
>> + ret = mchp_core_pwm_calc_period(chip, state, &prescale, &period_steps);
>> + if (ret) {
>> + mutex_unlock(&mchp_core_pwm->lock);
>> + return ret;
>> + }
>> + mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
>> + } else {
>> + prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
>> + period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
>> + }
>> +
>> + duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps);
>> +
>> + /*
>> + * Because the period is per channel, it is possible that the requested
>> + * duty cycle is longer than the period, in which case cap it to the
>> + * period, IOW a 100% duty cycle.
>> + */
>> + if (duty_steps > period_steps)
>> + duty_steps = period_steps + 1;
>> +
>> + mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
>> +
>> + mchp_core_pwm_enable(chip, pwm, true, state->period);
>> +
>> + mutex_unlock(&mchp_core_pwm->lock);
>> +
>> + return 0;
>> +}
>> +
>> +static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
>> + struct pwm_state *state)
>> +{
>> + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
>> + u16 prescale;
>> + u8 period_steps, duty_steps, posedge, negedge;
>> + int ret;
>> +
>> + ret = mutex_lock_interruptible(&mchp_core_pwm->lock);
>> + if (ret)
>> + return;
>> +
>> + if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
>
> channel_enabled is initialized to 0 in .probe(), so a PWM is never
> diagnosed to be running when the core initially wants to determine the
> current state.
Good point. I'll initialise it in probe.
>
>> + state->enabled = true;
>> + else
>> + state->enabled = false;
>> +
>> + prescale = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE));
>> +
>> + period_steps = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD));
>> + state->period = period_steps * prescale * NSEC_PER_SEC;
>> + state->period = DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_core_pwm->clk));
>> +
>> + posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
>> + negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
>> +
>> + if (negedge == posedge) {
>> + state->duty_cycle = state->period / 2;
>
> I thought that's:
>
> state->duty_cycle = state->period;
> state->period *= 2;
Correct, as usual..
Thanks for your review Uwe! I'll fix it all up & submit v8 after -rc1.
Conor.
On 05/08/2022 20:58, Uwe Kleine-König wrote:
> Hello Conor,
>
> On Tue, Aug 02, 2022 at 12:34:14PM +0000, [email protected] wrote:
>> I'll fix it all up & submit v8 after -rc1.
>
> I discard the whole series in patchwork in the expectation that all
> patches will be part of your v8.
That was my plan, don't think there's a rush on the dt-binding fix.
Thanks Uwe,
Conor.
Hello Conor,
On Tue, Aug 02, 2022 at 12:34:14PM +0000, [email protected] wrote:
> I'll fix it all up & submit v8 after -rc1.
I discard the whole series in patchwork in the expectation that all
patches will be part of your v8.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |