From: Nick Hawkins <[email protected]>
Changes since v6:
*Removed spaces between tags on commit descriptions
Changes since v5:
*Fixed indentation in Kconfig file
Changes since v4:
*Removed unnecessary quotes in hpe,gxp-spifi.yaml
Changes since v3:
*Fixed indentations in hpe,gxp-spifi.yaml
Changes since v2:
*Changed the CONFIG_SPI_GXP from y to m in defconfig
*Removed extra space around < > for reg in hpe,gxp-spifi.yaml
*Changed interrupt-parrent to interrupt-parent in hpe,gxp-spifi.yaml
*Removed repeated include file in spi-gxp.c
*Removed unnecessary initialization of ret variable in spi-gxp.c
*Removed conditional variable checks where failure is not possible in
spi-gxp.c
*Removed unnecessary variable cs in spi-gxp.c
*Removed blank gxp-spifi-remove function in spi-gxp.c
*Fixed error messages so they are not repetitive
The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash and bios part.
Nick Hawkins (5):
spi: spi-gxp: Add support for HPE GXP SoCs
spi: dt-bindings: add documentation for hpe,gxp-spifi
ARM: dts: hpe: Add spi driver node
ARM: configs: multi_v7_defconfig: Enable HPE GXP SPI driver
MAINTAINERS: add spi support to GXP
.../bindings/spi/hpe,gxp-spifi.yaml | 56 +++
MAINTAINERS | 2 +
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 58 ++++
arch/arm/boot/dts/hpe-gxp.dtsi | 21 +-
arch/arm/configs/multi_v7_defconfig | 1 +
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-gxp.c | 325 ++++++++++++++++++
8 files changed, 470 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
create mode 100644 drivers/spi/spi-gxp.c
--
2.17.1
From: Nick Hawkins <[email protected]>
Enable the SPI driver on the HPE GXP BMC.
Signed-off-by: Nick Hawkins <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
v6:
*Remove blank line between tags on commit description
v5:
*No change, add Acked-by from Krzsztof from previous version
v4:
*No change
v3:
*No change
v2:
*Change CONFIG_SPI_GXP from y to m
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ce9826bce29b..ee8a730dabc9 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -443,6 +443,7 @@ CONFIG_SPI_CADENCE=y
CONFIG_SPI_DAVINCI=y
CONFIG_SPI_FSL_QUADSPI=m
CONFIG_SPI_GPIO=m
+CONFIG_SPI_GXP=m
CONFIG_SPI_FSL_DSPI=m
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_ORION=y
--
2.17.1
From: Nick Hawkins <[email protected]>
The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash and bios part.
Signed-off-by: Nick Hawkins <[email protected]>
---
v6:
*No change
v5:
*Add missing spaces in Kconfig to have proper alignment
v4:
*No change
v3:
*No change
v2:
*Removed repeated include file
*Removed unnecessary initialization of ret variable
*Removed conditional variable checks where failure is impossible
*Removed unecessary variable cs and instead used in the initialization
*Removed blank gxp_spifi_remove function
*Fixed error messages so they are not repetitive
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-gxp.c | 325 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 333 insertions(+)
create mode 100644 drivers/spi/spi-gxp.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3b1044ebc400..e3787cd9b475 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -371,6 +371,13 @@ config SPI_FSL_QUADSPI
This controller does not support generic SPI messages. It only
supports the high-level SPI memory interface.
+config SPI_GXP
+ tristate "GXP SPI driver"
+ depends on ARCH_HPE || COMPILE_TEST
+ help
+ This enables support for the driver for GXP bus attached SPI
+ controllers.
+
config SPI_HISI_KUNPENG
tristate "HiSilicon SPI Controller for Kunpeng SoCs"
depends on (ARM64 && ACPI) || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 0f44eb6083a5..ca5f204017ee 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += spi-fsl-qspi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
+obj-$(CONFIG_SPI_GXP) += spi-gxp.o
obj-$(CONFIG_SPI_HISI_KUNPENG) += spi-hisi-kunpeng.o
obj-$(CONFIG_SPI_HISI_SFC_V3XX) += spi-hisi-sfc-v3xx.o
obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-gxp.c b/drivers/spi/spi-gxp.c
new file mode 100644
index 000000000000..9ea355f7d64f
--- /dev/null
+++ b/drivers/spi/spi-gxp.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0=or-later
+/* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
+
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define GXP_SPI0_MAX_CHIPSELECT 2
+#define GXP_SPI_SLEEP_TIME 1
+#define GXP_SPI_TIMEOUT (130 * 1000000 / GXP_SPI_SLEEP_TIME)
+
+#define MANUAL_MODE 0
+#define DIRECT_MODE 1
+#define SPILDAT_LEN 256
+
+#define OFFSET_SPIMCFG 0x0
+#define OFFSET_SPIMCTRL 0x4
+#define OFFSET_SPICMD 0x5
+#define OFFSET_SPIDCNT 0x6
+#define OFFSET_SPIADDR 0x8
+#define OFFSET_SPIINTSTS 0xc
+
+#define SPIMCTRL_START 0x01
+#define SPIMCTRL_BUSY 0x02
+#define SPIMCTRL_DIR 0x08
+
+struct gxp_spi;
+
+struct gxp_spi_chip {
+ struct gxp_spi *spifi;
+ u32 cs;
+};
+
+struct gxp_spi_data {
+ u32 max_cs;
+ u32 mode_bits;
+};
+
+struct gxp_spi {
+ const struct gxp_spi_data *data;
+ void __iomem *reg_base;
+ void __iomem *dat_base;
+ void __iomem *dir_base;
+ struct device *dev;
+ struct gxp_spi_chip chips[GXP_SPI0_MAX_CHIPSELECT];
+};
+
+static void gxp_spi_set_mode(struct gxp_spi *spifi, int mode)
+{
+ u8 value;
+ void __iomem *reg_base = spifi->reg_base;
+
+ value = readb(reg_base + OFFSET_SPIMCTRL);
+
+ if (mode == MANUAL_MODE) {
+ writeb(0x55, reg_base + OFFSET_SPICMD);
+ writeb(0xaa, reg_base + OFFSET_SPICMD);
+ value &= ~0x30;
+ } else {
+ value |= 0x30;
+ }
+ writeb(value, reg_base + OFFSET_SPIMCTRL);
+}
+
+static int gxp_spi_read_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+ int ret;
+ struct gxp_spi *spifi = chip->spifi;
+ void __iomem *reg_base = spifi->reg_base;
+ u32 value;
+
+ value = readl(reg_base + OFFSET_SPIMCFG);
+ value &= ~(1 << 24);
+ value |= (chip->cs << 24);
+ value &= ~(0x07 << 16);
+ value &= ~(0x1f << 19);
+ writel(value, reg_base + OFFSET_SPIMCFG);
+
+ writel(0, reg_base + OFFSET_SPIADDR);
+
+ writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+ writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
+
+ value = readb(reg_base + OFFSET_SPIMCTRL);
+ value &= ~SPIMCTRL_DIR;
+ value |= SPIMCTRL_START;
+
+ writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+ ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+ !(value & SPIMCTRL_BUSY),
+ GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+ if (ret) {
+ dev_warn(spifi->dev, "read reg busy time out\n");
+ return ret;
+ }
+
+ memcpy_fromio(op->data.buf.in, spifi->dat_base, op->data.nbytes);
+ return ret;
+}
+
+static int gxp_spi_write_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+ int ret;
+ struct gxp_spi *spifi = chip->spifi;
+ void __iomem *reg_base = spifi->reg_base;
+ u32 value;
+
+ value = readl(reg_base + OFFSET_SPIMCFG);
+ value &= ~(1 << 24);
+ value |= (chip->cs << 24);
+ value &= ~(0x07 << 16);
+ value &= ~(0x1f << 19);
+ writel(value, reg_base + OFFSET_SPIMCFG);
+
+ writel(0, reg_base + OFFSET_SPIADDR);
+
+ writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+ memcpy_toio(spifi->dat_base, op->data.buf.in, op->data.nbytes);
+
+ writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
+
+ value = readb(reg_base + OFFSET_SPIMCTRL);
+ value |= SPIMCTRL_DIR;
+ value |= SPIMCTRL_START;
+
+ writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+ ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+ !(value & SPIMCTRL_BUSY),
+ GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+ if (ret)
+ dev_warn(spifi->dev, "write reg busy time out\n");
+
+ return ret;
+}
+
+static ssize_t gxp_spi_read(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+ struct gxp_spi *spifi = chip->spifi;
+ u32 offset = op->addr.val;
+
+ if (chip->cs == 0)
+ offset += 0x4000000;
+
+ memcpy_fromio(op->data.buf.in, spifi->dir_base + offset, op->data.nbytes);
+
+ return 0;
+}
+
+static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+ struct gxp_spi *spifi = chip->spifi;
+ void __iomem *reg_base = spifi->reg_base;
+ u32 write_len;
+ u32 value;
+ int ret;
+
+ write_len = op->data.nbytes;
+ if (write_len > SPILDAT_LEN)
+ write_len = SPILDAT_LEN;
+
+ value = readl(reg_base + OFFSET_SPIMCFG);
+ value &= ~(1 << 24);
+ value |= (chip->cs << 24);
+ value &= ~(0x07 << 16);
+ value |= (op->addr.nbytes << 16);
+ value &= ~(0x1f << 19);
+ writel(value, reg_base + OFFSET_SPIMCFG);
+
+ writel(op->addr.val, reg_base + OFFSET_SPIADDR);
+
+ writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+ writew(write_len, reg_base + OFFSET_SPIDCNT);
+
+ memcpy_toio(spifi->dat_base, op->data.buf.in, write_len);
+
+ value = readb(reg_base + OFFSET_SPIMCTRL);
+ value |= SPIMCTRL_DIR;
+ value |= SPIMCTRL_START;
+
+ writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+ ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+ !(value & SPIMCTRL_BUSY),
+ GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+ if (ret) {
+ dev_warn(spifi->dev, "write busy time out\n");
+ return ret;
+ }
+
+ return write_len;
+}
+
+static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master);
+ struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select];
+ int ret;
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (!op->addr.nbytes)
+ ret = gxp_spi_read_reg(chip, op);
+ else
+ ret = gxp_spi_read(chip, op);
+ } else {
+ if (!op->addr.nbytes)
+ ret = gxp_spi_write_reg(chip, op);
+ else
+ ret = gxp_spi_write(chip, op);
+ }
+
+ return ret;
+}
+
+static int gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ int ret;
+
+ ret = do_gxp_exec_mem_op(mem, op);
+ if (ret)
+ dev_err(&mem->spi->dev, "operation failed: %d", ret);
+
+ return ret;
+}
+
+static const struct spi_controller_mem_ops gxp_spi_mem_ops = {
+ .exec_op = gxp_exec_mem_op,
+};
+
+static int gxp_spi_setup(struct spi_device *spi)
+{
+ struct gxp_spi *spifi = spi_controller_get_devdata(spi->master);
+ unsigned int cs = spi->chip_select;
+ struct gxp_spi_chip *chip = &spifi->chips[cs];
+
+ chip->spifi = spifi;
+ chip->cs = cs;
+
+ gxp_spi_set_mode(spifi, MANUAL_MODE);
+
+ return 0;
+}
+
+static int gxp_spifi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct gxp_spi_data *data;
+ struct spi_controller *ctlr;
+ struct gxp_spi *spifi;
+ struct resource *res;
+ int ret;
+
+ data = of_device_get_match_data(&pdev->dev);
+
+ ctlr = devm_spi_alloc_master(dev, sizeof(*spifi));
+ if (!ctlr)
+ return -ENOMEM;
+
+ spifi = spi_controller_get_devdata(ctlr);
+
+ platform_set_drvdata(pdev, spifi);
+ spifi->data = data;
+ spifi->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ spifi->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(spifi->reg_base))
+ return PTR_ERR(spifi->reg_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ spifi->dat_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(spifi->dat_base))
+ return PTR_ERR(spifi->dat_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ spifi->dir_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(spifi->dir_base))
+ return PTR_ERR(spifi->dir_base);
+
+ ctlr->mode_bits = data->mode_bits;
+ ctlr->bus_num = pdev->id;
+ ctlr->mem_ops = &gxp_spi_mem_ops;
+ ctlr->setup = gxp_spi_setup;
+ ctlr->num_chipselect = data->max_cs;
+ ctlr->dev.of_node = dev->of_node;
+
+ ret = devm_spi_register_controller(dev, ctlr);
+ if (ret) {
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to register spi controller\n");
+ }
+
+ return 0;
+}
+
+static const struct gxp_spi_data gxp_spifi_data = {
+ .max_cs = 2,
+ .mode_bits = 0,
+};
+
+static const struct of_device_id gxp_spifi_match[] = {
+ {.compatible = "hpe,gxp-spifi", .data = &gxp_spifi_data },
+ { /* null */ }
+};
+MODULE_DEVICE_TABLE(of, gxp_spifi_match);
+
+static struct platform_driver gxp_spifi_driver = {
+ .probe = gxp_spifi_probe,
+ .driver = {
+ .name = "gxp-spifi",
+ .of_match_table = gxp_spifi_match,
+ },
+};
+module_platform_driver(gxp_spifi_driver);
+
+MODULE_DESCRIPTION("HPE GXP SPI Flash Interface driver");
+MODULE_AUTHOR("Nick Hawkins <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.17.1
On Thu, 28 Jul 2022 11:14:54 -0500, [email protected] wrote:
> From: Nick Hawkins <[email protected]>
>
> Changes since v6:
> *Removed spaces between tags on commit descriptions
>
> Changes since v5:
> *Fixed indentation in Kconfig file
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/5] spi: spi-gxp: Add support for HPE GXP SoCs
commit: 730bc8ba5e9ec103065142975015a793558f09a0
[2/5] spi: dt-bindings: add documentation for hpe,gxp-spifi
commit: 8cc35b86546dc35fb4f5ff7d1d163c5efc78bf0e
[5/5] MAINTAINERS: add spi support to GXP
commit: a1848b0fa2517a8d0bbc2783c90aefd4b7e7567a
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark