LinuxLists.cc - [PATCH v9 0/4] Microchip soft ip corePWM driver

2022-08-19 08:59:51

Subject: [PATCH v9 0/4] Microchip soft ip corePWM driver

Hey Uwe, all,

6.0-rc1 has rolled around so here is the promised ~v8~v9.
The pre 6.0-rc1 cover letter/series is here:
https://lore.kernel.org/linux-pwm/[email protected]
I'll take the dts change myself once the rest is merged.

There is one change here that is not directly from your feedback on v7,
Iadded a test for invalid PERIOD_STEPS values, in which case we abort if
the period is locked and cannot be fixed. Hopefully the rounding is not
ruined..

Thanks,
Conor.

Changes since v8:
- fixed a(nother) raw 64 bit division (& built it for riscv32!)
- added a check to make sure we don't try to sleep for 0 us

Changes since v7:
- rebased on 6.0-rc1
- reworded comments you highlighted in v7
- fixed the overkill sleeping
- removed the unused variables in calc_duty
- added some extra comments to explain behaviours you questioned in v7
- make the mutexes un-interruptible
- fixed added the 1s you suggested for the if(period_locked) logic
- added setup of the channel_enabled shadowing
- fixed the period reporting for the negedge == posedge case in
get_state() I had to add the enabled check, as otherwise it broke
setting the period for the first time out of reset.
- added a test for invalid PERIOD_STEPS values, in which case we abort
if we cannot fix the period

Changes from v6:
- Dropped an unused variable that I'd missed
- Actually check the return values of the mutex lock()s
- Re-rebased on -next for the MAINTAINERS patch (again...)

Changes from v5:
- switched to a mutex b/c we must sleep with the lock taken
- simplified the locking in apply() and added locking to get_state()
- reworked apply() as requested
- removed the loop in the period calculation (thanks Uwe!)
- add a copy of the enable registers in the driver to save on reads.
- remove the second (useless) write to sync_update
- added some missing rounding in get_state()
- couple other minor cleanups as requested in:
https://lore.kernel.org/linux-riscv/[email protected]/

Changes from v4:
- dropped some accidentally added files

Conor Dooley (4):
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: fix the icicle's #pwm-cells
pwm: add microchip soft ip corePWM driver
MAINTAINERS: add pwm to PolarFire SoC entry

.../bindings/pwm/microchip,corepwm.yaml | 4 +-
MAINTAINERS | 1 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 400 ++++++++++++++++++
6 files changed, 416 insertions(+), 2 deletions(-)
create mode 100644 drivers/pwm/pwm-microchip-core.c

base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
--
2.36.1

2022-08-19 08:59:56

by Conor Dooley

[permalink] [raw]

Subject: [PATCH v9 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells

corePWM is capable of inverted operation but the binding requires
\#pwm-cells of 2. Expand the binding to support setting the polarity.

Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding")
Acked-by: Rob Herring <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
index a7fae1772a81..cd8e9a8907f8 100644
--- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -30,7 +30,9 @@ properties:
maxItems: 1

"#pwm-cells":
- const: 2
+ enum: [2, 3]
+ description:
+ The only flag supported by the controller is PWM_POLARITY_INVERTED.

microchip,sync-update-mask:
description: |
--
2.36.1

2022-08-19 09:00:08

by Conor Dooley

[permalink] [raw]

Subject: [PATCH v9 4/4] MAINTAINERS: add pwm to PolarFire SoC entry

Add the newly introduced pwm driver to the existing PolarFire SoC entry.

Signed-off-by: Conor Dooley <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8a5012ba6ff9..5db66c743595 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17532,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c
F: drivers/clk/microchip/clk-mpfs.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/pcie-microchip-host.c
+F: drivers/pwm/pwm-microchip-core.c
F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: drivers/spi/spi-microchip-core.c
--
2.36.1

2022-08-19 09:00:15

by Conor Dooley

[permalink] [raw]

Subject: [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver

Add a driver that supports the Microchip FPGA "soft" PWM IP core.

Signed-off-by: Conor Dooley <[email protected]>
---
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 400 +++++++++++++++++++++++++++++++
3 files changed, 411 insertions(+)
create mode 100644 drivers/pwm/pwm-microchip-core.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 60d13a949bc5..e4de8c02c3c0 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -393,6 +393,16 @@ config PWM_MEDIATEK
To compile this driver as a module, choose M here: the module
will be called pwm-mediatek.

+config PWM_MICROCHIP_CORE
+ tristate "Microchip corePWM PWM support"
+ depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
+ depends on HAS_IOMEM && OF
+ help
+ PWM driver for Microchip FPGA soft IP core.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-microchip-core.
+
config PWM_MXS
tristate "Freescale MXS PWM support"
depends on ARCH_MXS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 7bf1a29f02b8..a65625359ece 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o
obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
+obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
diff --git a/drivers/pwm/pwm-microchip-core.c b/drivers/pwm/pwm-microchip-core.c
new file mode 100644
index 000000000000..a4c788dbfb28
--- /dev/null
+++ b/drivers/pwm/pwm-microchip-core.c
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * corePWM driver for Microchip "soft" FPGA IP cores.
+ *
+ * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
+ * Author: Conor Dooley <[email protected]>
+ * Documentation:
+ * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
+ *
+ * Limitations:
+ * - If the IP block is configured without "shadow registers", all register
+ * writes will take effect immediately, causing glitches on the output.
+ * If shadow registers *are* enabled, a write to the "SYNC_UPDATE" register
+ * notifies the core that it needs to update the registers defining the
+ * waveform from the contents of the "shadow registers".
+ * - The IP block has no concept of a duty cycle, only rising/falling edges of
+ * the waveform. Unfortunately, if the rising & falling edges registers have
+ * the same value written to them the IP block will do whichever of a rising
+ * or a falling edge is possible. I.E. a 50% waveform at twice the requested
+ * period. Therefore to get a 0% waveform, the output is set the max high/low
+ * time depending on polarity.
+ * - The PWM period is set for the whole IP block not per channel. The driver
+ * will only change the period if no other PWM output is enabled.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/math.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#define PREG_TO_VAL(PREG) ((PREG) + 1)
+
+#define MCHPCOREPWM_PRESCALE_MAX 0x100
+#define MCHPCOREPWM_PERIOD_STEPS_MAX 0xff
+#define MCHPCOREPWM_PERIOD_MAX 0xff00
+
+#define MCHPCOREPWM_PRESCALE 0x00
+#define MCHPCOREPWM_PERIOD 0x04
+#define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */
+#define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */
+#define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */
+#define MCHPCOREPWM_SYNC_UPD 0xe4
+
+struct mchp_core_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct mutex lock; /* protect the shared period */
+ void __iomem *base;
+ u32 sync_update_mask;
+ u16 channel_enabled;
+};
+
+static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip)
+{
+ return container_of(chip, struct mchp_core_pwm_chip, chip);
+}
+
+static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
+ bool enable, u64 period)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u8 channel_enable, reg_offset, shift;
+
+ /*
+ * There are two adjacent 8 bit control regs, the lower reg controls
+ * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
+ * and if so, offset by the bus width.
+ */
+ reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
+ shift = pwm->hwpwm & 7;
+
+ channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
+ channel_enable &= ~(1 << shift);
+ channel_enable |= (enable << shift);
+
+ writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
+ mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
+ mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
+
+ /*
+ * Notify the block to update the waveform from the shadow registers.
+ * The updated values will not appear on the bus until they have been
+ * applied to the waveform at the beginning of the next period. We must
+ * write these registers and wait for them to be applied before
+ * considering the channel enabled.
+ * If the delay is under 1 us, sleep for at least 1 us anyway.
+ */
+ if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) {
+ u64 delay;
+
+ delay = div_u64(period, 1000u) ? : 1u;
+ writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
+ usleep_range(delay, delay * 2);
+ }
+}
+
+static u64 mchp_core_pwm_calc_duty(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state, u8 prescale, u8 period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u64 duty_steps, tmp;
+ u16 prescale_val = PREG_TO_VAL(prescale);
+
+ /*
+ * Calculate the duty cycle in multiples of the prescaled period:
+ * duty_steps = duty_in_ns / step_in_ns
+ * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
+ * The code below is rearranged slightly to only divide once.
+ */
+ duty_steps = state->duty_cycle * clk_get_rate(mchp_core_pwm->clk);
+ tmp = prescale_val * NSEC_PER_SEC;
+ return div64_u64(duty_steps, tmp);
+}
+
+static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state, u64 duty_steps, u8 period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u8 posedge, negedge;
+ u8 period_steps_val = PREG_TO_VAL(period_steps);
+
+ /*
+ * Setting posedge == negedge doesn't yield a constant output,
+ * so that's an unsuitable setting to model duty_steps = 0.
+ * In that case set the unwanted edge to a value that never
+ * triggers.
+ */
+ if (state->polarity == PWM_POLARITY_INVERSED) {
+ negedge = !duty_steps ? period_steps_val : 0u;
+ posedge = duty_steps;
+ } else {
+ posedge = !duty_steps ? period_steps_val : 0u;
+ negedge = duty_steps;
+ }
+
+ writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
+ writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
+}
+
+static int mchp_core_pwm_calc_period(struct pwm_chip *chip, const struct pwm_state *state,
+ u8 *prescale, u8 *period_steps)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u64 tmp, clk_rate;
+
+ /*
+ * Calculate the period cycles and prescale values.
+ * The registers are each 8 bits wide & multiplied to compute the period
+ * using the formula:
+ * (clock_period) * (prescale + 1) * (period_steps + 1)
+ * so the maximum period that can be generated is 0x10000 times the
+ * period of the input clock.
+ * However, due to the design of the "hardware", it is not possible to
+ * attain a 100% duty cycle if the full range of period_steps is used.
+ * Therefore period_steps is restricted to 0xFE and the maximum multiple
+ * of the clock period attainable is 0xFF00.
+ */
+ clk_rate = clk_get_rate(mchp_core_pwm->clk);
+
+ /*
+ * If clk_rate is too big, the following multiplication might overflow.
+ * However this is implausible, as the fabric of current FPGAs cannot
+ * provide clocks at a rate high enough.
+ */
+ if (clk_rate >= NSEC_PER_SEC)
+ return -EINVAL;
+
+ tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
+
+ /*
+ * The hardware adds one to the register value, so decrement by one to
+ * account for the offset
+ */
+ if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
+ *prescale = MCHPCOREPWM_PRESCALE_MAX - 1;
+ *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX - 1;
+ return 0;
+ }
+
+ *prescale = div_u64(tmp, MCHPCOREPWM_PERIOD_STEPS_MAX);
+ /* PREG_TO_VAL() can produce a value larger than UINT8_MAX */
+ *period_steps = div_u64(tmp, PREG_TO_VAL(*prescale)) - 1;
+
+ return 0;
+}
+
+static inline void mchp_core_pwm_apply_period(struct mchp_core_pwm_chip *mchp_core_pwm,
+ u8 prescale, u8 period_steps)
+{
+ writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+}
+
+static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ struct pwm_state current_state = pwm->state;
+ bool period_locked;
+ u64 duty_steps;
+ u16 prescale;
+ u8 period_steps;
+ int ret;
+
+ mutex_lock(&mchp_core_pwm->lock);
+
+ if (!state->enabled) {
+ mchp_core_pwm_enable(chip, pwm, false, current_state.period);
+ mutex_unlock(&mchp_core_pwm->lock);
+ return 0;
+ }
+
+ /*
+ * If the only thing that has changed is the duty cycle or the polarity,
+ * we can shortcut the calculations and just compute/apply the new duty
+ * cycle pos & neg edges
+ * As all the channels share the same period, do not allow it to be
+ * changed if any other channels are enabled.
+ * If the period is locked, it may not be possible to use a period
+ * less than that requested. In that case, we just abort.
+ */
+ period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
+
+ if (period_locked) {
+ u16 hw_prescale;
+ u8 hw_period_steps;
+
+ mchp_core_pwm_calc_period(chip, state, (u8 *)&prescale, &period_steps);
+ hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+
+ if ((period_steps + 1) * (prescale + 1) <
+ (hw_period_steps + 1) * (hw_prescale + 1)) {
+ mutex_unlock(&mchp_core_pwm->lock);
+ return -EINVAL;
+ }
+
+ /*
+ * It is possible that something could have set the period_steps
+ * register to 0xff, which would prevent us from setting a 100%
+ * duty cycle, as explained in the mchp_core_pwm_calc_period()
+ * above.
+ * The period is locked and we cannot change this, so we abort.
+ */
+ if (period_steps == MCHPCOREPWM_PERIOD_STEPS_MAX)
+ return -EINVAL;
+
+ prescale = hw_prescale;
+ period_steps = hw_period_steps;
+ } else if (!current_state.enabled || current_state.period != state->period) {
+ ret = mchp_core_pwm_calc_period(chip, state, (u8 *)&prescale, &period_steps);
+ if (ret) {
+ mutex_unlock(&mchp_core_pwm->lock);
+ return ret;
+ }
+ mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
+ } else {
+ prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
+ period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
+
+ /*
+ * As above, it is possible that something could have set the
+ * period_steps register to 0xff, which would prevent us from
+ * setting a 100% duty cycle, as explained above.
+ * As the period is not locked, we are free to fix this.
+ */
+ if (period_steps == MCHPCOREPWM_PERIOD_STEPS_MAX) {
+ period_steps -= 1;
+ mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
+ }
+ }
+
+ duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps);
+
+ /*
+ * Because the period is per channel, it is possible that the requested
+ * duty cycle is longer than the period, in which case cap it to the
+ * period, IOW a 100% duty cycle.
+ */
+ if (duty_steps > period_steps)
+ duty_steps = period_steps + 1;
+
+ mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
+
+ mchp_core_pwm_enable(chip, pwm, true, state->period);
+
+ mutex_unlock(&mchp_core_pwm->lock);
+
+ return 0;
+}
+
+static void mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
+ u16 prescale;
+ u8 period_steps, duty_steps, posedge, negedge;
+
+ mutex_lock(&mchp_core_pwm->lock);
+
+ if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
+ state->enabled = true;
+ else
+ state->enabled = false;
+
+ prescale = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE));
+
+ period_steps = PREG_TO_VAL(readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD));
+ state->period = period_steps * prescale * NSEC_PER_SEC;
+ state->period = DIV64_U64_ROUND_UP(state->period, clk_get_rate(mchp_core_pwm->clk));
+
+ posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
+ negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
+
+ if ((negedge == posedge) && state->enabled) {
+ state->duty_cycle = state->period;
+ state->period *= 2;
+ } else {
+ duty_steps = abs((s16)posedge - (s16)negedge);
+ state->duty_cycle = duty_steps * prescale * NSEC_PER_SEC;
+ state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle,
+ clk_get_rate(mchp_core_pwm->clk));
+ }
+
+ state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+
+ mutex_unlock(&mchp_core_pwm->lock);
+}
+
+static const struct pwm_ops mchp_core_pwm_ops = {
+ .apply = mchp_core_pwm_apply,
+ .get_state = mchp_core_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id mchp_core_of_match[] = {
+ {
+ .compatible = "microchip,corepwm-rtl-v4",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mchp_core_of_match);
+
+static int mchp_core_pwm_probe(struct platform_device *pdev)
+{
+ struct mchp_core_pwm_chip *mchp_pwm;
+ struct resource *regs;
+ int ret;
+
+ mchp_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_pwm), GFP_KERNEL);
+ if (!mchp_pwm)
+ return -ENOMEM;
+
+ mchp_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
+ if (IS_ERR(mchp_pwm->base))
+ return PTR_ERR(mchp_pwm->base);
+
+ mchp_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(mchp_pwm->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(mchp_pwm->clk),
+ "failed to get PWM clock\n");
+
+ if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
+ &mchp_pwm->sync_update_mask))
+ mchp_pwm->sync_update_mask = 0u;
+
+ mutex_init(&mchp_pwm->lock);
+
+ mchp_pwm->chip.dev = &pdev->dev;
+ mchp_pwm->chip.ops = &mchp_core_pwm_ops;
+ mchp_pwm->chip.npwm = 16;
+
+ mchp_pwm->channel_enabled = readb_relaxed(mchp_pwm->base + MCHPCOREPWM_EN(0));
+ mchp_pwm->channel_enabled |= readb_relaxed(mchp_pwm->base + MCHPCOREPWM_EN(1)) << 8;
+
+ ret = devm_pwmchip_add(&pdev->dev, &mchp_pwm->chip);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
+
+ return 0;
+}
+
+static struct platform_driver mchp_core_pwm_driver = {
+ .driver = {
+ .name = "mchp-core-pwm",
+ .of_match_table = mchp_core_of_match,
+ },
+ .probe = mchp_core_pwm_probe,
+};
+module_platform_driver(mchp_core_pwm_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Conor Dooley <[email protected]>");
+MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");
--
2.36.1

2022-08-19 09:31:31

by Conor Dooley

[permalink] [raw]

Subject: [PATCH v9 2/4] riscv: dts: fix the icicle's #pwm-cells

\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support inverted operation, so update the entry to correctly report its
capabilities.

Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
Reviewed-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 0d28858b83f2..e09a13aef268 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
clocks = <&fabric_clk3>;
status = "disabled";
};
--
2.36.1

2022-08-22 09:26:51

by Dan Carpenter

[permalink] [raw]

Subject: Re: [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver

Hi Conor,

url: https://github.com/intel-lab-lkp/linux/commits/Conor-Dooley/Microchip-soft-ip-corePWM-driver/20220819-170106
base: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
config: arm64-randconfig-m031-20220821 (https://download.01.org/0day-ci/archive/20220821/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
Reported-by: Dan Carpenter <[email protected]>

smatch warnings:
drivers/pwm/pwm-microchip-core.c:295 mchp_core_pwm_apply() warn: inconsistent returns '&mchp_core_pwm->lock'.

vim +295 drivers/pwm/pwm-microchip-core.c

ae39414af22131 Conor Dooley 2022-08-19 200 static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ae39414af22131 Conor Dooley 2022-08-19 201 const struct pwm_state *state)
ae39414af22131 Conor Dooley 2022-08-19 202 {
ae39414af22131 Conor Dooley 2022-08-19 203 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
ae39414af22131 Conor Dooley 2022-08-19 204 struct pwm_state current_state = pwm->state;
ae39414af22131 Conor Dooley 2022-08-19 205 bool period_locked;
ae39414af22131 Conor Dooley 2022-08-19 206 u64 duty_steps;
ae39414af22131 Conor Dooley 2022-08-19 207 u16 prescale;
ae39414af22131 Conor Dooley 2022-08-19 208 u8 period_steps;
ae39414af22131 Conor Dooley 2022-08-19 209 int ret;
ae39414af22131 Conor Dooley 2022-08-19 210
ae39414af22131 Conor Dooley 2022-08-19 211 mutex_lock(&mchp_core_pwm->lock);
ae39414af22131 Conor Dooley 2022-08-19 212
ae39414af22131 Conor Dooley 2022-08-19 213 if (!state->enabled) {
ae39414af22131 Conor Dooley 2022-08-19 214 mchp_core_pwm_enable(chip, pwm, false, current_state.period);
ae39414af22131 Conor Dooley 2022-08-19 215 mutex_unlock(&mchp_core_pwm->lock);
ae39414af22131 Conor Dooley 2022-08-19 216 return 0;
ae39414af22131 Conor Dooley 2022-08-19 217 }
ae39414af22131 Conor Dooley 2022-08-19 218
ae39414af22131 Conor Dooley 2022-08-19 219 /*
ae39414af22131 Conor Dooley 2022-08-19 220 * If the only thing that has changed is the duty cycle or the polarity,
ae39414af22131 Conor Dooley 2022-08-19 221 * we can shortcut the calculations and just compute/apply the new duty
ae39414af22131 Conor Dooley 2022-08-19 222 * cycle pos & neg edges
ae39414af22131 Conor Dooley 2022-08-19 223 * As all the channels share the same period, do not allow it to be
ae39414af22131 Conor Dooley 2022-08-19 224 * changed if any other channels are enabled.
ae39414af22131 Conor Dooley 2022-08-19 225 * If the period is locked, it may not be possible to use a period
ae39414af22131 Conor Dooley 2022-08-19 226 * less than that requested. In that case, we just abort.
ae39414af22131 Conor Dooley 2022-08-19 227 */
ae39414af22131 Conor Dooley 2022-08-19 228 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
ae39414af22131 Conor Dooley 2022-08-19 229
ae39414af22131 Conor Dooley 2022-08-19 230 if (period_locked) {
ae39414af22131 Conor Dooley 2022-08-19 231 u16 hw_prescale;
ae39414af22131 Conor Dooley 2022-08-19 232 u8 hw_period_steps;
ae39414af22131 Conor Dooley 2022-08-19 233
ae39414af22131 Conor Dooley 2022-08-19 234 mchp_core_pwm_calc_period(chip, state, (u8 *)&prescale, &period_steps);
ae39414af22131 Conor Dooley 2022-08-19 235 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
ae39414af22131 Conor Dooley 2022-08-19 236 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
ae39414af22131 Conor Dooley 2022-08-19 237
ae39414af22131 Conor Dooley 2022-08-19 238 if ((period_steps + 1) * (prescale + 1) <
ae39414af22131 Conor Dooley 2022-08-19 239 (hw_period_steps + 1) * (hw_prescale + 1)) {
ae39414af22131 Conor Dooley 2022-08-19 240 mutex_unlock(&mchp_core_pwm->lock);
ae39414af22131 Conor Dooley 2022-08-19 241 return -EINVAL;
ae39414af22131 Conor Dooley 2022-08-19 242 }
ae39414af22131 Conor Dooley 2022-08-19 243
ae39414af22131 Conor Dooley 2022-08-19 244 /*
ae39414af22131 Conor Dooley 2022-08-19 245 * It is possible that something could have set the period_steps
ae39414af22131 Conor Dooley 2022-08-19 246 * register to 0xff, which would prevent us from setting a 100%
ae39414af22131 Conor Dooley 2022-08-19 247 * duty cycle, as explained in the mchp_core_pwm_calc_period()
ae39414af22131 Conor Dooley 2022-08-19 248 * above.
ae39414af22131 Conor Dooley 2022-08-19 249 * The period is locked and we cannot change this, so we abort.
ae39414af22131 Conor Dooley 2022-08-19 250 */
ae39414af22131 Conor Dooley 2022-08-19 251 if (period_steps == MCHPCOREPWM_PERIOD_STEPS_MAX)
ae39414af22131 Conor Dooley 2022-08-19 252 return -EINVAL;

mutex_unlock(&mchp_core_pwm->lock); before the retun?

ae39414af22131 Conor Dooley 2022-08-19 253
ae39414af22131 Conor Dooley 2022-08-19 254 prescale = hw_prescale;
ae39414af22131 Conor Dooley 2022-08-19 255 period_steps = hw_period_steps;
ae39414af22131 Conor Dooley 2022-08-19 256 } else if (!current_state.enabled || current_state.period != state->period) {
ae39414af22131 Conor Dooley 2022-08-19 257 ret = mchp_core_pwm_calc_period(chip, state, (u8 *)&prescale, &period_steps);
ae39414af22131 Conor Dooley 2022-08-19 258 if (ret) {
ae39414af22131 Conor Dooley 2022-08-19 259 mutex_unlock(&mchp_core_pwm->lock);
ae39414af22131 Conor Dooley 2022-08-19 260 return ret;
ae39414af22131 Conor Dooley 2022-08-19 261 }
ae39414af22131 Conor Dooley 2022-08-19 262 mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
ae39414af22131 Conor Dooley 2022-08-19 263 } else {
ae39414af22131 Conor Dooley 2022-08-19 264 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
ae39414af22131 Conor Dooley 2022-08-19 265 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
ae39414af22131 Conor Dooley 2022-08-19 266
ae39414af22131 Conor Dooley 2022-08-19 267 /*
ae39414af22131 Conor Dooley 2022-08-19 268 * As above, it is possible that something could have set the
ae39414af22131 Conor Dooley 2022-08-19 269 * period_steps register to 0xff, which would prevent us from
ae39414af22131 Conor Dooley 2022-08-19 270 * setting a 100% duty cycle, as explained above.
ae39414af22131 Conor Dooley 2022-08-19 271 * As the period is not locked, we are free to fix this.
ae39414af22131 Conor Dooley 2022-08-19 272 */
ae39414af22131 Conor Dooley 2022-08-19 273 if (period_steps == MCHPCOREPWM_PERIOD_STEPS_MAX) {
ae39414af22131 Conor Dooley 2022-08-19 274 period_steps -= 1;
ae39414af22131 Conor Dooley 2022-08-19 275 mchp_core_pwm_apply_period(mchp_core_pwm, prescale, period_steps);
ae39414af22131 Conor Dooley 2022-08-19 276 }
ae39414af22131 Conor Dooley 2022-08-19 277 }
ae39414af22131 Conor Dooley 2022-08-19 278
ae39414af22131 Conor Dooley 2022-08-19 279 duty_steps = mchp_core_pwm_calc_duty(chip, pwm, state, prescale, period_steps);
ae39414af22131 Conor Dooley 2022-08-19 280
ae39414af22131 Conor Dooley 2022-08-19 281 /*
ae39414af22131 Conor Dooley 2022-08-19 282 * Because the period is per channel, it is possible that the requested
ae39414af22131 Conor Dooley 2022-08-19 283 * duty cycle is longer than the period, in which case cap it to the
ae39414af22131 Conor Dooley 2022-08-19 284 * period, IOW a 100% duty cycle.
ae39414af22131 Conor Dooley 2022-08-19 285 */
ae39414af22131 Conor Dooley 2022-08-19 286 if (duty_steps > period_steps)
ae39414af22131 Conor Dooley 2022-08-19 287 duty_steps = period_steps + 1;
ae39414af22131 Conor Dooley 2022-08-19 288
ae39414af22131 Conor Dooley 2022-08-19 289 mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
ae39414af22131 Conor Dooley 2022-08-19 290
ae39414af22131 Conor Dooley 2022-08-19 291 mchp_core_pwm_enable(chip, pwm, true, state->period);
ae39414af22131 Conor Dooley 2022-08-19 292
ae39414af22131 Conor Dooley 2022-08-19 293 mutex_unlock(&mchp_core_pwm->lock);
ae39414af22131 Conor Dooley 2022-08-19 294
ae39414af22131 Conor Dooley 2022-08-19 @295 return 0;
ae39414af22131 Conor Dooley 2022-08-19 296 }

--
0-DAY CI Kernel Test Service
https://01.org/lkp

2022-08-22 10:01:14

by Conor Dooley

[permalink] [raw]

Subject: Re: [PATCH v9 3/4] pwm: add microchip soft ip corePWM driver