Hou Zhiqiang (2):
arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
arm64: dts: ls1043a: Add big-endian property for PCIe nodes
Laurentiu Tudor (2):
arm64: dts: ls1043a: add missing dma ranges property
arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma
size
Li Yang (7):
arm64: dts: ls1043a: fix the wrong size of dcfg space
arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
arm64: dts: ls1043a: use pcie aer/pme interrupts
arm64: dts: ls1043a: make dma-coherent global to the SoC
arm64: dts: ls1043a: add gpio based i2c recovery information
arm64: dts: ls1043a-qds: add mmio based mdio-mux support
arm64: dts: ls1043a-rdb: add pcf85263 rtc node
.../boot/dts/freescale/fsl-ls1043a-qds.dts | 173 +++++++++++++++++-
.../boot/dts/freescale/fsl-ls1043a-rdb.dts | 10 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 131 +++++++------
3 files changed, 256 insertions(+), 58 deletions(-)
--
2.37.1
The size of the block should be 0x1000 instead of 0x10000.
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ca3d5a90d6d4..e6fce671799d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -393,7 +393,7 @@ sfp: efuse@1e80000 {
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1043a-dcfg", "syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
--
2.37.1
Enable USB3 HW LPM feature for ls1043a.
Signed-off-by: Ran Wang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e6fce671799d..3ba66b18de35 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -817,6 +817,7 @@ usb0: usb@2f00000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
@@ -828,6 +829,7 @@ usb1: usb@3000000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
@@ -839,6 +841,7 @@ usb2: usb@3100000 {
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
--
2.37.1
ls1043a is really completely dma coherent in their entirety so add the
dma-coherent property at the soc level in the device tree and drop the
instances where it's specifically added to a few select devices.
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index adaf337c438c..b37244acf16a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -301,6 +301,7 @@ soc: soc {
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
@@ -890,7 +891,6 @@ pcie1: pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -918,7 +918,6 @@ pcie2: pcie@3500000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -946,7 +945,6 @@ pcie3: pcie@3600000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
--
2.37.1
After the binding has been updated to include more specific interrupt
definition, update the dts to use the more specific interrupt names.
Signed-off-by: Po Liu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 3ba66b18de35..242fe8bfab17 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -883,9 +883,9 @@ pcie1: pcie@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 118 0x4>, /* controller interrupt */
- <0 117 0x4>; /* PME interrupt */
- interrupt-names = "intr", "pme";
+ interrupts = <0 117 0x4>,
+ <0 118 0x4>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -909,9 +909,9 @@ pcie2: pcie@3500000 {
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 128 0x4>,
- <0 127 0x4>;
- interrupt-names = "intr", "pme";
+ interrupts = <0 127 0x4>,
+ <0 128 0x4>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -935,9 +935,9 @@ pcie3: pcie@3600000 {
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 162 0x4>,
- <0 161 0x4>;
- interrupt-names = "intr", "pme";
+ interrupts = <0 161 0x4>,
+ <0 162 0x4>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
--
2.37.1
From: Hou Zhiqiang <[email protected]>
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller node.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 242fe8bfab17..6b2bfb5c6f32 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -901,6 +901,7 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic 0 111 0x4>,
<0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>;
+ fsl,pcie-scfg = <&scfg 0>;
status = "disabled";
};
@@ -927,6 +928,7 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic 0 121 0x4>,
<0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>;
+ fsl,pcie-scfg = <&scfg 1>;
status = "disabled";
};
@@ -953,6 +955,7 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic 0 155 0x4>,
<0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>;
+ fsl,pcie-scfg = <&scfg 2>;
status = "disabled";
};
--
2.37.1
Add scl-gpios property for i2c recovery and add SoC specific compatible
string for SoC specific fixup.
Signed-off-by: Zhang Ying <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index b37244acf16a..20888aceb5f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -538,7 +538,7 @@ dspi1: spi@2110000 {
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -553,7 +553,7 @@ i2c0: i2c@2180000 {
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
@@ -561,11 +561,12 @@ i2c1: i2c@2190000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ scl-gpios = <&gpio4 2 0>;
status = "disabled";
};
i2c2: i2c@21a0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
@@ -573,11 +574,12 @@ i2c2: i2c@21a0000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ scl-gpios = <&gpio4 10 0>;
status = "disabled";
};
i2c3: i2c@21b0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
@@ -585,6 +587,7 @@ i2c3: i2c@21b0000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ scl-gpios = <&gpio4 12 0>;
status = "disabled";
};
--
2.37.1
From: Laurentiu Tudor <[email protected]>
Wrap the usb and sata controllers in an intermediate simple-bus and use
it to constrain the dma address size of these usb controllers to the 40
bits that they generate toward the interconnect. This is required
because the SoC uses 48 bits address sizes and this mismatch would lead
to smmu context faults because the usb generates 40-bit addresses while
the smmu page tables are populated with 48-bit wide addresses.
Suggested-by: Robin Murphy <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 92 ++++++++++---------
1 file changed, 50 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 20888aceb5f4..1942ab84ab1c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -815,51 +815,59 @@ QORIQ_CLK_PLL_DIV(1)>,
QORIQ_CLK_PLL_DIV(1)>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <0 60 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- status = "disabled";
- };
+ aux_bus: aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
+
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
+ };
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <0 61 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- status = "disabled";
- };
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
+ };
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <0 63 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- status = "disabled";
- };
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
+ };
- sata: sata@3200000 {
- compatible = "fsl,ls1043a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <0 69 0x4>;
- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
- QORIQ_CLK_PLL_DIV(1)>;
- dma-coherent;
+ sata: sata@3200000 {
+ compatible = "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <0 69 0x4>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
+ dma-coherent;
+ };
};
msi1: msi-controller1@1571000 {
--
2.37.1
From: Laurentiu Tudor <[email protected]>
ls1043a has a 48-bit address size so make sure that the dma-ranges
reflects this. Otherwise the linux kernel's dma sub-system will set the
default dma masks to full 64-bit, badly breaking dmas.
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 3ebc608875b5..adaf337c438c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -300,6 +300,7 @@ soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
--
2.37.1
From: Hou Zhiqiang <[email protected]>
Add the big-endian property for LS1043A PCIe nodes for accessing PEX_LUT
and PF register block.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 6b2bfb5c6f32..3ebc608875b5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -902,6 +902,7 @@ pcie1: pcie@3400000 {
<0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>;
fsl,pcie-scfg = <&scfg 0>;
+ big-endian;
status = "disabled";
};
@@ -929,6 +930,7 @@ pcie2: pcie@3500000 {
<0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>;
fsl,pcie-scfg = <&scfg 1>;
+ big-endian;
status = "disabled";
};
@@ -956,6 +958,7 @@ pcie3: pcie@3600000 {
<0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>;
fsl,pcie-scfg = <&scfg 2>;
+ big-endian;
status = "disabled";
};
--
2.37.1
On Wed, Aug 24, 2022 at 05:36:54PM -0500, Li Yang wrote:
> After the binding has been updated to include more specific interrupt
> definition, update the dts to use the more specific interrupt names.
>
> Signed-off-by: Po Liu <[email protected]>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index 3ba66b18de35..242fe8bfab17 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -883,9 +883,9 @@ pcie1: pcie@3400000 {
> reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 118 0x4>, /* controller interrupt */
> - <0 117 0x4>; /* PME interrupt */
> - interrupt-names = "intr", "pme";
> + interrupts = <0 117 0x4>,
> + <0 118 0x4>;
While at it, could you use IRQ_TYPE_LEVEL_HIGH for the polarity cell?
Shawn
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> @@ -909,9 +909,9 @@ pcie2: pcie@3500000 {
> reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
> <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 128 0x4>,
> - <0 127 0x4>;
> - interrupt-names = "intr", "pme";
> + interrupts = <0 127 0x4>,
> + <0 128 0x4>;
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> @@ -935,9 +935,9 @@ pcie3: pcie@3600000 {
> reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
> <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <0 162 0x4>,
> - <0 161 0x4>;
> - interrupt-names = "intr", "pme";
> + interrupts = <0 161 0x4>,
> + <0 162 0x4>;
> + interrupt-names = "pme", "aer";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> --
> 2.37.1
>
On Wed, Aug 24, 2022 at 05:36:59PM -0500, Li Yang wrote:
> Add scl-gpios property for i2c recovery and add SoC specific compatible
> string for SoC specific fixup.
>
> Signed-off-by: Zhang Ying <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index b37244acf16a..20888aceb5f4 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -538,7 +538,7 @@ dspi1: spi@2110000 {
> };
>
> i2c0: i2c@2180000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2180000 0x0 0x10000>;
> @@ -553,7 +553,7 @@ i2c0: i2c@2180000 {
> };
>
> i2c1: i2c@2190000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x2190000 0x0 0x10000>;
> @@ -561,11 +561,12 @@ i2c1: i2c@2190000 {
> clock-names = "i2c";
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(1)>;
> + scl-gpios = <&gpio4 2 0>;
Could you use the polarity define from include/dt-bindings/gpio/gpio.h?
Shawn
> status = "disabled";
> };
>
> i2c2: i2c@21a0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21a0000 0x0 0x10000>;
> @@ -573,11 +574,12 @@ i2c2: i2c@21a0000 {
> clock-names = "i2c";
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(1)>;
> + scl-gpios = <&gpio4 10 0>;
> status = "disabled";
> };
>
> i2c3: i2c@21b0000 {
> - compatible = "fsl,vf610-i2c";
> + compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x21b0000 0x0 0x10000>;
> @@ -585,6 +587,7 @@ i2c3: i2c@21b0000 {
> clock-names = "i2c";
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(1)>;
> + scl-gpios = <&gpio4 12 0>;
> status = "disabled";
> };
>
> --
> 2.37.1
>
On Wed, Aug 24, 2022 at 05:37:00PM -0500, Li Yang wrote:
> From: Laurentiu Tudor <[email protected]>
>
> Wrap the usb and sata controllers in an intermediate simple-bus and use
> it to constrain the dma address size of these usb controllers to the 40
> bits that they generate toward the interconnect. This is required
> because the SoC uses 48 bits address sizes and this mismatch would lead
> to smmu context faults because the usb generates 40-bit addresses while
> the smmu page tables are populated with 48-bit wide addresses.
>
> Suggested-by: Robin Murphy <[email protected]>
> Signed-off-by: Laurentiu Tudor <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 92 ++++++++++---------
> 1 file changed, 50 insertions(+), 42 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index 20888aceb5f4..1942ab84ab1c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -815,51 +815,59 @@ QORIQ_CLK_PLL_DIV(1)>,
> QORIQ_CLK_PLL_DIV(1)>;
> };
>
> - usb0: usb@2f00000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x2f00000 0x0 0x10000>;
> - interrupts = <0 60 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + aux_bus: aux_bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
> +
> + usb0: usb@2f00000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x2f00000 0x0 0x10000>;
> + interrupts = <0 60 0x4>;
While at it, use define for polarity cell?
Shawn
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - usb1: usb@3000000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x3000000 0x0 0x10000>;
> - interrupts = <0 61 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + usb1: usb@3000000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3000000 0x0 0x10000>;
> + interrupts = <0 61 0x4>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - usb2: usb@3100000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x3100000 0x0 0x10000>;
> - interrupts = <0 63 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + usb2: usb@3100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <0 63 0x4>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - sata: sata@3200000 {
> - compatible = "fsl,ls1043a-ahci";
> - reg = <0x0 0x3200000 0x0 0x10000>,
> - <0x0 0x20140520 0x0 0x4>;
> - reg-names = "ahci", "sata-ecc";
> - interrupts = <0 69 0x4>;
> - clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> - QORIQ_CLK_PLL_DIV(1)>;
> - dma-coherent;
> + sata: sata@3200000 {
> + compatible = "fsl,ls1043a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>,
> + <0x0 0x20140520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <0 69 0x4>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(1)>;
> + dma-coherent;
> + };
> };
>
> msi1: msi-controller1@1571000 {
> --
> 2.37.1
>