From: Quanyang Wang <[email protected]>
The function zynqmp_pll_round_rate is used to find a most appropriate
PLL frequency which the hardware can generate according to the desired
frequency. For example, if the desired frequency is 297MHz, considering
the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
There are two problems with the current code of zynqmp_pll_round_rate:
1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate
when the parameter "rate" is an integer multiple of *prate, in other words,
if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which
is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz
and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and
just return 660MHz, and this will cause clk_calc_new_rates failure since
zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk
that zynqmp_pll_round_rate returns an invalid rate because the function
DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz,
this function will return 1499999985Hz by using the formula below:
value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
because DIV_ROUND_CLOSEST makes some loss in the fractional part.
Signed-off-by: Quanyang Wang <[email protected]>
---
drivers/clk/zynqmp/pll.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 91a6b4cc910e..0d3e1377b092 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -102,26 +102,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
u32 fbdiv;
- long rate_div, f;
+ u32 mult, div;
- /* Enable the fractional mode if needed */
- rate_div = (rate * FRAC_DIV) / *prate;
- f = rate_div % FRAC_DIV;
- if (f) {
- if (rate > PS_PLL_VCO_MAX) {
- fbdiv = rate / PS_PLL_VCO_MAX;
- rate = rate / (fbdiv + 1);
- }
- if (rate < PS_PLL_VCO_MIN) {
- fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
- rate = rate * fbdiv;
- }
- return rate;
+ /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
+ if (rate > PS_PLL_VCO_MAX) {
+ div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
+ rate = rate / div;
+ }
+ if (rate < PS_PLL_VCO_MIN) {
+ mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
+ rate = rate * mult;
}
fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
- fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
- return *prate * fbdiv;
+ if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
+ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
+ rate = *prate * fbdiv;
+ }
+
+ return rate;
}
/**
--
2.36.1
[AMD Official Use Only - General]
Hi ,
Thanks for the patch.
> -----Original Message-----
> From: [email protected] <[email protected]>
> Sent: Friday, August 26, 2022 7:51 PM
> To: Michael Turquette <[email protected]>; Stephen Boyd
> <[email protected]>; Michal Simek <[email protected]>
> Cc: Michael Tretter <[email protected]>; Quanyang Wang
> <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected]
> Subject: [PATCH] clk: zynqmp: pll: rectify rate rounding in
> zynqmp_pll_round_rate
>
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
>
>
> From: Quanyang Wang <[email protected]>
>
> The function zynqmp_pll_round_rate is used to find a most appropriate PLL
> frequency which the hardware can generate according to the desired
> frequency. For example, if the desired frequency is 297MHz, considering the
> limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
> of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
>
> There are two problems with the current code of zynqmp_pll_round_rate:
>
> 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate when
> the parameter "rate" is an integer multiple of *prate, in other words, if "f" is
> zero, zynqmp_pll_round_rate won't return a valid frequency which is from
> PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz and
> the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and just
> return 660MHz, and this will cause clk_calc_new_rates failure since
> zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
>
> 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk that
> zynqmp_pll_round_rate returns an invalid rate because the function
> DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
> clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, this
> function will return 1499999985Hz by using the formula below:
> value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
> This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
> because DIV_ROUND_CLOSEST makes some loss in the fractional part.
>
> Signed-off-by: Quanyang Wang <[email protected]>
Reviewed-by: Shubhrajyoti Datta <[email protected]>
Quoting [email protected] (2022-08-26 07:20:30)
> From: Quanyang Wang <[email protected]>
>
> The function zynqmp_pll_round_rate is used to find a most appropriate
> PLL frequency which the hardware can generate according to the desired
> frequency. For example, if the desired frequency is 297MHz, considering
> the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
> of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
>
> There are two problems with the current code of zynqmp_pll_round_rate:
>
> 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate
> when the parameter "rate" is an integer multiple of *prate, in other words,
> if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which
> is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz
> and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and
> just return 660MHz, and this will cause clk_calc_new_rates failure since
> zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
>
> 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk
> that zynqmp_pll_round_rate returns an invalid rate because the function
> DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
> clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz,
> this function will return 1499999985Hz by using the formula below:
> value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
> This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
> because DIV_ROUND_CLOSEST makes some loss in the fractional part.
>
> Signed-off-by: Quanyang Wang <[email protected]>
> ---
Applied to clk-next