Hey All,
On top of my other series adding the m100pfsevp and sevkit [0], here's
yet another development kit.. This time from Aldec.
The board has 32 GB of DDR but the DT I have access to only has a small
bit of that mapped.. until I know exactly what the mapping is, I will
not be applying this.
Thanks,
Conor.
0 - https://lore.kernel.org/all/[email protected]/
Conor Dooley (3):
dt-bindings: vendor-prefixes: Add entry for Aldec
dt-bindings: riscv: microchip: document the Aldec TySoM
riscv: dts: microchip: add a devicetree for the Aldec TySoM
.../devicetree/bindings/riscv/microchip.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++
.../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 168 ++++++++++++++++++
5 files changed, 219 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
--
2.36.1
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
a Microchip PolarFire SoC MPFS250T-FCG1152. Features include:
- 16 GB FPGA DDR4
- 16 GB MSS DDR4 with ECC
- eMMC
- SPI flash memory
- 2x Ethernet 10/100/1000
- USB 2.0
- PCIe x4 Gen2
- HDMI OUT
- 2x FMC connector (HPC and LPC)
Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++
.../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 168 ++++++++++++++++++
3 files changed, 216 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 7427a20934f3..c54922a325fd 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -3,4 +3,5 @@ dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
new file mode 100644
index 000000000000..51d0c5176b9e
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+// #include "dt-bindings/mailbox/miv-ihc.h"
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
new file mode 100644
index 000000000000..5ad2fbd1b7ae
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Original all-in-one devicetree:
+ * Copyright (C) 2020-2022 - Aldec
+ * Rewritten to use includes:
+ * Copyright (C) 2022 - Conor Dooley <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-tysom-m-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ model = "Aldec TySOM-M-MPFS250T";
+ compatible = "aldec,tysom-m-mpfs250t", "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ gpio0 = &gpio0;
+ gpio1 = &gpio2;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x00000000 0x0 0x40000000>;
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ led0 {
+ gpios = <&gpio1 23 1>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ hwmon: hwmon@45 {
+ status = "okay";
+ compatible = "ti,ina219";
+ reg = <0x45>;
+ shunt-resistor = <2000>;
+ };
+};
+
+&gpio1 {
+ interrupts = <27>, <28>, <29>, <30>,
+ <31>, <32>, <33>, <47>,
+ <35>, <36>, <37>, <38>,
+ <39>, <40>, <41>, <42>,
+ <43>, <44>, <45>, <46>,
+ <47>, <48>, <49>, <50>;
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ no-1-8-v;
+ disable-wp;
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart2 {
+ status = "okay";
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ status = "okay";
+ reg = <0x0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.36.1
Per their website:
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA)
company delivering innovative design creation, simulation and
verification solutions to assist in the development of complex FPGA,
ASIC, SoC and embedded system designs.
Link: https://www.aldec.com/
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 2f0151e9f6be..922be64799a2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -69,6 +69,8 @@ patternProperties:
description: Annapurna Labs
"^alcatel,.*":
description: Alcatel
+ "^aldec,.*":
+ description: Aldec, Inc.
"^allegro,.*":
description: Allegro DVT
"^allo,.*":
--
2.36.1
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
a Microchip PolarFire SoC MPFS250T-FCG1152.
Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index ab0a64cd5386..0bd62924d3e4 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
+ - aldec,tysom-m-mpfs250t
- aries,m100pfsevp
- microchip,mpfs-sev-kit
- sundance,polarberry
--
2.36.1
On 06/09/2022 14:15, Conor Dooley wrote:
> The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
> a Microchip PolarFire SoC MPFS250T-FCG1152.
>
> Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 06/09/2022 14:11, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 06/09/2022 14:15, Conor Dooley wrote:
>> The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
>> a Microchip PolarFire SoC MPFS250T-FCG1152. Features include:
>> - 16 GB FPGA DDR4
>> - 16 GB MSS DDR4 with ECC
>> - eMMC
>> - SPI flash memory
>> - 2x Ethernet 10/100/1000
>> - USB 2.0
>> - PCIe x4 Gen2
>> - HDMI OUT
>> - 2x FMC connector (HPC and LPC)
>> +
>> +&spi1 {
>> + status = "okay";
>> + flash@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> Are these needed? Does it pass dtbs_check?
It did, yea. But you're right in that they're not needed, I deleted some
dummy flash partitions that were in the dts I received and I didn't see
the cells too.
I'm likely going to sit on this patch for quite a while, but the various
things you pointed out all are valid, so they'll be sorted by the
eventual v2...
As always, thanks!
>
>> + compatible = "micron,n25q128a11", "jedec,spi-nor";
>> + status = "okay";
>
> No need for status.
On 06/09/2022 14:15, Conor Dooley wrote:
> The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
> a Microchip PolarFire SoC MPFS250T-FCG1152. Features include:
> - 16 GB FPGA DDR4
> - 16 GB MSS DDR4 with ECC
> - eMMC
> - SPI flash memory
> - 2x Ethernet 10/100/1000
> - USB 2.0
> - PCIe x4 Gen2
> - HDMI OUT
> - 2x FMC connector (HPC and LPC)
>
> Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> arch/riscv/boot/dts/microchip/Makefile | 1 +
> .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++
> .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 168 ++++++++++++++++++
> 3 files changed, 216 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
>
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> index 7427a20934f3..c54922a325fd 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -3,4 +3,5 @@ dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
> dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
> new file mode 100644
> index 000000000000..51d0c5176b9e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2022 Microchip Technology Inc */
> +
> +// #include "dt-bindings/mailbox/miv-ihc.h"
> +
> +/ {
> + fabric_clk3: fabric-clk3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <62500000>;
> + };
> +
> + fabric_clk1: fabric-clk1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + pcie: pcie@2000000000 {
> + compatible = "microchip,pcie-host-1.0";
> + #address-cells = <0x3>;
> + #interrupt-cells = <0x1>;
> + #size-cells = <0x2>;
> + device_type = "pci";
> + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
> + reg-names = "cfg", "apb";
> + bus-range = <0x0 0x7f>;
> + interrupt-parent = <&plic>;
> + interrupts = <119>;
> + interrupt-map = <0 0 0 1 &pcie_intc 0>,
> + <0 0 0 2 &pcie_intc 1>,
> + <0 0 0 3 &pcie_intc 2>,
> + <0 0 0 4 &pcie_intc 3>;
> + interrupt-map-mask = <0 0 0 7>;
> + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
> + clock-names = "fic0", "fic1", "fic3";
> + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
> + msi-parent = <&pcie>;
> + msi-controller;
> + status = "disabled";
> + pcie_intc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> new file mode 100644
> index 000000000000..5ad2fbd1b7ae
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Original all-in-one devicetree:
> + * Copyright (C) 2020-2022 - Aldec
> + * Rewritten to use includes:
> + * Copyright (C) 2022 - Conor Dooley <[email protected]>
> + */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-tysom-m-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ 1000000
> +
> +/ {
> + model = "Aldec TySOM-M-MPFS250T";
> + compatible = "aldec,tysom-m-mpfs250t", "microchip,mpfs";
> +
> + aliases {
> + ethernet0 = &mac0;
> + ethernet1 = &mac1;
> + serial0 = &mmuart0;
> + serial1 = &mmuart1;
> + serial2 = &mmuart2;
> + serial3 = &mmuart3;
> + serial4 = &mmuart4;
> + gpio0 = &gpio0;
> + gpio1 = &gpio2;
> + };
> +
> + chosen {
> + stdout-path = "serial1:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <MTIMER_FREQ>;
> + };
> +
> + ddrc_cache_lo: memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x40000000>;
> + status = "okay";
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
> + device_type = "memory";
> + reg = <0x10 0x00000000 0x0 0x40000000>;
> + status = "okay";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + status = "okay";
> +
> + led0 {
Typically this is led-0
> + gpios = <&gpio1 23 1>;
Does '1' stand for some GPIO flag?
> + default-state = "on";
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + hwmon: hwmon@45 {
> + status = "okay";
No need for status.
> + compatible = "ti,ina219";
> + reg = <0x45>;
> + shunt-resistor = <2000>;
> + };
> +};
> +
> +&gpio1 {
> + interrupts = <27>, <28>, <29>, <30>,
> + <31>, <32>, <33>, <47>,
> + <35>, <36>, <37>, <38>,
> + <39>, <40>, <41>, <42>,
> + <43>, <44>, <45>, <46>,
> + <47>, <48>, <49>, <50>;
> + status = "okay";
> +};
> +
> +&mac0 {
> + status = "okay";
> + phy-mode = "gmii";
> + phy-handle = <&phy0>;
> +
> +};
> +
> +&mac1 {
> + status = "okay";
> + phy-mode = "gmii";
> + phy-handle = <&phy1>;
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
> +
> +&mbox {
> + status = "okay";
> +};
> +
> +&mmc {
> + max-frequency = <200000000>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + no-1-8-v;
> + disable-wp;
> + status = "okay";
> +};
> +
> +&mmuart1 {
> + status = "okay";
> +};
> +
> +&mmuart2 {
> + status = "okay";
> +};
> +
> +&mmuart3 {
> + status = "okay";
> +};
> +
> +&mmuart4 {
> + status = "okay";
> +};
> +
> +&refclk {
> + clock-frequency = <125000000>;
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> +};
> +
> +&spi1 {
> + status = "okay";
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
Are these needed? Does it pass dtbs_check?
> + compatible = "micron,n25q128a11", "jedec,spi-nor";
> + status = "okay";
No need for status.
Best regards,
Krzysztof
On 06/09/2022 14:15, Conor Dooley wrote:
> Per their website:
> Aldec, Inc. is an industry-leading Electronic Design Automation (EDA)
> company delivering innovative design creation, simulation and
> verification solutions to assist in the development of complex FPGA,
> ASIC, SoC and embedded system designs.
>
> Link: https://www.aldec.com/
> Signed-off-by: Conor Dooley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof