From: Quentin Schulz <[email protected]>
Since the split of gpio and pinctrl in their own driver, gpio-sysfs and
libgpiod userspace GPIO handling has been broken because the pins aren't
put into their GPIO function anymore since pinctrl subsystem is
"bypassed" when requesting GPIOs from userspace.
This fixes it by making the gpio driver actually request from the
pinctrl subsystem to put the pin in its GPIO function when the GPIO
direction is set in userspace.
I discovered the issue because we have a GPIO the user needs to control
from userspace to flash FW on an on-board STM32 that is actually on the
same pin as one used by the flash controller. Considering the storage
medium tried by the BOOTROM is emmc->nor->nand->sdmmc, booting from emmc
didn't show the issue because the default function for pins is GPIO and
the flash controller pins didn't need to be muxed by the BOOTROM.
However, if there's nothing on emmc, the BOOTROM does the pinmux for SPI
controller and puts the pins in their flash mode and therefore the
handling of that pin as a GPIO from userspace was not possible, but only
when booting on something else than eMMC.
This restores the behavior as seen in v5.14 and earlier.
v2:
- fix missing header; reported by kernel test robot <[email protected]>
Cheers,
Quentin
Quentin Schulz (2):
pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback
gpio: rockchip: request GPIO mux to pinctrl when setting direction
drivers/gpio/gpio-rockchip.c | 7 +++++++
drivers/pinctrl/pinctrl-rockchip.c | 13 +++++++++++++
2 files changed, 20 insertions(+)
--
2.37.3
From: Quentin Schulz <[email protected]>
Before the split of gpio and pinctrl sections in their own driver,
rockchip_set_mux was called in pinmux_ops.gpio_set_direction for
configuring a pin in its GPIO function.
This is essential for cases where pinctrl is "bypassed" by gpio
consumers otherwise the GPIO function is not configured for the pin and
it does not work. Such was the case for the sysfs/libgpiod userspace
GPIO handling.
Let's re-implement the pinmux_ops.gpio_set_direction callback so that
the gpio subsystem can request from the pinctrl driver to put the pin in
its GPIO function.
Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes")
Cc: [email protected]
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
---
v2:
- added Reviewed-by,
drivers/pinctrl/pinctrl-rockchip.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 32e41395fc768..c84bd0e1ce5a6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2393,11 +2393,24 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
+static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset,
+ bool input)
+{
+ struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+ struct rockchip_pin_bank *bank;
+
+ bank = pin_to_bank(info, offset);
+ return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
+}
+
static const struct pinmux_ops rockchip_pmx_ops = {
.get_functions_count = rockchip_pmx_get_funcs_count,
.get_function_name = rockchip_pmx_get_func_name,
.get_function_groups = rockchip_pmx_get_groups,
.set_mux = rockchip_pmx_set,
+ .gpio_set_direction = rockchip_pmx_gpio_set_direction,
};
/*
--
2.37.3
From: Quentin Schulz <[email protected]>
Before the split of gpio and pinctrl sections in their own driver,
rockchip_set_mux was called in pinmux_ops.gpio_set_direction for
configuring a pin in its GPIO function.
This is essential for cases where pinctrl is "bypassed" by gpio
consumers otherwise the GPIO function is not configured for the pin and
it does not work. Such was the case for the sysfs/libgpiod userspace
GPIO handling.
Let's call pinctrl_gpio_direction_input/output when setting the
direction of a GPIO so that the pinctrl core requests from the rockchip
pinctrl driver to put the pin in its GPIO function.
Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes")
Fixes: 936ee2675eee ("gpio/rockchip: add driver for rockchip gpio")
Cc: [email protected]
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
---
v2:
- added Reviewed-by,
- added missing linux/pinctrl/consumer.h header,
drivers/gpio/gpio-rockchip.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index bb50335239ac8..9c976ad7208ef 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -19,6 +19,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
@@ -156,6 +157,12 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip,
unsigned long flags;
u32 data = input ? 0 : 1;
+
+ if (input)
+ pinctrl_gpio_direction_input(bank->pin_base + offset);
+ else
+ pinctrl_gpio_direction_output(bank->pin_base + offset);
+
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
--
2.37.3
On Fri, Sep 30, 2022 at 3:20 PM Quentin Schulz <[email protected]> wrote:
> From: Quentin Schulz <[email protected]>
>
> Since the split of gpio and pinctrl in their own driver, gpio-sysfs and
> libgpiod userspace GPIO handling has been broken because the pins aren't
> put into their GPIO function anymore since pinctrl subsystem is
> "bypassed" when requesting GPIOs from userspace.
>
> This fixes it by making the gpio driver actually request from the
> pinctrl subsystem to put the pin in its GPIO function when the GPIO
> direction is set in userspace.
>
> I discovered the issue because we have a GPIO the user needs to control
> from userspace to flash FW on an on-board STM32 that is actually on the
> same pin as one used by the flash controller. Considering the storage
> medium tried by the BOOTROM is emmc->nor->nand->sdmmc, booting from emmc
> didn't show the issue because the default function for pins is GPIO and
> the flash controller pins didn't need to be muxed by the BOOTROM.
> However, if there's nothing on emmc, the BOOTROM does the pinmux for SPI
> controller and puts the pins in their flash mode and therefore the
> handling of that pin as a GPIO from userspace was not possible, but only
> when booting on something else than eMMC.
>
> This restores the behavior as seen in v5.14 and earlier.
>
> v2:
> - fix missing header; reported by kernel test robot <[email protected]>
Patches applied to the pinctrl tree (also the GPIO patch) as that is the
dependence point. Will go into v6.1 merge window.
Yours,
Linus Walleij