v2 -- Commit "PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits"
- s/read compeletion boudnary/Read Completion Boundary/ (Bjorn)
v1 -- original
Jim Quinlan (5):
PCI: brcmstb: Enable Multi-MSI
PCI: brcmstb: Wait for 100ms following PERST# deassert
PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()
PCI: brcmstb: Functions needlessly specified as "inline"
PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits
drivers/pci/controller/pcie-brcmstb.c | 85 +++++++++++++++------------
1 file changed, 48 insertions(+), 37 deletions(-)
base-commit: 833477fce7a14d43ae4c07f8ddc32fa5119471a2
--
2.17.1
We always wanted to enable Multi-MSI but didn't have a test device until
recently. In addition, there are some devices out there that will ask for
multiple MSI but refuse to work if they are only granted one.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 521acd632f1a..a45ce7d61847 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -445,7 +445,8 @@ static struct irq_chip brcm_msi_irq_chip = {
static struct msi_domain_info brcm_msi_domain_info = {
/* Multi MSI is supported by the controller, but not by this driver */
- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_MULTI_PCI_MSI),
.chip = &brcm_msi_irq_chip,
};
@@ -505,21 +506,23 @@ static struct irq_chip brcm_msi_bottom_irq_chip = {
.irq_ack = brcm_msi_ack_irq,
};
-static int brcm_msi_alloc(struct brcm_msi *msi)
+static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs)
{
int hwirq;
mutex_lock(&msi->lock);
- hwirq = bitmap_find_free_region(msi->used, msi->nr, 0);
+ hwirq = bitmap_find_free_region(msi->used, msi->nr,
+ order_base_2(nr_irqs));
mutex_unlock(&msi->lock);
return hwirq;
}
-static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq,
+ unsigned int nr_irqs)
{
mutex_lock(&msi->lock);
- bitmap_release_region(msi->used, hwirq, 0);
+ bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs));
mutex_unlock(&msi->lock);
}
@@ -527,16 +530,17 @@ static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *args)
{
struct brcm_msi *msi = domain->host_data;
- int hwirq;
+ int hwirq, i;
- hwirq = brcm_msi_alloc(msi);
+ hwirq = brcm_msi_alloc(msi, nr_irqs);
if (hwirq < 0)
return hwirq;
- irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
- &brcm_msi_bottom_irq_chip, domain->host_data,
- handle_edge_irq, NULL, NULL);
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_info(domain, virq + i, hwirq + i,
+ &brcm_msi_bottom_irq_chip, domain->host_data,
+ handle_edge_irq, NULL, NULL);
return 0;
}
@@ -546,7 +550,7 @@ static void brcm_irq_domain_free(struct irq_domain *domain,
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
- brcm_msi_free(msi, d->hwirq);
+ brcm_msi_free(msi, d->hwirq, nr_irqs);
}
static const struct irq_domain_ops msi_domain_ops = {
--
2.17.1
Be prudent and give some time for power and clocks to become stable. As
described in the PCIe CEM specification sections 2.2 and 2.2.1; as well as
PCIe r5.0, 6.6.1.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index a45ce7d61847..39b545713ba0 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1037,8 +1037,15 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
pcie->perst_set(pcie, 0);
/*
- * Give the RC/EP time to wake up, before trying to configure RC.
- * Intermittently check status for link-up, up to a total of 100ms.
+ * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
+ * sections 2.2, PCIe r5.0, 6.6.1.
+ */
+ msleep(100);
+
+ /*
+ * Give the RC/EP even more time to wake up, before trying to
+ * configure RC. Intermittently check status for link-up, up to a
+ * total of 100ms.
*/
for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
msleep(5);
--
2.17.1
A number of inline functions are called rarely and/or are not
time-critical. Take out the "inline" and let the compiler do its work.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index c7210cec1f58..e3045f1eadbc 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -723,7 +723,7 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
return base + DATA_ADDR(pcie);
}
-static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
+static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
{
u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
@@ -733,7 +733,7 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie,
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
}
-static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
+static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
{
u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
@@ -743,7 +743,7 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
}
-static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
+static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
{
if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
return;
@@ -754,7 +754,7 @@ static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
reset_control_deassert(pcie->perst_reset);
}
-static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
+static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
{
u32 tmp;
@@ -764,7 +764,7 @@ static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
}
-static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
+static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
{
u32 tmp;
@@ -773,7 +773,7 @@ static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
}
-static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
+static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
u64 *rc_bar2_size,
u64 *rc_bar2_offset)
{
--
2.17.1
Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
the Maximum Payload Size (MPS) are returned in one completion, and data for
PCIe read requests greater than the MPS are split at the specified Read
Completion Boundary setting.
Set RCB_64B so that the Read Compeletion Boundary is 64B.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index e3045f1eadbc..edf283e2b5dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -53,6 +53,8 @@
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
+#define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
@@ -900,11 +902,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
else
burst = 0x2; /* 512 bytes */
- /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+ /*
+ * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN,
+ * RCB_MPS_MODE, RCB_64B_MODE
+ */
tmp = readl(base + PCIE_MISC_MISC_CTRL);
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK);
+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK);
writel(tmp, base + PCIE_MISC_MISC_CTRL);
ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
--
2.17.1
It would be nice to replace the PCIe link-up loop as well but
there are too many uses of this that do not poll (and the
read_poll_timeout uses "timeout==0" to loop forever).
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 39b545713ba0..c7210cec1f58 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -9,6 +9,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
@@ -302,42 +303,34 @@ static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
/* negative return value indicates error */
static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
{
- int tries;
u32 data;
+ int err;
writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
base + PCIE_RC_DL_MDIO_ADDR);
readl(base + PCIE_RC_DL_MDIO_ADDR);
-
- data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
- for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
- udelay(10);
- data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
- }
-
+ err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_RD_DATA, data,
+ MDIO_RD_DONE(data), 10, 100);
*val = FIELD_GET(MDIO_DATA_MASK, data);
- return MDIO_RD_DONE(data) ? 0 : -EIO;
+
+ return err;
}
/* negative return value indicates error */
static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
u8 regad, u16 wrdata)
{
- int tries;
u32 data;
+ int err;
writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
base + PCIE_RC_DL_MDIO_ADDR);
readl(base + PCIE_RC_DL_MDIO_ADDR);
writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
- data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
- for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
- udelay(10);
- data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
- }
-
- return MDIO_WT_DONE(data) ? 0 : -EIO;
+ err = readw_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data,
+ MDIO_WT_DONE(data), 10, 100);
+ return err;
}
/*
--
2.17.1
If you have occasion to revise this series, update the subject to be a
sentence like the others, e.g., something like
PCI: brcmstb: Drop needless 'inline' annotations
On Tue, Oct 11, 2022 at 02:42:09PM -0400, Jim Quinlan wrote:
> A number of inline functions are called rarely and/or are not
> time-critical. Take out the "inline" and let the compiler do its work.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Acked-by: Florian Fainelli <[email protected]>
Thanks, looks good to me!
Reviewed-by: Bjorn Helgaas <[email protected]>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index c7210cec1f58..e3045f1eadbc 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -723,7 +723,7 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
> return base + DATA_ADDR(pcie);
> }
>
> -static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
> +static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
> u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
> @@ -733,7 +733,7 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie,
> writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> }
>
> -static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
> +static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
> u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
> @@ -743,7 +743,7 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32
> writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> }
>
> -static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
> +static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
> {
> if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
> return;
> @@ -754,7 +754,7 @@ static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
> reset_control_deassert(pcie->perst_reset);
> }
>
> -static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
> +static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp;
>
> @@ -764,7 +764,7 @@ static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
> writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
> }
>
> -static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
> +static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp;
>
> @@ -773,7 +773,7 @@ static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
> writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> }
>
> -static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> +static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> u64 *rc_bar2_size,
> u64 *rc_bar2_offset)
> {
> --
> 2.17.1
>
On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> the Maximum Payload Size (MPS) are returned in one completion, and data for
> PCIe read requests greater than the MPS are split at the specified Read
> Completion Boundary setting.
>
> Set RCB_64B so that the Read Compeletion Boundary is 64B.
s/Compeletion/Completion/
On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <[email protected]> wrote:
>
> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > the Maximum Payload Size (MPS) are returned in one completion, and data for
> > PCIe read requests greater than the MPS are split at the specified Read
> > Completion Boundary setting.
> >
> > Set RCB_64B so that the Read Compeletion Boundary is 64B.
>
> s/Compeletion/Completion/
Hi Bjorn,
TIL that checkpatch.pl only flags misspelled words only if they match
its list of misspelled words.
I've modified my checkpatch.pl wrapper script to use aspell to better
address my typos.
At any rate, do you mind if I add some new commits for V3?
Thanks,
Jim Quinlan
Broadcom STB
On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <[email protected]> wrote:
> > On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > > Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > > the Maximum Payload Size (MPS) are returned in one completion, and data for
> > > PCIe read requests greater than the MPS are split at the specified Read
> > > Completion Boundary setting.
> > >
> > > Set RCB_64B so that the Read Compeletion Boundary is 64B.
> >
> > s/Compeletion/Completion/
>
> Hi Bjorn,
>
> TIL that checkpatch.pl only flags misspelled words only if they match
> its list of misspelled words.
> I've modified my checkpatch.pl wrapper script to use aspell to better
> address my typos.
> At any rate, do you mind if I add some new commits for V3?
Fine with me, I think Lorenzo will look at these again after v6.1-rc1
is tagged this weekend.
Bjorn
On 10/14/22 12:27, Bjorn Helgaas wrote:
> On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
>> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <[email protected]> wrote:
>>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
>>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
>>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
>>>> PCIe read requests greater than the MPS are split at the specified Read
>>>> Completion Boundary setting.
>>>>
>>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
>>>
>>> s/Compeletion/Completion/
>>
>> Hi Bjorn,
>>
>> TIL that checkpatch.pl only flags misspelled words only if they match
>> its list of misspelled words.
>> I've modified my checkpatch.pl wrapper script to use aspell to better
>> address my typos.
>> At any rate, do you mind if I add some new commits for V3?
>
> Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> is tagged this weekend.
Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!
--
Florian
On Thu, Nov 3, 2022 at 2:49 PM Florian Fainelli <[email protected]> wrote:
>
> On 10/14/22 12:27, Bjorn Helgaas wrote:
> > On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> >> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <[email protected]> wrote:
> >>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> >>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> >>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
> >>>> PCIe read requests greater than the MPS are split at the specified Read
> >>>> Completion Boundary setting.
> >>>>
> >>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
> >>>
> >>> s/Compeletion/Completion/
> >>
> >> Hi Bjorn,
> >>
> >> TIL that checkpatch.pl only flags misspelled words only if they match
> >> its list of misspelled words.
> >> I've modified my checkpatch.pl wrapper script to use aspell to better
> >> address my typos.
> >> At any rate, do you mind if I add some new commits for V3?
> >
> > Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> > is tagged this weekend.
>
> Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!
Oops, I said I would add some commits but I don't have time right now.
Bjorn or Lorenzo, could you review what is there and if you accept
the commits can you please make the single spelling correction? If
not, I will correct the spelling along with any other requested
changes.
Regards,
Jim Quinlan
Broadcom STB
>
> --
> Florian
>
On Tue, 11 Oct 2022 14:42:05 -0400, Jim Quinlan wrote:
> v2 -- Commit "PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits"
> - s/read compeletion boudnary/Read Completion Boundary/ (Bjorn)
>
> v1 -- original
>
> Jim Quinlan (5):
> PCI: brcmstb: Enable Multi-MSI
> PCI: brcmstb: Wait for 100ms following PERST# deassert
> PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()
> PCI: brcmstb: Functions needlessly specified as "inline"
> PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits
>
> [...]
Applied to pci/brcmstb, thanks!
[1/5] PCI: brcmstb: Enable Multi-MSI
https://git.kernel.org/lpieralisi/pci/c/198acab1772f
[2/5] PCI: brcmstb: Wait for 100ms following PERST# deassert
https://git.kernel.org/lpieralisi/pci/c/3ae140ad827b
[3/5] PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()
https://git.kernel.org/lpieralisi/pci/c/ca5dcc76314d
[4/5] PCI: brcmstb: Functions needlessly specified as "inline"
https://git.kernel.org/lpieralisi/pci/c/137b57413f56
[5/5] PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits
https://git.kernel.org/lpieralisi/pci/c/602fb860945f
Thanks,
Lorenzo
On Thu, Nov 03, 2022 at 03:43:13PM -0400, Jim Quinlan wrote:
> On Thu, Nov 3, 2022 at 2:49 PM Florian Fainelli <[email protected]> wrote:
> >
> > On 10/14/22 12:27, Bjorn Helgaas wrote:
> > > On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> > >> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <[email protected]> wrote:
> > >>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > >>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > >>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
> > >>>> PCIe read requests greater than the MPS are split at the specified Read
> > >>>> Completion Boundary setting.
> > >>>>
> > >>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
> > >>>
> > >>> s/Compeletion/Completion/
> > >>
> > >> Hi Bjorn,
> > >>
> > >> TIL that checkpatch.pl only flags misspelled words only if they match
> > >> its list of misspelled words.
> > >> I've modified my checkpatch.pl wrapper script to use aspell to better
> > >> address my typos.
> > >> At any rate, do you mind if I add some new commits for V3?
> > >
> > > Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> > > is tagged this weekend.
> >
> > Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!
>
> Oops, I said I would add some commits but I don't have time right now.
> Bjorn or Lorenzo, could you review what is there and if you accept
> the commits can you please make the single spelling correction? If
> not, I will correct the spelling along with any other requested
> changes.
I will fix the spelling, reviewing the patches now.
Lorenzo