Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
i.MX8MP PCIe reference clock.
The following properties of PHY dts node should be changed accordingly.
- Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
- Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
Signed-off-by: Richard Zhu <[email protected]>
---
Base on 6.1-rc1, and the following PHY changes [1],
the PCIe works fine when SYSPLL is used as reference clock on i.MX8MP
EVK board(schematic-46370) after removing R131/R132/R137/R138, and
populating R135/R136.
[1] https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
---
drivers/soc/imx/imx8mp-blk-ctrl.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 0e3b6ba22f94..5ad20a8ea25e 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -21,6 +21,16 @@
#define USB_CLOCK_MODULE_EN BIT(1)
#define PCIE_PHY_APB_RST BIT(4)
#define PCIE_PHY_INIT_RST BIT(5)
+#define GPR_REG2 0x8
+#define P_PLL_MASK GENMASK(5, 0)
+#define M_PLL_MASK GENMASK(15, 6)
+#define S_PLL_MASK GENMASK(18, 16)
+#define P_PLL (0xc << 0)
+#define M_PLL (0x320 << 6)
+#define S_PLL (0x4 << 16)
+#define GPR_REG3 0xc
+#define PLL_CKE BIT(17)
+#define PLL_RST BIT(31)
struct imx8mp_blk_ctrl_domain;
@@ -86,6 +96,18 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
case IMX8MP_HSIOBLK_PD_PCIE_PHY:
regmap_set_bits(bc->regmap, GPR_REG0,
PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+
+ /* Set the PLL configurations, P = 12, M = 800, S = 4. */
+ regmap_update_bits(bc->regmap, GPR_REG2,
+ P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
+ P_PLL | M_PLL | S_PLL);
+ udelay(1);
+
+ regmap_update_bits(bc->regmap, GPR_REG3, PLL_RST, PLL_RST);
+ udelay(10);
+
+ /* Set 1b'1 to pll_cke of GPR_REG3 */
+ regmap_update_bits(bc->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
break;
default:
break;
--
2.25.1
On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> i.MX8MP PCIe reference clock.
>
> The following properties of PHY dts node should be changed accordingly.
> - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
>
> Signed-off-by: Richard Zhu <[email protected]>
Applied, thanks!
Hi Shawn, Richard,
Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > i.MX8MP PCIe reference clock.
> >
> > The following properties of PHY dts node should be changed accordingly.
> > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> >
> > Signed-off-by: Richard Zhu <[email protected]>
>
> Applied, thanks!
Sorry for the late reply, but I'm not really happy with the fact that
the PLL is now unconditionally enabled, even though it is only needed
when there is no external reference clock source.
I fear that this will be hard to correct later on as the DT abstraction
is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
PHY, but the PLL generated clock, which isn't properly exposed with
this series.
I'm not happy to see this going in in the current state and if not too
late would like to ask Shawn to remove it from the tree again.
Regards,
Lucas
> -----Original Message-----
> From: Lucas Stach <[email protected]>
> Sent: 2022年11月1日 16:45
> To: Shawn Guo <[email protected]>; Hongxing Zhu
> <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> configurations
>
> Hi Shawn, Richard,
>
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used
> > > as i.MX8MP PCIe reference clock.
> > >
> > > The following properties of PHY dts node should be changed accordingly.
> > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > >
> > > Signed-off-by: Richard Zhu <[email protected]>
> >
> > Applied, thanks!
>
> Sorry for the late reply, but I'm not really happy with the fact that the PLL is
> now unconditionally enabled, even though it is only needed when there is no
> external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction is wrong, as
> IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the PHY, but the PLL
> generated clock, which isn't properly exposed with this series.
Hi Lucas:
First of all, thanks for your comments.
IMHO, I'm not sure it's proper or not to describe the hardware logic in
the PHY node when internal SYSPLL is used as PCIe PHY reference clock.
So, I'm trying to get some suggestions and used to send out an email to
you and Marcel on Sep20.
Okay, if you think it's not correct to expose IMX8MP_CLK_HSIO_ROOT clock
out.
Which clock you are prefer to use as PHY reference clock here?
Thanks.
Best Regards
Richard Zhu
>
> I'm not happy to see this going in in the current state and if not too late would
> like to ask Shawn to remove it from the tree again.
>
> Regards,
> Lucas
On Tue, Nov 01, 2022 at 09:44:41AM +0100, Lucas Stach wrote:
> Hi Shawn, Richard,
>
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > > i.MX8MP PCIe reference clock.
> > >
> > > The following properties of PHY dts node should be changed accordingly.
> > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > >
> > > Signed-off-by: Richard Zhu <[email protected]>
> >
> > Applied, thanks!
>
> Sorry for the late reply, but I'm not really happy with the fact that
> the PLL is now unconditionally enabled, even though it is only needed
> when there is no external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction
> is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
> PHY, but the PLL generated clock, which isn't properly exposed with
> this series.
>
> I'm not happy to see this going in in the current state and if not too
> late would like to ask Shawn to remove it from the tree again.
Removed.
Shawn
> -----Original Message-----
> From: Hongxing Zhu
> Sent: 2022年11月2日 9:46
> To: Lucas Stach <[email protected]>; Shawn Guo <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>;
> [email protected]
> Subject: RE: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> configurations
>
> > -----Original Message-----
> > From: Lucas Stach <[email protected]>
> > Sent: 2022年11月1日 16:45
> > To: Shawn Guo <[email protected]>; Hongxing Zhu
> > <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; dl-linux-imx <[email protected]>
> > Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> > configurations
> >
> > Hi Shawn, Richard,
> >
> > Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be
> > > > used as i.MX8MP PCIe reference clock.
> > > >
> > > > The following properties of PHY dts node should be changed accordingly.
> > > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > > >
> > > > Signed-off-by: Richard Zhu <[email protected]>
> > >
> > > Applied, thanks!
> >
> > Sorry for the late reply, but I'm not really happy with the fact that
> > the PLL is now unconditionally enabled, even though it is only needed
> > when there is no external reference clock source.
> > I fear that this will be hard to correct later on as the DT
> > abstraction is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference
> > clock for the PHY, but the PLL generated clock, which isn't properly exposed
> with this series.
> Hi Lucas:
> First of all, thanks for your comments.
>
> IMHO, I'm not sure it's proper or not to describe the hardware logic in the
> PHY node when internal SYSPLL is used as PCIe PHY reference clock.
> So, I'm trying to get some suggestions and used to send out an email to you
> and Marcel on Sep20.
>
> Okay, if you think it's not correct to expose IMX8MP_CLK_HSIO_ROOT clock
> out.
> Which clock you are prefer to use as PHY reference clock here?
>
> Thanks.
>
> Best Regards
> Richard Zhu
> >
> > I'm not happy to see this going in in the current state and if not too
> > late would like to ask Shawn to remove it from the tree again.
Hi Lucas:
Refer to the "Reference Clock Section" of i.MX8MP PCIe PHY document.
I_pll_refclk_from_syspll clock is used as reference clock when Inner chip
clock mode is used.
In the current codes, IMX8MP_CLK_HSIO_AXI is source from sys_pll2 clock.
is it reasonable that use it as PCIe reference clock in this scenario here?
Best Regards
Richard Zhu
> >
> > Regards,
> > Lucas