Add the camera clock controller node and CCI nodes to sm6350 dtsi and enable
the i2c busses on Fairphone 4 dts.
This is tested using PM8008 regulator patches from the lists which power the
cameras, and using i2cdetect/i2cget/i2cset reading the sensor ID registers.
To: Andy Gross <[email protected]>
To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
To: Loic Poulain <[email protected]>
To: Robert Foss <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
Cc: ~postmarketos/[email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Luca Weiss <[email protected]>
---
Luca Weiss (4):
dt-bindings: i2c: qcom-cci: Document SM6350 compatible
arm64: dts: qcom: sm6350: Add camera clock controller
arm64: dts: qcom: sm6350: Add CCI nodes
arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI busses
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 141 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 20 +++
3 files changed, 163 insertions(+)
---
base-commit: 1578f85d549045aac441821064e7953732460e51
change-id: 20221213-sm6350-cci-38baf19ace3b
Best regards,
--
Luca Weiss <[email protected]>
Add a node for the camcc found on SM6350 SoC.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8224adb99948..300ced5cda57 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1435,6 +1435,15 @@ usb_1_dwc3: usb@a600000 {
};
};
+ camcc: clock-controller@ad00000 {
+ compatible = "qcom,sm6350-camcc";
+ reg = <0 0x0ad00000 0 0x16000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
--
2.39.1
Document the compatible for the CCI block found on SM6350 SoC.
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 87e414f0c39c..ec79b7270437 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
- qcom,sdm845-cci
+ - qcom,sm6350-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
- const: qcom,msm8996-cci # CCI v2
@@ -139,6 +140,7 @@ allOf:
contains:
enum:
- qcom,sdm845-cci
+ - qcom,sm6350-cci
then:
properties:
clocks:
--
2.39.1
On 20/01/2023 12:11, Luca Weiss wrote:
> Document the compatible for the CCI block found on SM6350 SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Enable the CCI busses that have cameras connected to them.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index f0e7ae630e0c..ed0cb70849d3 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -363,6 +363,26 @@ vreg_bob: bob {
};
};
+&cci0 {
+ status = "okay";
+};
+
+&cci0_i2c0 {
+ /* IMX582 @ 0x1a */
+};
+
+&cci0_i2c1 {
+ /* IMX582 @ 0x1a */
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ /* IMX576 @ 0x10 */
+};
+
&cdsp {
status = "okay";
firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
--
2.39.1
Add nodes for the two CCI blocks found on SM6350.
The first contains two i2c busses and while the second one might also
contains two busses, the downstream kernel only has one configured, and
some boards use the GPIOs for the potential cci1_i2c1 one other
purposes, so leave that one unconfigured.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 300ced5cda57..666c1c80e4e6 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm6350-camcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 {
};
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4a000 0 0x1000>;
+ interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SOC_AHB_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_0_CLK>,
+ <&camcc CAMCC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "soc_ahb",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CCI_0_CLK>;
+ assigned-clock-rates = <80000000>, <37500000>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4b000 0 0x1000>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SOC_AHB_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_1_CLK>,
+ <&camcc CAMCC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "soc_ahb",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CCI_1_CLK>;
+ assigned-clock-rates = <80000000>, <37500000>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci2_default>;
+ pinctrl-1 = <&cci2_sleep>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sm6350-camcc";
reg = <0 0x0ad00000 0 0x16000>;
@@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
+ cci0_default: cci0-default-state {
+ pins = "gpio39", "gpio40";
+ function = "cci_i2c";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ pins = "gpio39", "gpio40";
+ function = "cci_i2c";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio41", "gpio42";
+ function = "cci_i2c";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ pins = "gpio41", "gpio42";
+ function = "cci_i2c";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ cci2_default: cci2-default-state {
+ pins = "gpio43", "gpio44";
+ function = "cci_i2c";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ pins = "gpio43", "gpio44";
+ function = "cci_i2c";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
sdc2_off_state: sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
--
2.39.1
On 20.01.2023 12:11, Luca Weiss wrote:
> Add nodes for the two CCI blocks found on SM6350.
>
> The first contains two i2c busses and while the second one might also
> contains two busses, the downstream kernel only has one configured, and
> some boards use the GPIOs for the potential cci1_i2c1 one other
> purposes, so leave that one unconfigured.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++
> 1 file changed, 132 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 300ced5cda57..666c1c80e4e6 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -6,6 +6,7 @@
>
> #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm6350-camcc.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 {
> };
> };
>
> + cci0: cci@ac4a000 {
> + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
> + #address-cells = <1>;
> + #size-cells = <0>;
These two belong at the bottom
> +
> + reg = <0 0x0ac4a000 0 0x1000>;
> + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_SOC_AHB_CLK>,
> + <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
> + <&camcc CAMCC_CPAS_AHB_CLK>,
> + <&camcc CAMCC_CCI_0_CLK>,
> + <&camcc CAMCC_CCI_0_CLK_SRC>;
> + clock-names = "camnoc_axi",
> + "soc_ahb",
> + "slow_ahb_src",
> + "cpas_ahb",
> + "cci",
> + "cci_src";
> +
> + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_CCI_0_CLK>;
> + assigned-clock-rates = <80000000>, <37500000>;
> +
> + pinctrl-names = "default", "sleep";
Please move pinctrl-names below pinctrl-N for consistency
with other properties ending with -names.
> + pinctrl-0 = <&cci0_default &cci1_default>;
> + pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> +
> + status = "disabled";
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@ac4b000 {
> + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <0 0x0ac4b000 0 0x1000>;
> + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_SOC_AHB_CLK>,
> + <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
> + <&camcc CAMCC_CPAS_AHB_CLK>,
> + <&camcc CAMCC_CCI_1_CLK>,
> + <&camcc CAMCC_CCI_1_CLK_SRC>;
> + clock-names = "camnoc_axi",
> + "soc_ahb",
> + "slow_ahb_src",
> + "cpas_ahb",
> + "cci",
> + "cci_src";
> +
> + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_CCI_1_CLK>;
> + assigned-clock-rates = <80000000>, <37500000>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&cci2_default>;
> + pinctrl-1 = <&cci2_sleep>;
> +
> + status = "disabled";
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
> + };
> +
> camcc: clock-controller@ad00000 {
> compatible = "qcom,sm6350-camcc";
> reg = <0 0x0ad00000 0 0x16000>;
> @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 {
> #interrupt-cells = <2>;
> gpio-ranges = <&tlmm 0 0 157>;
>
> + cci0_default: cci0-default-state {
> + pins = "gpio39", "gpio40";
> + function = "cci_i2c";
> + bias-pull-up;
Most other pin definitions in our directory have bias
properties below drive-strength, please reorder.
Konrad
> + drive-strength = <2>;
> + };
> +
> + cci0_sleep: cci0-sleep-state {
> + pins = "gpio39", "gpio40";
> + function = "cci_i2c";
> + bias-pull-down;
> + drive-strength = <2>;
> + };
> +
> + cci1_default: cci1-default-state {
> + pins = "gpio41", "gpio42";
> + function = "cci_i2c";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + cci1_sleep: cci1-sleep-state {
> + pins = "gpio41", "gpio42";
> + function = "cci_i2c";
> + bias-pull-down;
> + drive-strength = <2>;
> + };
> +
> + cci2_default: cci2-default-state {
> + pins = "gpio43", "gpio44";
> + function = "cci_i2c";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + cci2_sleep: cci2-sleep-state {
> + pins = "gpio43", "gpio44";
> + function = "cci_i2c";
> + bias-pull-down;
> + drive-strength = <2>;
> + };
> +
> sdc2_off_state: sdc2-off-state {
> clk-pins {
> pins = "sdc2_clk";
>
On 20.01.2023 12:11, Luca Weiss wrote:
> Add a node for the camcc found on SM6350 SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 8224adb99948..300ced5cda57 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1435,6 +1435,15 @@ usb_1_dwc3: usb@a600000 {
> };
> };
>
> + camcc: clock-controller@ad00000 {
> + compatible = "qcom,sm6350-camcc";
> + reg = <0 0x0ad00000 0 0x16000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm6350-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
>
On 20.01.2023 12:11, Luca Weiss wrote:
> Enable the CCI busses that have cameras connected to them.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
> index f0e7ae630e0c..ed0cb70849d3 100644
> --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
> +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
> @@ -363,6 +363,26 @@ vreg_bob: bob {
> };
> };
>
> +&cci0 {
> + status = "okay";
> +};
> +
> +&cci0_i2c0 {
> + /* IMX582 @ 0x1a */
> +};
> +
> +&cci0_i2c1 {
> + /* IMX582 @ 0x1a */
> +};
> +
> +&cci1 {
> + status = "okay";
> +};
> +
> +&cci1_i2c0 {
> + /* IMX576 @ 0x10 */
> +};
> +
> &cdsp {
> status = "okay";
> firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
>