2022-12-13 01:12:09

by Eric Chanudet

[permalink] [raw]
Subject: [PATCH 1/2] arm64: dts: qcom: pm8450a: add rtc node

Add the rtc block on pm8450a first pmic to enable the rtc for
sa8540p-ride.

Signed-off-by: Eric Chanudet <[email protected]>
---
arch/arm64/boot/dts/qcom/pm8450a.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
index 34fc72896761..af761dbfbc66 100644
--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
@@ -13,6 +13,14 @@ pm8450a: pmic@0 {
#address-cells = <1>;
#size-cells = <0>;

+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ };
+
pm8450a_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
--
2.38.1


2022-12-13 01:25:18

by Eric Chanudet

[permalink] [raw]
Subject: [PATCH 2/2] arm64: dts: qcom: sa8295p-adp: use pm8450a dtsi

Include the dtsi to use a single pmic descriptions.
Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently.

Signed-off-by: Eric Chanudet <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +-----------------------
1 file changed, 1 insertion(+), 78 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 84cb6f3eeb56..889259df3287 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/spmi/spmi.h>

#include "sa8540p.dtsi"
+#include "pm8450a.dtsi"

/ {
model = "Qualcomm SA8295P ADP";
@@ -260,84 +261,6 @@ &remoteproc_nsp1 {
status = "okay";
};

-&spmi_bus {
- pm8450a: pmic@0 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@6000 {
- compatible = "qcom,pm8941-rtc";
- reg = <0x6000>;
- reg-names = "rtc", "alarm";
- interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
- wakeup-source;
- };
-
- pm8450a_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450a_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450c: pmic@4 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x4 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450c_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450c_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450e: pmic@8 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x8 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450e_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450e_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450g: pmic@c {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0xc SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450g_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450g_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;

--
2.38.1

2022-12-13 01:37:20

by Dmitry Baryshkov

[permalink] [raw]
Subject: Re: [PATCH 1/2] arm64: dts: qcom: pm8450a: add rtc node



On 13 December 2022 03:55:38 GMT+03:00, Eric Chanudet <[email protected]> wrote:
>Add the rtc block on pm8450a first pmic to enable the rtc for
>sa8540p-ride.
>
>Signed-off-by: Eric Chanudet <[email protected]>
>---
> arch/arm64/boot/dts/qcom/pm8450a.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>index 34fc72896761..af761dbfbc66 100644
>--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>@@ -13,6 +13,14 @@ pm8450a: pmic@0 {
> #address-cells = <1>;
> #size-cells = <0>;
>
>+ rtc@6000 {
>+ compatible = "qcom,pm8941-rtc";
>+ reg = <0x6000>;
>+ reg-names = "rtc", "alarm";
>+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;


0x60?

>+ wakeup-source;
>+ };
>+
> pm8450a_gpios: gpio@c000 {
> compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> reg = <0xc000>;

--
With best wishes
Dmitry

2022-12-13 18:51:57

by Eric Chanudet

[permalink] [raw]
Subject: Re: [PATCH 1/2] arm64: dts: qcom: pm8450a: add rtc node

On Tue, Dec 13, 2022 at 04:18:00AM +0300, Dmitry Baryshkov wrote:
> >diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> >index 34fc72896761..af761dbfbc66 100644
> >--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> >+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> >@@ -13,6 +13,14 @@ pm8450a: pmic@0 {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> >+ rtc@6000 {
> >+ compatible = "qcom,pm8941-rtc";
> >+ reg = <0x6000>;
> >+ reg-names = "rtc", "alarm";
> >+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
>
>
> 0x60?

Checking downstream it uses 0x61 for the ppid. This is also the case
for all other descriptions of that RTC I could find. On the other hand,
that does not describe the "alarm" register bank at 0x6100.
Should it be added, if anything to match reg-names?

I tried a quick test of the alarm on sa8540p-ride:
$ echo $(date '+%s' -d '+ 10 seconds') > /sys/class/rtc/rtc0/wakealarm
It logged the interrupt:
172: 3 0 0 0 0 0 0 0 pmic_arb 101777441 Edge pm8xxx_rtc_alarm

--
Eric Chanudet

2022-12-13 22:36:18

by Dmitry Baryshkov

[permalink] [raw]
Subject: Re: [PATCH 1/2] arm64: dts: qcom: pm8450a: add rtc node



On 13 December 2022 20:18:55 EET, Eric Chanudet <[email protected]> wrote:
>On Tue, Dec 13, 2022 at 04:18:00AM +0300, Dmitry Baryshkov wrote:
>> >diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>> >index 34fc72896761..af761dbfbc66 100644
>> >--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>> >+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
>> >@@ -13,6 +13,14 @@ pm8450a: pmic@0 {
>> > #address-cells = <1>;
>> > #size-cells = <0>;
>> >
>> >+ rtc@6000 {
>> >+ compatible = "qcom,pm8941-rtc";
>> >+ reg = <0x6000>;
>> >+ reg-names = "rtc", "alarm";
>> >+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
>>
>>
>> 0x60?
>
>Checking downstream it uses 0x61 for the ppid. This is also the case
>for all other descriptions of that RTC I could find. On the other hand,
>that does not describe the "alarm" register bank at 0x6100.
>Should it be added, if anything to match reg-names?

Definitely yes. I think otherwise it breaks the idea of reg-names.

>
>I tried a quick test of the alarm on sa8540p-ride:
>$ echo $(date '+%s' -d '+ 10 seconds') > /sys/class/rtc/rtc0/wakealarm
>It logged the interrupt:
>172: 3 0 0 0 0 0 0 0 pmic_arb 101777441 Edge pm8xxx_rtc_alarm
>

--
With best wishes
Dmitry