This series is based on matthias github, v6.1-next.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
Allen-KH Cheng (4):
dt-bindings: power: Add MT8192 ADSP power domain
soc: mediatek: pm-domains: Add ADSP power domain data for MT8192
dt-bindings: arm: mediatek: Add missing power-domains property
arm64: dts: mediatek: Add the missing ADSP power domains controller
for MT8192
.../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
include/dt-bindings/power/mt8192-power.h | 1 +
4 files changed, 43 insertions(+)
--
2.18.0
Add the missing ADSP power domains controller for mt8192-scp_adsp clock
controllers.
Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers")
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..6ee60db3ac23 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -511,6 +511,14 @@
};
};
};
+
+ power-domain@MT8192_POWER_DOMAIN_ADSP {
+ reg = <MT8192_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP_SEL>;
+ clock-names = "adsp";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
};
};
@@ -574,6 +582,7 @@
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>;
#clock-cells = <1>;
};
--
2.18.0
Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
index b97b2051920f..19e58f0ca1df 100644
--- a/drivers/soc/mediatek/mt8192-pm-domains.h
+++ b/drivers/soc/mediatek/mt8192-pm-domains.h
@@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
+ [MT8192_POWER_DOMAIN_ADSP] = {
+ .name = "adsp",
+ .sta_mask = BIT(22),
+ .ctl_offs = 0x0358,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .ext_buck_iso_offs = 0x039C,
+ .ext_buck_iso_mask = BIT(2),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ },
+ .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
+ },
[MT8192_POWER_DOMAIN_CAM] = {
.name = "cam",
.sta_mask = BIT(23),
--
2.18.0
Add power domain ID for the ADSP power partition found on MT8192 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
include/dt-bindings/power/mt8192-power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h
index 4eaa53d7270a..63e81cd0d06d 100644
--- a/include/dt-bindings/power/mt8192-power.h
+++ b/include/dt-bindings/power/mt8192-power.h
@@ -28,5 +28,6 @@
#define MT8192_POWER_DOMAIN_CAM_RAWA 18
#define MT8192_POWER_DOMAIN_CAM_RAWB 19
#define MT8192_POWER_DOMAIN_CAM_RAWC 20
+#define MT8192_POWER_DOMAIN_ADSP 21
#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
--
2.18.0
On 15/12/2022 13:00, Allen-KH Cheng wrote:
> Add power domain ID for the ADSP power partition found on MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> include/dt-bindings/power/mt8192-power.h | 1 +
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 15/12/2022 13:00, Allen-KH Cheng wrote:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
> index b97b2051920f..19e58f0ca1df 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> + [MT8192_POWER_DOMAIN_ADSP] = {
> + .name = "adsp",
> + .sta_mask = BIT(22),
> + .ctl_offs = 0x0358,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .ext_buck_iso_offs = 0x039C,
> + .ext_buck_iso_mask = BIT(2),
Not defined in upstream. It seems we are missing something here.
Regards,
Matthias
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
> + },
> [MT8192_POWER_DOMAIN_CAM] = {
> .name = "cam",
> .sta_mask = BIT(23),
Hi Matthias,
Thanks for the reminder. I will check this and resend next version.
Best Regards,
Allen
-----Original Message-----
From: Matthias Brugger <[email protected]>
Sent: Friday, December 16, 2022 7:16 PM
To: Allen-KH Cheng (程冠勳) <[email protected]>; Rob Herring <
[email protected]>; Krzysztof Kozlowski <
[email protected]>; Chun-Jie Chen (陳浚桀) <
[email protected]>; Stephen Boyd <[email protected]>; Ikjoon
Jang <[email protected]>
Cc: Project_Global_Chrome_Upstream_Group <
[email protected]>;
[email protected]; [email protected];
[email protected]; [email protected];
[email protected]; Chen-Yu Tsai <[email protected]>
Subject: Re: [PATCH 2/4] soc: mediatek: pm-domains: Add ADSP power
domain data for MT8192
On 15/12/2022 13:00, Allen-KH Cheng wrote:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h
> b/drivers/soc/mediatek/mt8192-pm-domains.h
> index b97b2051920f..19e58f0ca1df 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -287,6 +287,22 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8192[] = {
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> + [MT8192_POWER_DOMAIN_ADSP] = {
> + .name = "adsp",
> + .sta_mask = BIT(22),
> + .ctl_offs = 0x0358,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .ext_buck_iso_offs = 0x039C,
> + .ext_buck_iso_mask = BIT(2),
Not defined in upstream. It seems we are missing something here.
Regards,
Matthias
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
> + },
> [MT8192_POWER_DOMAIN_CAM] = {
> .name = "cam",
> .sta_mask = BIT(23),