Add the rtc block on pm8450a first pmic to enable the rtc for
sa8540p-ride.
Signed-off-by: Eric Chanudet <[email protected]>
---
arch/arm64/boot/dts/qcom/pm8450a.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
index 34fc72896761..c9b8da43b237 100644
--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
@@ -13,6 +13,14 @@ pm8450a: pmic@0 {
#address-cells = <1>;
#size-cells = <0>;
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ };
+
pm8450a_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
--
2.38.1
Include the dtsi to use a single pmic descriptions.
Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently.
Signed-off-by: Eric Chanudet <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +-----------------------
1 file changed, 1 insertion(+), 78 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 84cb6f3eeb56..889259df3287 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/spmi/spmi.h>
#include "sa8540p.dtsi"
+#include "pm8450a.dtsi"
/ {
model = "Qualcomm SA8295P ADP";
@@ -260,84 +261,6 @@ &remoteproc_nsp1 {
status = "okay";
};
-&spmi_bus {
- pm8450a: pmic@0 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@6000 {
- compatible = "qcom,pm8941-rtc";
- reg = <0x6000>;
- reg-names = "rtc", "alarm";
- interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
- wakeup-source;
- };
-
- pm8450a_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450a_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450c: pmic@4 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x4 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450c_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450c_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450e: pmic@8 {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0x8 SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450e_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450e_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- pm8450g: pmic@c {
- compatible = "qcom,pm8150", "qcom,spmi-pmic";
- reg = <0xc SPMI_USID>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8450g_gpios: gpio@c000 {
- compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8450g_gpios 0 0 10>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
--
2.38.1
On 14.12.2022 22:09, Eric Chanudet wrote:
> Add the rtc block on pm8450a first pmic to enable the rtc for
> sa8540p-ride.
>
> Signed-off-by: Eric Chanudet <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/pm8450a.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> index 34fc72896761..c9b8da43b237 100644
> --- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
> @@ -13,6 +13,14 @@ pm8450a: pmic@0 {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + rtc@6000 {
> + compatible = "qcom,pm8941-rtc";
> + reg = <0x6000>, <0x6100>;
> + reg-names = "rtc", "alarm";
> + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> + wakeup-source;
> + };
> +
> pm8450a_gpios: gpio@c000 {
> compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> reg = <0xc000>;
On 14.12.2022 22:09, Eric Chanudet wrote:
> Include the dtsi to use a single pmic descriptions.
> Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently.
>
> Signed-off-by: Eric Chanudet <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +-----------------------
> 1 file changed, 1 insertion(+), 78 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index 84cb6f3eeb56..889259df3287 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -11,6 +11,7 @@
> #include <dt-bindings/spmi/spmi.h>
>
> #include "sa8540p.dtsi"
> +#include "pm8450a.dtsi"
I feel like naming it sa8540p-pmics.dtsi (like sc8280xp-pmics.dtsi)
would be more representative of what's really going on (unless it's
a single chip providing 4 virtual PMICs on different SIDs).
Konrad
>
> / {
> model = "Qualcomm SA8295P ADP";
> @@ -260,84 +261,6 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> -&spmi_bus {
> - pm8450a: pmic@0 {
> - compatible = "qcom,pm8150", "qcom,spmi-pmic";
> - reg = <0x0 SPMI_USID>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - rtc@6000 {
> - compatible = "qcom,pm8941-rtc";
> - reg = <0x6000>;
> - reg-names = "rtc", "alarm";
> - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> - wakeup-source;
> - };
> -
> - pm8450a_gpios: gpio@c000 {
> - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> - reg = <0xc000>;
> - gpio-controller;
> - gpio-ranges = <&pm8450a_gpios 0 0 10>;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> - };
> -
> - pm8450c: pmic@4 {
> - compatible = "qcom,pm8150", "qcom,spmi-pmic";
> - reg = <0x4 SPMI_USID>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - pm8450c_gpios: gpio@c000 {
> - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> - reg = <0xc000>;
> - gpio-controller;
> - gpio-ranges = <&pm8450c_gpios 0 0 10>;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> - };
> -
> - pm8450e: pmic@8 {
> - compatible = "qcom,pm8150", "qcom,spmi-pmic";
> - reg = <0x8 SPMI_USID>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - pm8450e_gpios: gpio@c000 {
> - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> - reg = <0xc000>;
> - gpio-controller;
> - gpio-ranges = <&pm8450e_gpios 0 0 10>;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> - };
> -
> - pm8450g: pmic@c {
> - compatible = "qcom,pm8150", "qcom,spmi-pmic";
> - reg = <0xc SPMI_USID>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - pm8450g_gpios: gpio@c000 {
> - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
> - reg = <0xc000>;
> - gpio-controller;
> - gpio-ranges = <&pm8450g_gpios 0 0 10>;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> - };
> -};
> -
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
On Thu, Dec 15, 2022 at 02:01:09PM +0100, Konrad Dybcio wrote:
> On 14.12.2022 22:09, Eric Chanudet wrote:
> > Include the dtsi to use a single pmic descriptions.
> > Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently.
> >
> > Signed-off-by: Eric Chanudet <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +-----------------------
> > 1 file changed, 1 insertion(+), 78 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > index 84cb6f3eeb56..889259df3287 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > @@ -11,6 +11,7 @@
> > #include <dt-bindings/spmi/spmi.h>
> >
> > #include "sa8540p.dtsi"
> > +#include "pm8450a.dtsi"
> I feel like naming it sa8540p-pmics.dtsi (like sc8280xp-pmics.dtsi)
> would be more representative of what's really going on (unless it's
> a single chip providing 4 virtual PMICs on different SIDs).
I can make a v3 renaming this. The initial commit from Parikshit
mentions it is to be re-used on sa8540 based boards.
Side note: A quick look also shows pm8450.dtsi[1] is not included by
any of its intended targets (sm8350 and sm8450 IIUC). Was this lost?
Thanks,
[1] https://lore.kernel.org/r/[email protected]
--
Eric Chanudet
On 16.12.2022 20:56, Eric Chanudet wrote:
> On Thu, Dec 15, 2022 at 02:01:09PM +0100, Konrad Dybcio wrote:
>> On 14.12.2022 22:09, Eric Chanudet wrote:
>>> Include the dtsi to use a single pmic descriptions.
>>> Both sa8295p-adp and sa8540p-adp have the same spmi pmic apparently.
>>>
>>> Signed-off-by: Eric Chanudet <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +-----------------------
>>> 1 file changed, 1 insertion(+), 78 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> index 84cb6f3eeb56..889259df3287 100644
>>> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> @@ -11,6 +11,7 @@
>>> #include <dt-bindings/spmi/spmi.h>
>>>
>>> #include "sa8540p.dtsi"
>>> +#include "pm8450a.dtsi"
>> I feel like naming it sa8540p-pmics.dtsi (like sc8280xp-pmics.dtsi)
>> would be more representative of what's really going on (unless it's
>> a single chip providing 4 virtual PMICs on different SIDs).
>
> I can make a v3 renaming this. The initial commit from Parikshit
> mentions it is to be re-used on sa8540 based boards.
>
> Side note: A quick look also shows pm8450.dtsi[1] is not included by
> any of its intended targets (sm8350 and sm8450 IIUC). Was this lost?
sm8450 only. They were not included, as SPMI was not enabled on sm8450.
They will be included in 6.3 once that's merged.
Konrad
>
> Thanks,
>
> [1] https://lore.kernel.org/r/[email protected]
>