Use macros for 64-bit operations. This allows compile-testing this
driver on 32-bit arches, so enable it.
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/gpu/drm/hisilicon/kirin/Kconfig | 2 +-
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index c5265675bf0c..0772f79567ef 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config DRM_HISI_KIRIN
tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
- depends on DRM && OF && ARM64
+ depends on DRM && OF && (ARM64 || COMPILE_TEST)
select DRM_KMS_HELPER
select DRM_GEM_DMA_HELPER
select DRM_MIPI_DSI
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
index d9978b79828c..1cfeffefd4b4 100644
--- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
- m_n_int = temp / (u64)1000000000;
- m_n = (temp % (u64)1000000000) / (u64)100000000;
+ m_n_int = div_u64_rem(temp, 1000000000, &m_n);
+ m_n /= 100000000;
if (m_n_int % 2 == 0) {
if (m_n * 6 >= 50) {
@@ -229,8 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
phy->pll_fbd_div5f = 1;
}
- f_kHz = (u64)1000000000 * (u64)m_pll /
- ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
+ f_kHz = div64_u64((u64)1000000000 * (u64)m_pll,
+ (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
if (f_kHz >= req_kHz)
break;
@@ -490,7 +490,7 @@ static void dsi_set_mode_timing(void __iomem *base,
hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
tmp = (u64)htot * (u64)lane_byte_clk_kHz;
- hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
+ hline_time = DIV64_U64_ROUND_UP(tmp, pixel_clk_kHz);
/* all specified in byte-lane clocks */
writel(hsa_time, base + VID_HSA_TIME);
--
2.35.1.1320.gc452695387.dirty
Hi Sean,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes linus/master v6.1 next-20221220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sean-Anderson/drm-kirin-Enable-COMPILE_TEST/20221223-053621
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20221222213426.1858941-1-sean.anderson%40seco.com
patch subject: [PATCH] drm: kirin: Enable COMPILE_TEST
config: powerpc-allyesconfig
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project f5700e7b69048de958172fb513b336564e7f8709)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/f03f2c25aa69e3d409b5ad4da0fd49fe21958ef0
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sean-Anderson/drm-kirin-Enable-COMPILE_TEST/20221223-053621
git checkout f03f2c25aa69e3d409b5ad4da0fd49fe21958ef0
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/gpu/drm/hisilicon/kirin/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c:128:9: warning: shift count >= width of type [-Wshift-count-overflow]
writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
^~~~~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h:13:21: note: expanded from macro 'MASK'
#define MASK(x) (BIT(x) - 1)
^~~~~~
include/vdso/bits.h:7:26: note: expanded from macro 'BIT'
#define BIT(nr) (UL(1) << (nr))
^ ~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c:129:9: warning: shift count >= width of type [-Wshift-count-overflow]
writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
^~~~~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h:13:21: note: expanded from macro 'MASK'
#define MASK(x) (BIT(x) - 1)
^~~~~~
include/vdso/bits.h:7:26: note: expanded from macro 'BIT'
#define BIT(nr) (UL(1) << (nr))
^ ~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c:130:9: warning: shift count >= width of type [-Wshift-count-overflow]
writel(MASK(32), base + ADE_RELOAD_DIS(0));
^~~~~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h:13:21: note: expanded from macro 'MASK'
#define MASK(x) (BIT(x) - 1)
^~~~~~
include/vdso/bits.h:7:26: note: expanded from macro 'BIT'
#define BIT(nr) (UL(1) << (nr))
^ ~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c:131:9: warning: shift count >= width of type [-Wshift-count-overflow]
writel(MASK(32), base + ADE_RELOAD_DIS(1));
^~~~~~~~
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h:13:21: note: expanded from macro 'MASK'
#define MASK(x) (BIT(x) - 1)
^~~~~~
include/vdso/bits.h:7:26: note: expanded from macro 'BIT'
#define BIT(nr) (UL(1) << (nr))
^ ~~~~
4 warnings generated.
vim +128 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
783ad972c9a0e46 Xinliang Liu 2015-10-10 115
783ad972c9a0e46 Xinliang Liu 2015-10-10 116 static void ade_init(struct ade_hw_ctx *ctx)
783ad972c9a0e46 Xinliang Liu 2015-10-10 117 {
783ad972c9a0e46 Xinliang Liu 2015-10-10 118 void __iomem *base = ctx->base;
783ad972c9a0e46 Xinliang Liu 2015-10-10 119
783ad972c9a0e46 Xinliang Liu 2015-10-10 120 /* enable clk gate */
783ad972c9a0e46 Xinliang Liu 2015-10-10 121 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
783ad972c9a0e46 Xinliang Liu 2015-10-10 122 AUTO_CLK_GATE_EN, ADE_ENABLE);
783ad972c9a0e46 Xinliang Liu 2015-10-10 123 /* clear overlay */
783ad972c9a0e46 Xinliang Liu 2015-10-10 124 writel(0, base + ADE_OVLY1_TRANS_CFG);
783ad972c9a0e46 Xinliang Liu 2015-10-10 125 writel(0, base + ADE_OVLY_CTL);
d3c9a7385f1924c Xinliang Liu 2015-10-10 126 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
783ad972c9a0e46 Xinliang Liu 2015-10-10 127 /* clear reset and reload regs */
783ad972c9a0e46 Xinliang Liu 2015-10-10 @128 writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
783ad972c9a0e46 Xinliang Liu 2015-10-10 129 writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
783ad972c9a0e46 Xinliang Liu 2015-10-10 130 writel(MASK(32), base + ADE_RELOAD_DIS(0));
783ad972c9a0e46 Xinliang Liu 2015-10-10 131 writel(MASK(32), base + ADE_RELOAD_DIS(1));
783ad972c9a0e46 Xinliang Liu 2015-10-10 132 /*
783ad972c9a0e46 Xinliang Liu 2015-10-10 133 * for video mode, all the ade registers should
783ad972c9a0e46 Xinliang Liu 2015-10-10 134 * become effective at frame end.
783ad972c9a0e46 Xinliang Liu 2015-10-10 135 */
783ad972c9a0e46 Xinliang Liu 2015-10-10 136 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
783ad972c9a0e46 Xinliang Liu 2015-10-10 137 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
783ad972c9a0e46 Xinliang Liu 2015-10-10 138 }
783ad972c9a0e46 Xinliang Liu 2015-10-10 139
--
0-DAY CI Kernel Test Service
https://01.org/lkp