Hello,
This series adds GIC-ITS support to SM8450 PCIe controllers for signalling
the MSIs received from endpoint devices to the CPU cores.
The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.
This series has been tested on SM8450 based dev board that works using an
out-of-tree dts where the MSIs from endpoint devices are distributed across
the CPU cores.
Thanks,
Mani
Changes in v2:
* Reworded the commit messages as per Lorenzo's comments
* Rebased on top of v6.2-rc1
Changes in v2:
* Swapped the Device ID for PCIe0 as it causes same issue as PCIe1
* Removed the definition of msi-map and msi-map-mask from binding
* Added Ack from Krzysztof
Manivannan Sadhasivam (3):
dt-bindings: PCI: qcom: Update maintainers
dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1
.../devicetree/bindings/pci/qcom,pcie.yaml | 14 +++++++++----
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++++++------
2 files changed, 24 insertions(+), 10 deletions(-)
--
2.25.1
Stanimir has left mm-sol and already expressed his wish to not continue
maintaining the PCIe RC driver. So his entry can be removed.
Adding myself as the co-maintainer since I took over the PCIe RC driver
maintainership from Stanimir.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a5859bb3dc28..a3639920fcbb 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex
maintainers:
- Bjorn Andersson <[email protected]>
- - Stanimir Varbanov <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
description: |
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
--
2.25.1
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.
Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the
msi-map-mask of 0xff00, all the 32 devices under these two busses can
share the same Device ID.
The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.
It should be noted that the MSIs for BDF (1:0.0) only works with Device
ID of 0x5980 and 0x5a00. Hence, the IDs are swapped.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 570475040d95..c4dd5838fac6 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1733,9 +1733,13 @@ pcie0: pci@1c00000 {
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
+ /*
+ * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
+ * Hence, the IDs are swapped.
+ */
+ msi-map = <0x0 &gic_its 0x5981 0x1>,
+ <0x100 &gic_its 0x5980 0x1>;
+ msi-map-mask = <0xff00>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
@@ -1842,9 +1846,13 @@ pcie1: pci@1c08000 {
ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
+ /*
+ * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
+ * Hence, the IDs are swapped.
+ */
+ msi-map = <0x0 &gic_its 0x5a01 0x1>,
+ <0x100 &gic_its 0x5a00 0x1>;
+ msi-map-mask = <0xff00>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
--
2.25.1
The Qcom PCIe controller is capable of using either internal MSI controller
or the external GIC-ITS for signaling MSIs sent by endpoint devices.
Currently, the binding only documents the internal MSI implementation.
Let's document the GIC-ITS imeplementation by making use of msi-map and
msi-map-mask properties. Only one of the implementation should be used
at a time.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a3639920fcbb..01208450e05c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -114,14 +114,20 @@ required:
- compatible
- reg
- reg-names
- - interrupts
- - interrupt-names
- - "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- clocks
- clock-names
+oneOf:
+ - required:
+ - interrupts
+ - interrupt-names
+ - "#interrupt-cells"
+ - required:
+ - msi-map
+ - msi-map-mask
+
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- if:
--
2.25.1
On 2.01.2023 11:58, Manivannan Sadhasivam wrote:
> Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
> received from endpoint devices to the CPU using GIC-ITS MSI controller.
> Add support for it.
>
> Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the
> msi-map-mask of 0xff00, all the 32 devices under these two busses can
> share the same Device ID.
>
> The GIC-ITS MSI implementation provides an advantage over internal MSI
> implementation using Locality-specific Peripheral Interrupts (LPI) that
> would allow MSIs to be targeted for each CPU core.
>
> It should be noted that the MSIs for BDF (1:0.0) only works with Device
> ID of 0x5980 and 0x5a00. Hence, the IDs are swapped.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
Tested-by: Konrad Dybcio <[email protected]> # Xperia 1 IV (WCN6855)
Konrad
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 570475040d95..c4dd5838fac6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -1733,9 +1733,13 @@ pcie0: pci@1c00000 {
> ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
>
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> - #interrupt-cells = <1>;
> + /*
> + * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
> + * Hence, the IDs are swapped.
> + */
> + msi-map = <0x0 &gic_its 0x5981 0x1>,
> + <0x100 &gic_its 0x5980 0x1>;
> + msi-map-mask = <0xff00>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> @@ -1842,9 +1846,13 @@ pcie1: pci@1c08000 {
> ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
> <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> - #interrupt-cells = <1>;
> + /*
> + * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
> + * Hence, the IDs are swapped.
> + */
> + msi-map = <0x0 &gic_its 0x5a01 0x1>,
> + <0x100 &gic_its 0x5a00 0x1>;
> + msi-map-mask = <0xff00>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
On Mon, Jan 02, 2023 at 04:28:19PM +0530, Manivannan Sadhasivam wrote:
> Stanimir has left mm-sol and already expressed his wish to not continue
> maintaining the PCIe RC driver. So his entry can be removed.
>
> Adding myself as the co-maintainer since I took over the PCIe RC driver
> maintainership from Stanimir.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
Acked-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index a5859bb3dc28..a3639920fcbb 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex
>
> maintainers:
> - Bjorn Andersson <[email protected]>
> - - Stanimir Varbanov <[email protected]>
> + - Manivannan Sadhasivam <[email protected]>
>
> description: |
> Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
> --
> 2.25.1
>
On Mon, Jan 02, 2023 at 04:28:20PM +0530, Manivannan Sadhasivam wrote:
> The Qcom PCIe controller is capable of using either internal MSI controller
> or the external GIC-ITS for signaling MSIs sent by endpoint devices.
> Currently, the binding only documents the internal MSI implementation.
>
> Let's document the GIC-ITS imeplementation by making use of msi-map and
> msi-map-mask properties. Only one of the implementation should be used
> at a time.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index a3639920fcbb..01208450e05c 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -114,14 +114,20 @@ required:
> - compatible
> - reg
> - reg-names
> - - interrupts
> - - interrupt-names
> - - "#interrupt-cells"
> - interrupt-map-mask
> - interrupt-map
> - clocks
> - clock-names
>
> +oneOf:
anyOf
The OS should have the option of both being present and pick which MSI
path it wants to use.
Rob
On Mon, 2 Jan 2023 16:28:18 +0530, Manivannan Sadhasivam wrote:
> This series adds GIC-ITS support to SM8450 PCIe controllers for signalling
> the MSIs received from endpoint devices to the CPU cores.
>
> The GIC-ITS MSI implementation provides an advantage over internal MSI
> implementation using Locality-specific Peripheral Interrupts (LPI) that
> would allow MSIs to be targeted for each CPU core.
>
> [...]
Applied, thanks!
[3/3] arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1
commit: ff384ab56f164ef14bcc5f2bd79e995b4dea4bf3
Best regards,
--
Bjorn Andersson <[email protected]>
On Sun, Jan 08, 2023 at 02:33:40PM -0600, Rob Herring wrote:
> On Mon, Jan 02, 2023 at 04:28:20PM +0530, Manivannan Sadhasivam wrote:
> > The Qcom PCIe controller is capable of using either internal MSI controller
> > or the external GIC-ITS for signaling MSIs sent by endpoint devices.
> > Currently, the binding only documents the internal MSI implementation.
> >
> > Let's document the GIC-ITS imeplementation by making use of msi-map and
> > msi-map-mask properties. Only one of the implementation should be used
> > at a time.
> >
> > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > ---
> > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++---
> > 1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index a3639920fcbb..01208450e05c 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -114,14 +114,20 @@ required:
> > - compatible
> > - reg
> > - reg-names
> > - - interrupts
> > - - interrupt-names
> > - - "#interrupt-cells"
> > - interrupt-map-mask
> > - interrupt-map
> > - clocks
> > - clock-names
> >
> > +oneOf:
>
> anyOf
>
> The OS should have the option of both being present and pick which MSI
> path it wants to use.
>
Makes sense. Given that the current series merged by Bjorn, I'll send a
follow-up patch.
Thanks,
Mani
> Rob
--
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