Hi,
This series adds support for audio using the QMC controller
available in some Freescale PowerQUICC SoCs.
This series contains three parts in order to show the different
blocks hierarchy and their usage in this support.
The first one is related to TSA (Time Slot Assigner).
The TSA handles the data present at the pin level (TDM with up
to 64 time slots) and dispatchs them to one or more serial
controller (SCC).
The second is related to QMC (QUICC Multichannel Controller).
The QMC handles the data at the serial controller (SCC) level
and splits again the data to creates some virtual channels.
The last one is related to the audio component (QMC audio).
It is the glue between the QMC controller and the ASoC
component. It handles one or more QMC virtual channels and
creates one DAI per QMC virtual channels handled.
Compared to the v2 series, this v3 series mainly:
- adds modification in the DT bindings,
- uses generic io{read,write}be{16,32} for registers
accesses instead of the specific PowerPC ones.
- updates some commit subjects and logs (CPM1 SoCs supports).
Best regards,
Herve Codina
Changes v2 -> v3
- All bindings
Rename fsl-tsa.h to fsl,tsa.h
Add missing vendor prefix
Various fixes (quotes, node names, upper/lower case)
- patches 1 and 2 (TSA binding specific)
Remove 'reserved' values in the routing tables
Remove fsl,grant-mode
Add a better description for 'fsl,common-rxtx-pins'
Fix clocks/clocks-name handling against fsl,common-rxtx-pins
Add information related to the delays unit
Removed FSL_CPM_TSA_NBCELL
Fix license in binding header file fsl,tsa.h
- patches 5 and 6 (QMC binding specific)
Remove fsl,cpm-command property
Add interrupt property constraint
- patches 8 and 9 (QMC audio binding specific)
Remove 'items' in compatible property definition
Add missing 'dai-common.yaml' reference
Fix the qmc_chan phandle definition
- patch 2 and 6
Use io{read,write}be{32,16}
Change commit subjects and logs
- patch 4
Add 'Acked-by: Christophe Leroy <[email protected]>'
Changes v1 -> v2:
- patch 2 and 6
Fix kernel test robot errors
- other patches
No changes
Herve Codina (10):
dt-bindings: soc: fsl: cpm_qe: Add TSA controller
soc: fsl: cpm1: Add support for TSA
MAINTAINERS: add the Freescale TSA controller entry
powerpc/8xx: Use a larger CPM1 command check mask
dt-bindings: soc: fsl: cpm_qe: Add QMC controller
soc: fsl: cmp1: Add support for QMC
MAINTAINERS: add the Freescale QMC controller entry
dt-bindings: sound: Add support for QMC audio
ASoC: fsl: Add support for QMC audio
MAINTAINERS: add the Freescale QMC audio entry
.../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++
.../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 +++
.../bindings/sound/fsl,qmc-audio.yaml | 117 ++
MAINTAINERS | 25 +
arch/powerpc/platforms/8xx/cpm1.c | 2 +-
drivers/soc/fsl/qe/Kconfig | 23 +
drivers/soc/fsl/qe/Makefile | 2 +
drivers/soc/fsl/qe/qmc.c | 1531 +++++++++++++++++
drivers/soc/fsl/qe/tsa.c | 810 +++++++++
drivers/soc/fsl/qe/tsa.h | 43 +
include/dt-bindings/soc/fsl,tsa.h | 13 +
include/soc/fsl/qe/qmc.h | 71 +
sound/soc/fsl/Kconfig | 9 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/fsl_qmc_audio.c | 732 ++++++++
15 files changed, 3803 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
create mode 100644 drivers/soc/fsl/qe/qmc.c
create mode 100644 drivers/soc/fsl/qe/tsa.c
create mode 100644 drivers/soc/fsl/qe/tsa.h
create mode 100644 include/dt-bindings/soc/fsl,tsa.h
create mode 100644 include/soc/fsl/qe/qmc.h
create mode 100644 sound/soc/fsl/fsl_qmc_audio.c
--
2.38.1
The QMC (QUICC mutichannel controller) is a controller
present in some PowerQUICC SoC such as MPC885.
The QMC audio is an ASoC component that uses the QMC
controller to transfer the audio data.
Signed-off-by: Herve Codina <[email protected]>
---
.../bindings/sound/fsl,qmc-audio.yaml | 117 ++++++++++++++++++
1 file changed, 117 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
diff --git a/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
new file mode 100644
index 000000000000..ff5cd9241941
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QMC audio
+
+maintainers:
+ - Herve Codina <[email protected]>
+
+description: |
+ The QMC audio is an ASoC component which uses QMC (QUICC Multichannel
+ Controller) channels to transfer the audio data.
+ It provides as many DAI as the number of QMC channel used.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: fsl,qmc-audio
+
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ '#sound-dai-cells':
+ const: 1
+
+patternProperties:
+ '^dai@([0-9]|[1-5][0-9]|6[0-3])$':
+ description:
+ A DAI managed by this controller
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 63
+ description:
+ The DAI number
+
+ fsl,qmc-chan:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to QMC node
+ - description: Channel number
+ description:
+ Should be a phandle/number pair. The phandle to QMC node and the QMC
+ channel to use for this DAI.
+
+ required:
+ - reg
+ - fsl,qmc-chan
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ audio_controller: audio-controller {
+ compatible = "fsl,qmc-audio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ dai@16 {
+ reg = <16>;
+ fsl,qmc-chan = <&qmc 16>;
+ };
+ dai@17 {
+ reg = <17>;
+ fsl,qmc-chan = <&qmc 17>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ simple-audio-card,dai-link@0 {
+ reg = <0>;
+ format = "dsp_b";
+ cpu {
+ sound-dai = <&audio_controller 16>;
+ };
+ codec {
+ sound-dai = <&codec1>;
+ dai-tdm-slot-num = <4>;
+ dai-tdm-slot-width = <8>;
+ /* TS 3, 5, 7, 9 */
+ dai-tdm-slot-tx-mask = <0 0 0 1 0 1 0 1 0 1>;
+ dai-tdm-slot-rx-mask = <0 0 0 1 0 1 0 1 0 1>;
+ };
+ };
+ simple-audio-card,dai-link@1 {
+ reg = <1>;
+ format = "dsp_b";
+ cpu {
+ sound-dai = <&audio_controller 17>;
+ };
+ codec {
+ sound-dai = <&codec2>;
+ dai-tdm-slot-num = <4>;
+ dai-tdm-slot-width = <8>;
+ /* TS 2, 4, 6, 8 */
+ dai-tdm-slot-tx-mask = <0 0 1 0 1 0 1 0 1>;
+ dai-tdm-slot-rx-mask = <0 0 1 0 1 0 1 0 1>;
+ };
+ };
+ };
--
2.38.1
After contributing the component, add myself as the maintainer
for the Freescale QMC audio ASoC component.
Signed-off-by: Herve Codina <[email protected]>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9a574892b9b1..9dcfadec5aa3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8440,6 +8440,14 @@ F: sound/soc/fsl/fsl*
F: sound/soc/fsl/imx*
F: sound/soc/fsl/mpc8610_hpcd.c
+FREESCALE SOC SOUND QMC DRIVER
+M: Herve Codina <[email protected]>
+L: [email protected] (moderated for non-subscribers)
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
+F: sound/soc/fsl/fsl_qmc_audio.c
+
FREESCALE USB PERIPHERAL DRIVERS
M: Li Yang <[email protected]>
L: [email protected]
--
2.38.1
After contributing the driver, add myself as the maintainer
for the Freescale QMC controller.
Signed-off-by: Herve Codina <[email protected]>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6a0605ebf8a0..9a574892b9b1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8372,6 +8372,14 @@ S: Maintained
F: drivers/soc/fsl/qe/
F: include/soc/fsl/qe/
+FREESCALE QUICC ENGINE QMC DRIVER
+M: Herve Codina <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
+F: drivers/soc/fsl/qe/qmc.c
+F: include/soc/fsl/qe/qmc.h
+
FREESCALE QUICC ENGINE TSA DRIVER
M: Herve Codina <[email protected]>
L: [email protected]
--
2.38.1
The TSA (Time Slot Assigner) purpose is to route some
TDM time-slots to other internal serial controllers.
It is available in some PowerQUICC SoC such as the
MPC885 or MPC866.
It is also available on some Quicc Engine SoCs.
This current version support CPM1 SoCs only and some
enhancement are needed to support Quicc Engine SoCs.
Signed-off-by: Herve Codina <[email protected]>
---
drivers/soc/fsl/qe/Kconfig | 11 +
drivers/soc/fsl/qe/Makefile | 1 +
drivers/soc/fsl/qe/tsa.c | 810 ++++++++++++++++++++++++++++++++++++
drivers/soc/fsl/qe/tsa.h | 43 ++
4 files changed, 865 insertions(+)
create mode 100644 drivers/soc/fsl/qe/tsa.c
create mode 100644 drivers/soc/fsl/qe/tsa.h
diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 357c5800b112..60ec11c9f4d9 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -33,6 +33,17 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
+config CPM_TSA
+ tristate "CPM TSA support"
+ depends on OF && HAS_IOMEM
+ depends on CPM1 || (PPC && COMPILE_TEST)
+ help
+ Freescale CPM Time Slot Assigner (TSA)
+ controller.
+
+ This option enables support for this
+ controller
+
config QE_TDM
bool
default y if FSL_UCC_HDLC
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 55a555304f3a..45c961acc81b 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
obj-$(CONFIG_CPM) += qe_common.o
+obj-$(CONFIG_CPM_TSA) += tsa.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
new file mode 100644
index 000000000000..58b574cf37e2
--- /dev/null
+++ b/drivers/soc/fsl/qe/tsa.c
@@ -0,0 +1,810 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TSA driver
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina <[email protected]>
+ */
+
+#include "tsa.h"
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* TSA SI RAM routing tables entry */
+#define TSA_SIRAM_ENTRY_LAST (1 << 16)
+#define TSA_SIRAM_ENTRY_BYTE (1 << 17)
+#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18)
+#define TSA_SIRAM_ENTRY_CSEL_MASK (0x7 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_NU (0x0 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC2 (0x2 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC3 (0x3 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC4 (0x4 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC1 (0x5 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC2 (0x6 << 22)
+
+/* SI mode register (32 bits) */
+#define TSA_SIMODE 0x00
+#define TSA_SIMODE_SMC2 0x80000000
+#define TSA_SIMODE_SMC1 0x00008000
+#define TSA_SIMODE_TDMA(x) ((x) << 0)
+#define TSA_SIMODE_TDMB(x) ((x) << 16)
+#define TSA_SIMODE_TDM_MASK 0x0fff
+#define TSA_SIMODE_TDM_SDM_MASK 0x0c00
+#define TSA_SIMODE_TDM_SDM_NORM 0x0000
+#define TSA_SIMODE_TDM_SDM_ECHO 0x0400
+#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800
+#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00
+#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8)
+#define TSA_SIMODE_TDM_DSC 0x0080
+#define TSA_SIMODE_TDM_CRT 0x0040
+#define TSA_SIMODE_TDM_STZ 0x0020
+#define TSA_SIMODE_TDM_CE 0x0010
+#define TSA_SIMODE_TDM_FE 0x0008
+#define TSA_SIMODE_TDM_GM 0x0004
+#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0)
+
+/* SI global mode register (8 bits) */
+#define TSA_SIGMR 0x04
+#define TSA_SIGMR_ENB (1<<3)
+#define TSA_SIGMR_ENA (1<<2)
+#define TSA_SIGMR_RDM_MASK 0x03
+#define TSA_SIGMR_RDM_STATIC_TDMA 0x00
+#define TSA_SIGMR_RDM_DYN_TDMA 0x01
+#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02
+#define TSA_SIGMR_RDM_DYN_TDMAB 0x03
+
+/* SI status register (8 bits) */
+#define TSA_SISTR 0x06
+
+/* SI command register (8 bits) */
+#define TSA_SICMR 0x07
+
+/* SI clock route register (32 bits) */
+#define TSA_SICR 0x0C
+#define TSA_SICR_SCC2(x) ((x) << 8)
+#define TSA_SICR_SCC3(x) ((x) << 16)
+#define TSA_SICR_SCC4(x) ((x) << 24)
+#define TSA_SICR_SCC_MASK 0x0ff
+#define TSA_SICR_SCC_GRX (1 << 7)
+#define TSA_SICR_SCC_SCX_TSA (1 << 6)
+#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3)
+#define TSA_SICR_SCC_RXCS_BRG1 (0x0 << 3)
+#define TSA_SICR_SCC_RXCS_BRG2 (0x1 << 3)
+#define TSA_SICR_SCC_RXCS_BRG3 (0x2 << 3)
+#define TSA_SICR_SCC_RXCS_BRG4 (0x3 << 3)
+#define TSA_SICR_SCC_RXCS_CLK15 (0x4 << 3)
+#define TSA_SICR_SCC_RXCS_CLK26 (0x5 << 3)
+#define TSA_SICR_SCC_RXCS_CLK37 (0x6 << 3)
+#define TSA_SICR_SCC_RXCS_CLK48 (0x7 << 3)
+#define TSA_SICR_SCC_TXCS_MASK (0x7 << 0)
+#define TSA_SICR_SCC_TXCS_BRG1 (0x0 << 0)
+#define TSA_SICR_SCC_TXCS_BRG2 (0x1 << 0)
+#define TSA_SICR_SCC_TXCS_BRG3 (0x2 << 0)
+#define TSA_SICR_SCC_TXCS_BRG4 (0x3 << 0)
+#define TSA_SICR_SCC_TXCS_CLK15 (0x4 << 0)
+#define TSA_SICR_SCC_TXCS_CLK26 (0x5 << 0)
+#define TSA_SICR_SCC_TXCS_CLK37 (0x6 << 0)
+#define TSA_SICR_SCC_TXCS_CLK48 (0x7 << 0)
+
+/* Serial interface RAM pointer register (32 bits) */
+#define TSA_SIRP 0x10
+
+struct tsa_entries_area {
+ void *__iomem entries_start;
+ void *__iomem entries_next;
+ void *__iomem last_entry;
+};
+
+struct tsa_tdm {
+ bool is_enable;
+ struct clk *l1rclk_clk;
+ struct clk *l1rsync_clk;
+ struct clk *l1tclk_clk;
+ struct clk *l1tsync_clk;
+ u32 simode_tdm;
+};
+
+#define TSA_TDMA 0
+#define TSA_TDMB 1
+
+struct tsa {
+ struct device *dev;
+ void *__iomem si_regs;
+ void *__iomem si_ram;
+ resource_size_t si_ram_sz;
+ int tdms; /* TSA_TDMx ORed */
+ struct tsa_tdm tdm[2]; /* TDMa and TDMb */
+ struct tsa_cell_info cell_infos[6];
+};
+
+static inline void tsa_write32(void *__iomem addr, u32 val)
+{
+ iowrite32be(val, addr);
+}
+
+static inline u32 tsa_read32(void *__iomem addr)
+{
+ return ioread32be(addr);
+}
+
+static inline void tsa_clrbits32(void *__iomem addr, u32 clr)
+{
+ tsa_write32(addr, tsa_read32(addr) & ~clr);
+}
+
+static inline void tsa_clrsetbits32(void *__iomem addr, u32 clr, u32 set)
+{
+ tsa_write32(addr, (tsa_read32(addr) & ~clr) | set);
+}
+
+int tsa_connect(struct tsa *tsa, unsigned int cell_index)
+{
+ u32 clear;
+ u32 set;
+
+ switch (cell_index) {
+ case FSL_CPM_TSA_SCC2:
+ clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK);
+ set = TSA_SICR_SCC2(TSA_SICR_SCC_SCX_TSA);
+ break;
+ case FSL_CPM_TSA_SCC3:
+ clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK);
+ set = TSA_SICR_SCC3(TSA_SICR_SCC_SCX_TSA);
+ break;
+ case FSL_CPM_TSA_SCC4:
+ clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK);
+ set = TSA_SICR_SCC4(TSA_SICR_SCC_SCX_TSA);
+ break;
+ default:
+ dev_err(tsa->dev, "Unsupported cell-index %u\n", cell_index);
+ return -EINVAL;
+ }
+
+ tsa_clrsetbits32(tsa->si_regs + TSA_SICR, clear, set);
+ return 0;
+}
+EXPORT_SYMBOL(tsa_connect);
+
+int tsa_disconnect(struct tsa *tsa, unsigned int cell_index)
+{
+ u32 clear;
+
+ switch (cell_index) {
+ case 2:
+ clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK);
+ break;
+ case 3:
+ clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK);
+ break;
+ case 4:
+ clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK);
+ break;
+ default:
+ dev_err(tsa->dev, "Unsupported cell-index %u\n", cell_index);
+ return -EINVAL;
+ }
+
+ tsa_clrsetbits32(tsa->si_regs + TSA_SICR, clear, 0);
+ return 0;
+}
+EXPORT_SYMBOL(tsa_disconnect);
+
+int tsa_get_info(struct tsa *tsa, unsigned int cell_id, struct tsa_cell_info *info)
+{
+ if (cell_id >= ARRAY_SIZE(tsa->cell_infos))
+ return -EINVAL;
+
+ memcpy(info, &tsa->cell_infos[cell_id], sizeof(*info));
+ return 0;
+}
+EXPORT_SYMBOL(tsa_get_info);
+
+static void tsa_init_entries_area(struct tsa *tsa, struct tsa_entries_area *area,
+ u32 tdms, u32 tdm_id, bool is_rx)
+{
+ resource_size_t quarter;
+ resource_size_t half;
+
+ quarter = tsa->si_ram_sz/4;
+ half = tsa->si_ram_sz/2;
+
+ if (tdms == BIT(TSA_TDMA)) {
+ /* Only TDMA */
+ if (is_rx) {
+ /* First half of si_ram */
+ area->entries_start = tsa->si_ram;
+ area->entries_next = area->entries_start + half;
+ area->last_entry = NULL;
+ } else {
+ /* Second half of si_ram */
+ area->entries_start = tsa->si_ram + half;
+ area->entries_next = area->entries_start + half;
+ area->last_entry = NULL;
+ }
+ } else {
+ /* Only TDMB or both TDMs */
+ if (tdm_id == TSA_TDMA) {
+ if (is_rx) {
+ /* First half of first half of si_ram */
+ area->entries_start = tsa->si_ram;
+ area->entries_next = area->entries_start + quarter;
+ area->last_entry = NULL;
+ } else {
+ /* First half of second half of si_ram */
+ area->entries_start = tsa->si_ram + (2 * quarter);
+ area->entries_next = area->entries_start + quarter;
+ area->last_entry = NULL;
+ }
+ } else {
+ if (is_rx) {
+ /* Second half of first half of si_ram */
+ area->entries_start = tsa->si_ram + quarter;
+ area->entries_next = area->entries_start + quarter;
+ area->last_entry = NULL;
+ } else {
+ /* Second half of second half of si_ram */
+ area->entries_start = tsa->si_ram + (3 * quarter);
+ area->entries_next = area->entries_start + quarter;
+ area->last_entry = NULL;
+ }
+ }
+ }
+}
+
+static const char *tsa_cell_id2name(struct tsa *tsa, u32 cell_id)
+{
+ switch (cell_id) {
+ case FSL_CPM_TSA_NU: return "Not used";
+ case FSL_CPM_TSA_SCC2: return "SCC2";
+ case FSL_CPM_TSA_SCC3: return "SCC3";
+ case FSL_CPM_TSA_SCC4: return "SCC4";
+ case FSL_CPM_TSA_SMC1: return "SMC1";
+ case FSL_CPM_TSA_SMC2: return "SMC2";
+ default:
+ break;
+ }
+ return NULL;
+}
+
+static u32 tsa_cell_id2csel(struct tsa *tsa, u32 cell_id)
+{
+ switch (cell_id) {
+ case FSL_CPM_TSA_SCC2: return TSA_SIRAM_ENTRY_CSEL_SCC2;
+ case FSL_CPM_TSA_SCC3: return TSA_SIRAM_ENTRY_CSEL_SCC3;
+ case FSL_CPM_TSA_SCC4: return TSA_SIRAM_ENTRY_CSEL_SCC4;
+ case FSL_CPM_TSA_SMC1: return TSA_SIRAM_ENTRY_CSEL_SMC1;
+ case FSL_CPM_TSA_SMC2: return TSA_SIRAM_ENTRY_CSEL_SMC2;
+ default:
+ break;
+ }
+ return TSA_SIRAM_ENTRY_CSEL_NU;
+}
+
+static int tsa_add_entry(struct tsa *tsa, struct tsa_entries_area *area,
+ u32 count, u32 cell_id)
+{
+ void *__iomem addr;
+ u32 left;
+ u32 val;
+ u32 cnt;
+ u32 nb;
+
+ addr = area->last_entry ? area->last_entry + 4 : area->entries_start;
+
+ nb = DIV_ROUND_UP(count, 8);
+ if ((addr + (nb * 4)) > area->entries_next) {
+ dev_err(tsa->dev, "si ram area full\n");
+ return -ENOSPC;
+ }
+
+ if (area->last_entry) {
+ /* Clear last flag */
+ tsa_clrbits32(area->last_entry, TSA_SIRAM_ENTRY_LAST);
+ }
+
+ left = count;
+ while (left) {
+ val = TSA_SIRAM_ENTRY_BYTE | tsa_cell_id2csel(tsa, cell_id);
+
+ if (left > 16) {
+ cnt = 16;
+ } else {
+ cnt = left;
+ val |= TSA_SIRAM_ENTRY_LAST;
+ area->last_entry = addr;
+ }
+ val |= TSA_SIRAM_ENTRY_CNT(cnt - 1);
+
+ tsa_write32(addr, val);
+ addr += 4;
+ left -= cnt;
+ }
+
+ return 0;
+}
+
+static int tsa_of_parse_tdm_route(struct tsa *tsa, struct device_node *tdm_np,
+ u32 tdms, u32 tdm_id, bool is_rx)
+{
+ struct tsa_entries_area area;
+ const char *route_name;
+ int len, i;
+ u32 count;
+ u32 cell_id;
+ const char *cell_name;
+ struct tsa_cell_info *cell_info;
+ struct tsa_tdm *tdm;
+ int ret;
+ u32 ts;
+
+ route_name = is_rx ? "fsl,rx-ts-routes" : "fsl,tx-ts-routes";
+
+ len = of_property_count_u32_elems(tdm_np, route_name);
+ if (len < 0) {
+ dev_err(tsa->dev, "%pOF: failed to read %s\n", tdm_np, route_name);
+ return len;
+ }
+ if (len % 2 != 0) {
+ dev_err(tsa->dev, "%pOF: wrong %s format\n", tdm_np, route_name);
+ return -EINVAL;
+ }
+
+ tsa_init_entries_area(tsa, &area, tdms, tdm_id, is_rx);
+ ts = 0;
+ for (i = 0; i < len; i += 2) {
+ of_property_read_u32_index(tdm_np, route_name, i, &count);
+ of_property_read_u32_index(tdm_np, route_name, i + 1, &cell_id);
+
+ if (cell_id >= ARRAY_SIZE(tsa->cell_infos)) {
+ dev_err(tsa->dev, "%pOF: invalid cell id (%u)\n", tdm_np,
+ cell_id);
+ return -EINVAL;
+ }
+
+ cell_name = tsa_cell_id2name(tsa, cell_id);
+ if (!cell_name) {
+ dev_err(tsa->dev, "%pOF: unsupported cell id (%u)\n", tdm_np,
+ cell_id);
+ return -EINVAL;
+ }
+
+ dev_dbg(tsa->dev, "tdm_id=%u, %s ts %u..%u -> %s\n",
+ tdm_id, route_name, ts, ts+count-1, cell_name);
+ ts += count;
+
+ ret = tsa_add_entry(tsa, &area, count, cell_id);
+ if (ret)
+ return ret;
+
+ cell_info = &tsa->cell_infos[cell_id];
+ tdm = &tsa->tdm[tdm_id];
+ if (is_rx) {
+ cell_info->rx_fs_rate = clk_get_rate(tdm->l1rsync_clk);
+ cell_info->rx_bit_rate = clk_get_rate(tdm->l1rclk_clk);
+ cell_info->nb_rx_ts += count;
+ } else {
+ cell_info->tx_fs_rate = tdm->l1tsync_clk ?
+ clk_get_rate(tdm->l1tsync_clk) :
+ clk_get_rate(tdm->l1rsync_clk);
+ cell_info->tx_bit_rate = tdm->l1tclk_clk ?
+ clk_get_rate(tdm->l1tclk_clk) :
+ clk_get_rate(tdm->l1rclk_clk);
+ cell_info->nb_tx_ts += count;
+ }
+ }
+ return 0;
+}
+
+static inline int tsa_of_parse_tdm_rx_route(struct tsa *tsa,
+ struct device_node *tdm_np,
+ u32 tdms, u32 tdm_id)
+{
+ return tsa_of_parse_tdm_route(tsa, tdm_np, tdms, tdm_id, true);
+}
+
+static inline int tsa_of_parse_tdm_tx_route(struct tsa *tsa,
+ struct device_node *tdm_np,
+ u32 tdms, u32 tdm_id)
+{
+ return tsa_of_parse_tdm_route(tsa, tdm_np, tdms, tdm_id, false);
+}
+
+static int tsa_of_parse_tdms(struct tsa *tsa, struct device_node *np)
+{
+ struct device_node *tdm_np;
+ struct tsa_tdm *tdm;
+ struct clk *clk;
+ const char *mode;
+ u32 tdm_id, val;
+ int ret;
+ int i;
+
+ tsa->tdms = 0;
+ tsa->tdm[0].is_enable = false;
+ tsa->tdm[1].is_enable = false;
+
+ for_each_available_child_of_node(np, tdm_np) {
+ ret = of_property_read_u32(tdm_np, "reg", &tdm_id);
+ if (ret) {
+ dev_err(tsa->dev, "%pOF: failed to read reg\n", tdm_np);
+ of_node_put(tdm_np);
+ return ret;
+ }
+ switch (tdm_id) {
+ case 0:
+ tsa->tdms |= BIT(TSA_TDMA);
+ break;
+ case 1:
+ tsa->tdms |= BIT(TSA_TDMB);
+ break;
+ default:
+ dev_err(tsa->dev, "%pOF: Invalid tdm_id (%u)\n", tdm_np,
+ tdm_id);
+ of_node_put(tdm_np);
+ return -EINVAL;
+ }
+ }
+
+ for_each_available_child_of_node(np, tdm_np) {
+ ret = of_property_read_u32(tdm_np, "reg", &tdm_id);
+ if (ret) {
+ dev_err(tsa->dev, "%pOF: failed to read reg\n", tdm_np);
+ of_node_put(tdm_np);
+ return ret;
+ }
+
+ tdm = &tsa->tdm[tdm_id];
+
+ mode = "normal";
+ ret = of_property_read_string(tdm_np, "fsl,mode", &mode);
+ if (ret && ret != -EINVAL) {
+ dev_err(tsa->dev, "%pOF: failed to read fsl,mode\n", tdm_np);
+ of_node_put(tdm_np);
+ return ret;
+ }
+ if (!strcmp(mode, "normal")) {
+ tdm->simode_tdm |= TSA_SIMODE_TDM_SDM_NORM;
+ } else if (!strcmp(mode, "echo")) {
+ tdm->simode_tdm |= TSA_SIMODE_TDM_SDM_ECHO;
+ } else if (!strcmp(mode, "internal-loopback")) {
+ tdm->simode_tdm |= TSA_SIMODE_TDM_SDM_INTL_LOOP;
+ } else if (!strcmp(mode, "control-loopback")) {
+ tdm->simode_tdm |= TSA_SIMODE_TDM_SDM_LOOP_CTRL;
+ } else {
+ dev_err(tsa->dev, "%pOF: Invalid fsl,mode (%s)\n", tdm_np,
+ mode);
+ of_node_put(tdm_np);
+ return -EINVAL;
+ }
+
+ val = 0;
+ ret = of_property_read_u32(tdm_np, "fsl,rx-frame-sync-delay-bits",
+ &val);
+ if (ret && ret != -EINVAL) {
+ dev_err(tsa->dev,
+ "%pOF: failed to read fsl,rx-frame-sync-delay-bits\n",
+ tdm_np);
+ of_node_put(tdm_np);
+ return ret;
+ }
+ if (val > 3) {
+ dev_err(tsa->dev,
+ "%pOF: Invalid fsl,rx-frame-sync-delay-bits (%u)\n",
+ tdm_np, val);
+ of_node_put(tdm_np);
+ return -EINVAL;
+ }
+ tdm->simode_tdm |= TSA_SIMODE_TDM_RFSD(val);
+
+ val = 0;
+ ret = of_property_read_u32(tdm_np, "fsl,tx-frame-sync-delay-bits",
+ &val);
+ if (ret && ret != -EINVAL) {
+ dev_err(tsa->dev,
+ "%pOF: failed to read fsl,tx-frame-sync-delay-bits\n",
+ tdm_np);
+ of_node_put(tdm_np);
+ return ret;
+ }
+ if (val > 3) {
+ dev_err(tsa->dev,
+ "%pOF: Invalid fsl,tx-frame-sync-delay-bits (%u)\n",
+ tdm_np, val);
+ of_node_put(tdm_np);
+ return -EINVAL;
+ }
+ tdm->simode_tdm |= TSA_SIMODE_TDM_TFSD(val);
+
+ if (of_property_read_bool(tdm_np, "fsl,common-rxtx-pins"))
+ tdm->simode_tdm |= TSA_SIMODE_TDM_CRT;
+
+ if (of_property_read_bool(tdm_np, "fsl,clock-falling-edge"))
+ tdm->simode_tdm |= TSA_SIMODE_TDM_CE;
+
+ if (of_property_read_bool(tdm_np, "fsl,fsync-rising-edge"))
+ tdm->simode_tdm |= TSA_SIMODE_TDM_FE;
+
+ if (of_property_read_bool(tdm_np, "fsl,double-speed-clock"))
+ tdm->simode_tdm |= TSA_SIMODE_TDM_DSC;
+
+ clk = of_clk_get_by_name(tdm_np, "l1rsync");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ clk_put(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ tdm->l1rsync_clk = clk;
+
+ clk = of_clk_get_by_name(tdm_np, "l1rclk");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ clk_put(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ tdm->l1rclk_clk = clk;
+
+ if (!(tdm->simode_tdm & TSA_SIMODE_TDM_CRT)) {
+ clk = of_clk_get_by_name(tdm_np, "l1tsync");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ clk_put(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ tdm->l1tsync_clk = clk;
+
+ clk = of_clk_get_by_name(tdm_np, "l1tclk");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ clk_put(clk);
+ of_node_put(tdm_np);
+ goto err;
+ }
+ tdm->l1tclk_clk = clk;
+ }
+
+ ret = tsa_of_parse_tdm_rx_route(tsa, tdm_np, tsa->tdms, tdm_id);
+ if (ret) {
+ of_node_put(tdm_np);
+ goto err;
+ }
+
+ ret = tsa_of_parse_tdm_tx_route(tsa, tdm_np, tsa->tdms, tdm_id);
+ if (ret) {
+ of_node_put(tdm_np);
+ goto err;
+ }
+
+ tdm->is_enable = true;
+ }
+ return 0;
+
+err:
+ for (i = 0; i < 2; i++) {
+ if (tsa->tdm[i].l1rsync_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rsync_clk);
+ clk_put(tsa->tdm[i].l1rsync_clk);
+ }
+ if (tsa->tdm[i].l1rclk_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rclk_clk);
+ clk_put(tsa->tdm[i].l1rclk_clk);
+ }
+ if (tsa->tdm[i].l1tsync_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rsync_clk);
+ clk_put(tsa->tdm[i].l1rsync_clk);
+ }
+ if (tsa->tdm[i].l1tclk_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rclk_clk);
+ clk_put(tsa->tdm[i].l1rclk_clk);
+ }
+ }
+ return ret;
+}
+
+static void tsa_init_si_ram(struct tsa *tsa)
+{
+ resource_size_t i;
+
+ /* Fill all entries as the last one */
+ for (i = 0; i < tsa->si_ram_sz; i += 4)
+ tsa_write32(tsa->si_ram + i, TSA_SIRAM_ENTRY_LAST);
+}
+
+static int tsa_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *res;
+ struct tsa *tsa;
+ u32 val;
+ int ret;
+
+ tsa = devm_kzalloc(&pdev->dev, sizeof(*tsa), GFP_KERNEL);
+ if (!tsa)
+ return -ENOMEM;
+
+ tsa->dev = &pdev->dev;
+
+ tsa->si_regs = devm_platform_ioremap_resource_byname(pdev, "si_regs");
+ if (IS_ERR(tsa->si_regs))
+ return PTR_ERR(tsa->si_regs);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "si_ram");
+ if (!res) {
+ dev_err(tsa->dev, "si_ram resource missing\n");
+ return -EINVAL;
+ }
+ tsa->si_ram_sz = resource_size(res);
+ tsa->si_ram = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tsa->si_ram))
+ return PTR_ERR(tsa->si_ram);
+
+ tsa_init_si_ram(tsa);
+
+ ret = tsa_of_parse_tdms(tsa, np);
+ if (ret)
+ return ret;
+
+ /* Set SIMODE */
+ val = 0;
+ if (tsa->tdm[0].is_enable)
+ val |= TSA_SIMODE_TDMA(tsa->tdm[0].simode_tdm);
+ if (tsa->tdm[1].is_enable)
+ val |= TSA_SIMODE_TDMB(tsa->tdm[1].simode_tdm);
+
+ tsa_clrsetbits32(tsa->si_regs + TSA_SIMODE,
+ TSA_SIMODE_TDMA(TSA_SIMODE_TDM_MASK) |
+ TSA_SIMODE_TDMB(TSA_SIMODE_TDM_MASK),
+ val);
+
+ /* Set SIGMR */
+ val = (tsa->tdms == BIT(TSA_TDMA)) ?
+ TSA_SIGMR_RDM_STATIC_TDMA : TSA_SIGMR_RDM_STATIC_TDMAB;
+ if (tsa->tdms & BIT(TSA_TDMA))
+ val |= TSA_SIGMR_ENA;
+ if (tsa->tdms & BIT(TSA_TDMB))
+ val |= TSA_SIGMR_ENB;
+ out_8(tsa->si_regs + TSA_SIGMR, val);
+
+ platform_set_drvdata(pdev, tsa);
+
+ return 0;
+}
+
+static int tsa_remove(struct platform_device *pdev)
+{
+ struct tsa *tsa = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ if (tsa->tdm[i].l1rsync_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rsync_clk);
+ clk_put(tsa->tdm[i].l1rsync_clk);
+ }
+ if (tsa->tdm[i].l1rclk_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rclk_clk);
+ clk_put(tsa->tdm[i].l1rclk_clk);
+ }
+ if (tsa->tdm[i].l1tsync_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rsync_clk);
+ clk_put(tsa->tdm[i].l1rsync_clk);
+ }
+ if (tsa->tdm[i].l1tclk_clk) {
+ clk_disable_unprepare(tsa->tdm[i].l1rclk_clk);
+ clk_put(tsa->tdm[i].l1rclk_clk);
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id tsa_id_table[] = {
+ { .compatible = "fsl,cpm1-tsa" },
+ {} /* sentinel */
+};
+MODULE_DEVICE_TABLE(of, tsa_id_table);
+
+static struct platform_driver tsa_driver = {
+ .driver = {
+ .name = "fsl-tsa",
+ .of_match_table = of_match_ptr(tsa_id_table),
+ },
+ .probe = tsa_probe,
+ .remove = tsa_remove,
+};
+module_platform_driver(tsa_driver);
+
+struct tsa *tsa_get_byphandle(struct device_node *np, const char *phandle_name)
+{
+ struct platform_device *pdev;
+ struct device_node *tsa_np;
+ struct tsa *tsa;
+
+ tsa_np = of_parse_phandle(np, phandle_name, 0);
+ if (!tsa_np)
+ return ERR_PTR(-EINVAL);
+
+ if (!of_match_node(tsa_driver.driver.of_match_table, tsa_np)) {
+ of_node_put(tsa_np);
+ return ERR_PTR(-EINVAL);
+ }
+
+ pdev = of_find_device_by_node(tsa_np);
+ of_node_put(tsa_np);
+ if (!pdev)
+ return ERR_PTR(-ENODEV);
+
+ tsa = platform_get_drvdata(pdev);
+ if (!tsa) {
+ platform_device_put(pdev);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ return tsa;
+}
+EXPORT_SYMBOL(tsa_get_byphandle);
+
+void tsa_put(struct tsa *tsa)
+{
+ put_device(tsa->dev);
+}
+EXPORT_SYMBOL(tsa_put);
+
+static void devm_tsa_release(struct device *dev, void *res)
+{
+ struct tsa **tsa = res;
+
+ tsa_put(*tsa);
+}
+
+struct tsa *devm_tsa_get_byphandle(struct device *dev, struct device_node *np,
+ const char *phandle_name)
+{
+ struct tsa *tsa;
+ struct tsa **dr;
+
+ dr = devres_alloc(devm_tsa_release, sizeof(*dr), GFP_KERNEL);
+ if (!dr)
+ return ERR_PTR(-ENOMEM);
+
+ tsa = tsa_get_byphandle(np, phandle_name);
+ if (!IS_ERR(tsa)) {
+ *dr = tsa;
+ devres_add(dev, dr);
+ } else {
+ devres_free(dr);
+ }
+
+ return tsa;
+}
+EXPORT_SYMBOL(devm_tsa_get_byphandle);
+
+MODULE_AUTHOR("Herve Codina <[email protected]>");
+MODULE_DESCRIPTION("CPM TSA driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/fsl/qe/tsa.h b/drivers/soc/fsl/qe/tsa.h
new file mode 100644
index 000000000000..b253d2a17955
--- /dev/null
+++ b/drivers/soc/fsl/qe/tsa.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TSA management
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina <[email protected]>
+ */
+#ifndef __SOC_FSL_TSA_H__
+#define __SOC_FSL_TSA_H__
+
+#include <dt-bindings/soc/fsl,tsa.h>
+#include <linux/types.h>
+
+struct device_node;
+struct device;
+struct tsa;
+
+struct tsa *tsa_get_byphandle(struct device_node *np, const char *phandle_name);
+void tsa_put(struct tsa *tsa);
+struct tsa *devm_tsa_get_byphandle(struct device *dev, struct device_node *np,
+ const char *phandle_name);
+
+/* Connect and disconnect. cell_id is one of FSL_CPM_TSA_* available in
+ * dt-bindings/soc/fsl-fsa.h
+ */
+int tsa_connect(struct tsa *tsa, unsigned int cell_id);
+int tsa_disconnect(struct tsa *tsa, unsigned int cell_id);
+
+/* Cell information */
+struct tsa_cell_info {
+ unsigned long rx_fs_rate;
+ unsigned long rx_bit_rate;
+ u8 nb_rx_ts;
+ unsigned long tx_fs_rate;
+ unsigned long tx_bit_rate;
+ u8 nb_tx_ts;
+};
+
+/* Get information */
+int tsa_get_info(struct tsa *tsa, unsigned int cell_id, struct tsa_cell_info *info);
+
+#endif /* __SOC_FSL_TSA_H__ */
--
2.38.1
Add support for the QMC (QUICC Multichannel Controller)
available in some PowerQUICC SoC such as MPC885 or MPC866.
Signed-off-by: Herve Codina <[email protected]>
---
.../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
1 file changed, 164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
new file mode 100644
index 000000000000..3ec52f1635c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
+
+maintainers:
+ - Herve Codina <[email protected]>
+
+description: |
+ The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
+ one serial controller using the same TDM physical interface routed from
+ TSA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc885-scc-qmc
+ - fsl,mpc866-scc-qmc
+ - const: fsl,cpm1-scc-qmc
+
+ reg:
+ items:
+ - description: SCC (Serial communication controller) register base
+ - description: SCC parameter ram base
+ - description: Dual port ram base
+
+ reg-names:
+ items:
+ - const: scc_regs
+ - const: scc_pram
+ - const: dpram
+
+ interrupts:
+ maxItems: 1
+ description: SCC interrupt line in the CPM interrupt controller
+
+ fsl,tsa:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the TSA
+
+ fsl,tsa-cell-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+ description: |
+ TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
+ - 1: SCC2
+ - 2: SCC3
+ - 3: SCC4
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#chan-cells':
+ const: 1
+
+patternProperties:
+ '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
+ description:
+ A channel managed by this controller
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 63
+ description:
+ The channel number
+
+ fsl,mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [transparent, hdlc]
+ default: transparent
+ description: Operational mode
+
+ fsl,reverse-data:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The bit order as seen on the channels is reversed,
+ transmitting/receiving the MSB of each octet first.
+ This flag is used only in 'transparent' mode.
+
+ fsl,tx-ts-mask:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description:
+ Channel assigned Tx time-slots within the Tx time-slots routed
+ by the TSA to this cell.
+
+ fsl,rx-ts-mask:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description:
+ Channel assigned Rx time-slots within the Rx time-slots routed
+ by the TSA to this cell.
+
+ required:
+ - reg
+ - fsl,tx-ts-mask
+ - fsl,rx-ts-mask
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - fsl,tsa
+ - fsl,tsa-cell-id
+ - '#address-cells'
+ - '#size-cells'
+ - '#chan-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/fsl,tsa.h>
+
+ qmc@a60 {
+ compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
+ reg = <0xa60 0x20>,
+ <0x3f00 0xc0>,
+ <0x2000 0x1000>;
+ reg-names = "scc_regs", "scc_pram", "dpram";
+ interrupts = <27>;
+ interrupt-parent = <&CPM_PIC>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #chan-cells = <1>;
+
+ fsl,tsa = <&tsa>;
+ fsl,tsa-cell-id = <FSL_CPM_TSA_SCC4>;
+
+ channel@16 {
+ /* Ch16 : First 4 even TS from all routed from TSA */
+ reg = <16>;
+ fsl,mode = "transparent";
+ fsl,reverse-data;
+ fsl,tx-ts-mask = <0x00000000 0x000000aa>;
+ fsl,rx-ts-mask = <0x00000000 0x000000aa>;
+ };
+
+ channel@17 {
+ /* Ch17 : First 4 odd TS from all routed from TSA */
+ reg = <17>;
+ fsl,mode = "transparent";
+ fsl,reverse-data;
+ fsl,tx-ts-mask = <0x00000000 0x00000055>;
+ fsl,rx-ts-mask = <0x00000000 0x00000055>;
+ };
+
+ channel@19 {
+ /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
+ reg = <19>;
+ fsl,mode = "hdlc";
+ fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
+ fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
+ };
+ };
--
2.38.1
Add support for the time slot assigner (TSA)
available in some PowerQUICC SoC such as MPC885
or MPC866.
Signed-off-by: Herve Codina <[email protected]>
---
.../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++
include/dt-bindings/soc/fsl,tsa.h | 13 +
2 files changed, 273 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
create mode 100644 include/dt-bindings/soc/fsl,tsa.h
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
new file mode 100644
index 000000000000..eb17b6119abd
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
@@ -0,0 +1,260 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM Time-slot assigner (TSA) controller
+
+maintainers:
+ - Herve Codina <[email protected]>
+
+description: |
+ The TSA is the time-slot assigner that can be found on some
+ PowerQUICC SoC.
+ Its purpose is to route some TDM time-slots to other internal
+ serial controllers.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc885-tsa
+ - fsl,mpc866-tsa
+ - const: fsl,cpm1-tsa
+
+ reg:
+ items:
+ - description: SI (Serial Interface) register base
+ - description: SI RAM base
+
+ reg-names:
+ items:
+ - const: si_regs
+ - const: si_ram
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^tdm@[0-1]$':
+ description:
+ The TDM managed by this controller
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1
+ description:
+ The TDM number for this TDM, 0 for TDMa and 1 for TDMb
+
+ fsl,common-rxtx-pins:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The hardware can use four dedicated pins for Tx clock,
+ Tx sync, Rx clock and Rx sync or use only two pins,
+ Tx/Rx clock and Rx/Rx sync.
+ Without the 'fsl,common-rxtx-pins' property, the four
+ pins are used. With the 'fsl,common-rxtx-pins' property,
+ two pins are used.
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+
+ fsl,mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [normal, echo, internal-loopback, control-loopback]
+ default: normal
+ description: |
+ Operational mode:
+ - normal:
+ Normal operation
+ - echo:
+ Automatic echo. Rx data is resent on Tx
+ - internal-loopback:
+ The TDM transmitter is connected to the receiver.
+ Data appears on Tx pin.
+ - control-loopback:
+ The TDM transmitter is connected to the receiver.
+ The Tx pin is disconnected.
+
+ fsl,rx-frame-sync-delay-bits:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Receive frame sync delay in number of bits.
+ Indicates the delay between the Rx sync and the first bit of the
+ Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+ fsl,tx-frame-sync-delay-bits:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ Transmit frame sync delay in number of bits.
+ Indicates the delay between the Tx sync and the first bit of the
+ Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+ fsl,clock-falling-edge:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Data is sent on falling edge of the clock (and received on the
+ rising edge).
+ If 'clock-falling-edge' is not present, data is sent on the
+ rising edge (and received on the falling edge).
+
+ fsl,fsync-rising-edge:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Frame sync pulses are sampled with the rising edge of the channel
+ clock. If 'fsync-rising-edge' is not present, pulses are sample
+ with e falling edge.
+
+ fsl,double-speed-clock:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The channel clock is twice the data rate.
+
+ fsl,tx-ts-routes:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ A list of tupple that indicates the Tx time-slots routes.
+ tx_ts_routes =
+ < 2 0 >, /* The first 2 time slots are not used */
+ < 3 1 >, /* The next 3 ones are route to SCC2 */
+ < 4 0 >, /* The next 4 ones are not used */
+ < 2 2 >; /* The nest 2 ones are route to SCC3 */
+ items:
+ items:
+ - description:
+ The number of time-slots
+ minimum: 1
+ maximum: 64
+ - description: |
+ The source serial interface (dt-bindings/soc/fsl,tsa.h
+ defines these values)
+ - 0: No destination
+ - 1: SCC2
+ - 2: SCC3
+ - 3: SCC4
+ - 4: SMC1
+ - 5: SMC2
+ enum: [0, 1, 2, 3, 4, 5]
+ minItems: 1
+ maxItems: 64
+
+ fsl,rx-ts-routes:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ A list of tupple that indicates the Rx time-slots routes.
+ tx_ts_routes =
+ < 2 0 >, /* The first 2 time slots are not used */
+ < 3 1 >, /* The next 3 ones are route from SCC2 */
+ < 4 0 >, /* The next 4 ones are not used */
+ < 2 2 >; /* The nest 2 ones are route from SCC3 */
+ items:
+ items:
+ - description:
+ The number of time-slots
+ minimum: 1
+ maximum: 64
+ - description: |
+ The destination serial interface (dt-bindings/soc/fsl,tsa.h
+ defines these values)
+ - 0: No destination
+ - 1: SCC2
+ - 2: SCC3
+ - 3: SCC4
+ - 4: SMC1
+ - 5: SMC2
+ enum: [0, 1, 2, 3, 4, 5]
+ minItems: 1
+ maxItems: 64
+
+ allOf:
+ # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
+ # Else, the 4 clocks must be present.
+ - if:
+ required:
+ - fsl,common-rxtx-pins
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External clock connected to L1RSYNC pin
+ - description: External clock connected to L1RCLK pin
+ clock-names:
+ items:
+ - const: l1rsync
+ - const: l1rclk
+ else:
+ properties:
+ clocks:
+ items:
+ - description: External clock connected to L1RSYNC pin
+ - description: External clock connected to L1RCLK pin
+ - description: External clock connected to L1TSYNC pin
+ - description: External clock connected to L1TCLK pin
+ clock-names:
+ items:
+ - const: l1rsync
+ - const: l1rclk
+ - const: l1tsync
+ - const: l1tclk
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/fsl,tsa.h>
+
+ tsa@ae0 {
+ compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
+ reg = <0xae0 0x10>,
+ <0xc00 0x200>;
+ reg-names = "si_regs", "si_ram";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tdm@0 {
+ /* TDMa */
+ reg = <0>;
+
+ clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
+ clock-names = "l1rsync", "l1rclk";
+
+ fsl,common-rxtx-pins;
+ fsl,fsync-rising-edge;
+
+ fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */
+ < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */
+ < 1 0 >, /* TS 26 */
+ < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
+
+ fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */
+ < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */
+ < 1 0 >, /* TS 26 */
+ < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
+ };
+ };
diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h
new file mode 100644
index 000000000000..2cc44e867dbe
--- /dev/null
+++ b/include/dt-bindings/soc/fsl,tsa.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_SOC_FSL_TSA_H
+#define __DT_BINDINGS_SOC_FSL_TSA_H
+
+#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */
+#define FSL_CPM_TSA_SCC2 1
+#define FSL_CPM_TSA_SCC3 2
+#define FSL_CPM_TSA_SCC4 3
+#define FSL_CPM_TSA_SMC1 4
+#define FSL_CPM_TSA_SMC2 5
+
+#endif
--
2.38.1
The CPM1 command mask is defined for use with the standard
CPM1 command register as described in the user's manual:
0 |1 3|4 7|8 11|12 14| 15|
RST| - |OPCODE|CH_NUM| - |FLG|
In the QMC extension the CPM1 command register is redefined
(QMC supplement user's manuel) with the following mapping:
0 |1 3|4 7|8 13|14| 15|
RST|QMC OPCODE| 1110|CHANNEL_NUMBER| -|FLG|
Extend the check command mask in order to support both the
standard CH_NUM field and the QMC extension CHANNEL_NUMBER
field.
Signed-off-by: Herve Codina <[email protected]>
Acked-by: Christophe Leroy <[email protected]>
---
arch/powerpc/platforms/8xx/cpm1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/8xx/cpm1.c b/arch/powerpc/platforms/8xx/cpm1.c
index 8ef1f4392086..6b828b9f90d9 100644
--- a/arch/powerpc/platforms/8xx/cpm1.c
+++ b/arch/powerpc/platforms/8xx/cpm1.c
@@ -100,7 +100,7 @@ int cpm_command(u32 command, u8 opcode)
int i, ret;
unsigned long flags;
- if (command & 0xffffff0f)
+ if (command & 0xffffff03)
return -EINVAL;
spin_lock_irqsave(&cmd_lock, flags);
--
2.38.1
On 13/01/2023 11:37, Herve Codina wrote:
> Add support for the QMC (QUICC Multichannel Controller)
> available in some PowerQUICC SoC such as MPC885 or MPC866.
>
> Signed-off-by: Herve Codina <[email protected]>
> ---
> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
> 1 file changed, 164 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> new file mode 100644
> index 000000000000..3ec52f1635c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> @@ -0,0 +1,164 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
> +
> +maintainers:
> + - Herve Codina <[email protected]>
> +
> +description: |
> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
> + one serial controller using the same TDM physical interface routed from
> + TSA.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc885-scc-qmc
> + - fsl,mpc866-scc-qmc
> + - const: fsl,cpm1-scc-qmc
> +
> + reg:
> + items:
> + - description: SCC (Serial communication controller) register base
> + - description: SCC parameter ram base
> + - description: Dual port ram base
> +
> + reg-names:
> + items:
> + - const: scc_regs
> + - const: scc_pram
> + - const: dpram
> +
> + interrupts:
> + maxItems: 1
> + description: SCC interrupt line in the CPM interrupt controller
> +
> + fsl,tsa:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle to the TSA
> +
> + fsl,tsa-cell-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 3]
> + description: |
> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> + - 1: SCC2
> + - 2: SCC3
> + - 3: SCC4
Is this used as argument to tsa? If so, this should be part of fsl,tsa
property, just like we do for all syscon-like phandles.
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + '#chan-cells':
> + const: 1
> +
> +patternProperties:
> + '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
> + description:
> + A channel managed by this controller
> + type: object
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 63
> + description:
> + The channel number
> +
> + fsl,mode:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [transparent, hdlc]
> + default: transparent
> + description: Operational mode
You still need to explain what do transparent and hdlc mean.
> +
Best regards,
Krzysztof
On 13/01/2023 11:37, Herve Codina wrote:
> Add support for the time slot assigner (TSA)
> available in some PowerQUICC SoC such as MPC885
> or MPC866.
>
> Signed-off-by: Herve Codina <[email protected]>
> ---
> .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++
> include/dt-bindings/soc/fsl,tsa.h | 13 +
> 2 files changed, 273 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> create mode 100644 include/dt-bindings/soc/fsl,tsa.h
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 13/01/2023 11:37, Herve Codina wrote:
> The QMC (QUICC mutichannel controller) is a controller
> present in some PowerQUICC SoC such as MPC885.
> The QMC audio is an ASoC component that uses the QMC
> controller to transfer the audio data.
>
> Signed-off-by: Herve Codina <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote:
> Add support for the time slot assigner (TSA)
> available in some PowerQUICC SoC such as MPC885
> or MPC866.
An odd line wrap length...
>
> Signed-off-by: Herve Codina <[email protected]>
> ---
> .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++
> include/dt-bindings/soc/fsl,tsa.h | 13 +
> 2 files changed, 273 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> create mode 100644 include/dt-bindings/soc/fsl,tsa.h
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> new file mode 100644
> index 000000000000..eb17b6119abd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> @@ -0,0 +1,260 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: PowerQUICC CPM Time-slot assigner (TSA) controller
> +
> +maintainers:
> + - Herve Codina <[email protected]>
> +
> +description: |
Don't need '|' if no formatting.
> + The TSA is the time-slot assigner that can be found on some
> + PowerQUICC SoC.
> + Its purpose is to route some TDM time-slots to other internal
> + serial controllers.
Wrap at 80.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,mpc885-tsa
> + - fsl,mpc866-tsa
> + - const: fsl,cpm1-tsa
> +
> + reg:
> + items:
> + - description: SI (Serial Interface) register base
> + - description: SI RAM base
> +
> + reg-names:
> + items:
> + - const: si_regs
> + - const: si_ram
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> +patternProperties:
> + '^tdm@[0-1]$':
> + description:
> + The TDM managed by this controller
> + type: object
additionalProperties: false
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 1
> + description:
> + The TDM number for this TDM, 0 for TDMa and 1 for TDMb
> +
> + fsl,common-rxtx-pins:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + The hardware can use four dedicated pins for Tx clock,
> + Tx sync, Rx clock and Rx sync or use only two pins,
> + Tx/Rx clock and Rx/Rx sync.
> + Without the 'fsl,common-rxtx-pins' property, the four
> + pins are used. With the 'fsl,common-rxtx-pins' property,
> + two pins are used.
> +
> + clocks:
> + minItems: 2
> + maxItems: 4
> +
> + clock-names:
> + minItems: 2
> + maxItems: 4
> +
> + fsl,mode:
'mode' is a bit vague. It's already used as well which can be a problem
if there are differing types. (There's not in this case)
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [normal, echo, internal-loopback, control-loopback]
> + default: normal
> + description: |
> + Operational mode:
> + - normal:
> + Normal operation
> + - echo:
> + Automatic echo. Rx data is resent on Tx
> + - internal-loopback:
> + The TDM transmitter is connected to the receiver.
> + Data appears on Tx pin.
> + - control-loopback:
> + The TDM transmitter is connected to the receiver.
> + The Tx pin is disconnected.
> +
> + fsl,rx-frame-sync-delay-bits:
> + enum: [0, 1, 2, 3]
> + default: 0
> + description: |
> + Receive frame sync delay in number of bits.
> + Indicates the delay between the Rx sync and the first bit of the
> + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
> +
> + fsl,tx-frame-sync-delay-bits:
> + enum: [0, 1, 2, 3]
> + default: 0
> + description: |
> + Transmit frame sync delay in number of bits.
> + Indicates the delay between the Tx sync and the first bit of the
> + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
> +
> + fsl,clock-falling-edge:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: |
> + Data is sent on falling edge of the clock (and received on the
> + rising edge).
> + If 'clock-falling-edge' is not present, data is sent on the
> + rising edge (and received on the falling edge).
> +
> + fsl,fsync-rising-edge:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Frame sync pulses are sampled with the rising edge of the channel
> + clock. If 'fsync-rising-edge' is not present, pulses are sample
> + with e falling edge.
> +
> + fsl,double-speed-clock:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + The channel clock is twice the data rate.
> +
> + fsl,tx-ts-routes:
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + description: |
> + A list of tupple that indicates the Tx time-slots routes.
> + tx_ts_routes =
> + < 2 0 >, /* The first 2 time slots are not used */
> + < 3 1 >, /* The next 3 ones are route to SCC2 */
> + < 4 0 >, /* The next 4 ones are not used */
> + < 2 2 >; /* The nest 2 ones are route to SCC3 */
> + items:
> + items:
> + - description:
> + The number of time-slots
> + minimum: 1
> + maximum: 64
> + - description: |
> + The source serial interface (dt-bindings/soc/fsl,tsa.h
> + defines these values)
> + - 0: No destination
> + - 1: SCC2
> + - 2: SCC3
> + - 3: SCC4
> + - 4: SMC1
> + - 5: SMC2
> + enum: [0, 1, 2, 3, 4, 5]
> + minItems: 1
> + maxItems: 64
> +
> + fsl,rx-ts-routes:
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + description: |
> + A list of tupple that indicates the Rx time-slots routes.
> + tx_ts_routes =
> + < 2 0 >, /* The first 2 time slots are not used */
> + < 3 1 >, /* The next 3 ones are route from SCC2 */
> + < 4 0 >, /* The next 4 ones are not used */
> + < 2 2 >; /* The nest 2 ones are route from SCC3 */
> + items:
> + items:
> + - description:
> + The number of time-slots
> + minimum: 1
> + maximum: 64
> + - description: |
> + The destination serial interface (dt-bindings/soc/fsl,tsa.h
> + defines these values)
> + - 0: No destination
> + - 1: SCC2
> + - 2: SCC3
> + - 3: SCC4
> + - 4: SMC1
> + - 5: SMC2
> + enum: [0, 1, 2, 3, 4, 5]
> + minItems: 1
> + maxItems: 64
> +
> + allOf:
> + # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
> + # Else, the 4 clocks must be present.
> + - if:
> + required:
> + - fsl,common-rxtx-pins
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External clock connected to L1RSYNC pin
> + - description: External clock connected to L1RCLK pin
> + clock-names:
> + items:
> + - const: l1rsync
> + - const: l1rclk
> + else:
> + properties:
> + clocks:
> + items:
> + - description: External clock connected to L1RSYNC pin
> + - description: External clock connected to L1RCLK pin
> + - description: External clock connected to L1TSYNC pin
> + - description: External clock connected to L1TCLK pin
> + clock-names:
> + items:
> + - const: l1rsync
> + - const: l1rclk
> + - const: l1tsync
> + - const: l1tclk
As the names are the same, just the length varies between 2 or 4, move
all this to the main definition and here just put constraints on the
length.
> +
> + required:
> + - reg
> + - clocks
> + - clock-names
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - '#address-cells'
> + - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/soc/fsl,tsa.h>
> +
> + tsa@ae0 {
> + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
> + reg = <0xae0 0x10>,
> + <0xc00 0x200>;
> + reg-names = "si_regs", "si_ram";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tdm@0 {
> + /* TDMa */
> + reg = <0>;
> +
> + clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
> + clock-names = "l1rsync", "l1rclk";
> +
> + fsl,common-rxtx-pins;
> + fsl,fsync-rising-edge;
> +
> + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */
> + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */
> + < 1 0 >, /* TS 26 */
> + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
> +
> + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */
> + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */
> + < 1 0 >, /* TS 26 */
> + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
> + };
> + };
> diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h
> new file mode 100644
> index 000000000000..2cc44e867dbe
> --- /dev/null
> +++ b/include/dt-bindings/soc/fsl,tsa.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +
> +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H
> +#define __DT_BINDINGS_SOC_FSL_TSA_H
> +
> +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */
> +#define FSL_CPM_TSA_SCC2 1
> +#define FSL_CPM_TSA_SCC3 2
> +#define FSL_CPM_TSA_SCC4 3
> +#define FSL_CPM_TSA_SMC1 4
> +#define FSL_CPM_TSA_SMC2 5
> +
> +#endif
> --
> 2.38.1
>
Hi Rob,
On Tue, 17 Jan 2023 08:55:29 -0600
Rob Herring <[email protected]> wrote:
> On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote:
> > Add support for the time slot assigner (TSA)
> > available in some PowerQUICC SoC such as MPC885
> > or MPC866.
>
> An odd line wrap length...
Will be changed in v4.
>
> >
> > Signed-off-by: Herve Codina <[email protected]>
> > ---
> > .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++
> > include/dt-bindings/soc/fsl,tsa.h | 13 +
> > 2 files changed, 273 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> > create mode 100644 include/dt-bindings/soc/fsl,tsa.h
> >
> > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> > new file mode 100644
> > index 000000000000..eb17b6119abd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
> > @@ -0,0 +1,260 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: PowerQUICC CPM Time-slot assigner (TSA) controller
> > +
> > +maintainers:
> > + - Herve Codina <[email protected]>
> > +
> > +description: |
>
> Don't need '|' if no formatting.
Will be changed in v4.
>
> > + The TSA is the time-slot assigner that can be found on some
> > + PowerQUICC SoC.
> > + Its purpose is to route some TDM time-slots to other internal
> > + serial controllers.
>
> Wrap at 80.
Will be fixed in v4.
>
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,mpc885-tsa
> > + - fsl,mpc866-tsa
> > + - const: fsl,cpm1-tsa
> > +
> > + reg:
> > + items:
> > + - description: SI (Serial Interface) register base
> > + - description: SI RAM base
> > +
> > + reg-names:
> > + items:
> > + - const: si_regs
> > + - const: si_ram
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 0
> > +
> > +patternProperties:
> > + '^tdm@[0-1]$':
> > + description:
> > + The TDM managed by this controller
> > + type: object
>
> additionalProperties: false
Will be added in v4.
>
> > +
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 1
> > + description:
> > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb
> > +
> > + fsl,common-rxtx-pins:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + The hardware can use four dedicated pins for Tx clock,
> > + Tx sync, Rx clock and Rx sync or use only two pins,
> > + Tx/Rx clock and Rx/Rx sync.
> > + Without the 'fsl,common-rxtx-pins' property, the four
> > + pins are used. With the 'fsl,common-rxtx-pins' property,
> > + two pins are used.
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 4
> > +
> > + clock-names:
> > + minItems: 2
> > + maxItems: 4
> > +
> > + fsl,mode:
>
> 'mode' is a bit vague. It's already used as well which can be a problem
> if there are differing types. (There's not in this case)
What do you think about:
fsl,diagnostic-mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [disabled, echo, internal-loopback, control-loopback]
default: disabled
description: |
The diagnostic mode can be used to diagnose some communication issues.
It should not be present (or set to 'disabled') when diagnostic is not
needed.
Diagnostic mode:
- disabled:
Diagnostic disabled (ie. normal operation)
- echo:
Automatic echo. Rx data is resent on Tx
- internal-loopback:
The TDM transmitter is connected to the receiver.
Data appears on Tx pin.
- control-loopback:
The TDM transmitter is connected to the receiver.
The Tx pin is disconnected.
>
> > + $ref: /schemas/types.yaml#/definitions/string
> > + enum: [normal, echo, internal-loopback, control-loopback]
> > + default: normal
> > + description: |
> > + Operational mode:
> > + - normal:
> > + Normal operation
> > + - echo:
> > + Automatic echo. Rx data is resent on Tx
> > + - internal-loopback:
> > + The TDM transmitter is connected to the receiver.
> > + Data appears on Tx pin.
> > + - control-loopback:
> > + The TDM transmitter is connected to the receiver.
> > + The Tx pin is disconnected.
> > +
> > + fsl,rx-frame-sync-delay-bits:
> > + enum: [0, 1, 2, 3]
> > + default: 0
> > + description: |
> > + Receive frame sync delay in number of bits.
> > + Indicates the delay between the Rx sync and the first bit of the
> > + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
> > +
> > + fsl,tx-frame-sync-delay-bits:
> > + enum: [0, 1, 2, 3]
> > + default: 0
> > + description: |
> > + Transmit frame sync delay in number of bits.
> > + Indicates the delay between the Tx sync and the first bit of the
> > + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
> > +
> > + fsl,clock-falling-edge:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description: |
> > + Data is sent on falling edge of the clock (and received on the
> > + rising edge).
> > + If 'clock-falling-edge' is not present, data is sent on the
> > + rising edge (and received on the falling edge).
> > +
> > + fsl,fsync-rising-edge:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + Frame sync pulses are sampled with the rising edge of the channel
> > + clock. If 'fsync-rising-edge' is not present, pulses are sample
> > + with e falling edge.
> > +
> > + fsl,double-speed-clock:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + The channel clock is twice the data rate.
> > +
> > + fsl,tx-ts-routes:
> > + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > + description: |
> > + A list of tupple that indicates the Tx time-slots routes.
> > + tx_ts_routes =
> > + < 2 0 >, /* The first 2 time slots are not used */
> > + < 3 1 >, /* The next 3 ones are route to SCC2 */
> > + < 4 0 >, /* The next 4 ones are not used */
> > + < 2 2 >; /* The nest 2 ones are route to SCC3 */
> > + items:
> > + items:
> > + - description:
> > + The number of time-slots
> > + minimum: 1
> > + maximum: 64
> > + - description: |
> > + The source serial interface (dt-bindings/soc/fsl,tsa.h
> > + defines these values)
> > + - 0: No destination
> > + - 1: SCC2
> > + - 2: SCC3
> > + - 3: SCC4
> > + - 4: SMC1
> > + - 5: SMC2
> > + enum: [0, 1, 2, 3, 4, 5]
> > + minItems: 1
> > + maxItems: 64
> > +
> > + fsl,rx-ts-routes:
> > + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > + description: |
> > + A list of tupple that indicates the Rx time-slots routes.
> > + tx_ts_routes =
> > + < 2 0 >, /* The first 2 time slots are not used */
> > + < 3 1 >, /* The next 3 ones are route from SCC2 */
> > + < 4 0 >, /* The next 4 ones are not used */
> > + < 2 2 >; /* The nest 2 ones are route from SCC3 */
> > + items:
> > + items:
> > + - description:
> > + The number of time-slots
> > + minimum: 1
> > + maximum: 64
> > + - description: |
> > + The destination serial interface (dt-bindings/soc/fsl,tsa.h
> > + defines these values)
> > + - 0: No destination
> > + - 1: SCC2
> > + - 2: SCC3
> > + - 3: SCC4
> > + - 4: SMC1
> > + - 5: SMC2
> > + enum: [0, 1, 2, 3, 4, 5]
> > + minItems: 1
> > + maxItems: 64
> > +
> > + allOf:
> > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
> > + # Else, the 4 clocks must be present.
> > + - if:
> > + required:
> > + - fsl,common-rxtx-pins
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: External clock connected to L1RSYNC pin
> > + - description: External clock connected to L1RCLK pin
> > + clock-names:
> > + items:
> > + - const: l1rsync
> > + - const: l1rclk
> > + else:
> > + properties:
> > + clocks:
> > + items:
> > + - description: External clock connected to L1RSYNC pin
> > + - description: External clock connected to L1RCLK pin
> > + - description: External clock connected to L1TSYNC pin
> > + - description: External clock connected to L1TCLK pin
> > + clock-names:
> > + items:
> > + - const: l1rsync
> > + - const: l1rclk
> > + - const: l1tsync
> > + - const: l1tclk
>
> As the names are the same, just the length varies between 2 or 4, move
> all this to the main definition and here just put constraints on the
> length.
Ok, will be done in v4.
>
> > +
> > + required:
> > + - reg
> > + - clocks
> > + - clock-names
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - '#address-cells'
> > + - '#size-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/soc/fsl,tsa.h>
> > +
> > + tsa@ae0 {
> > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
> > + reg = <0xae0 0x10>,
> > + <0xc00 0x200>;
> > + reg-names = "si_regs", "si_ram";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + tdm@0 {
> > + /* TDMa */
> > + reg = <0>;
> > +
> > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
> > + clock-names = "l1rsync", "l1rclk";
> > +
> > + fsl,common-rxtx-pins;
> > + fsl,fsync-rising-edge;
> > +
> > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */
> > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */
> > + < 1 0 >, /* TS 26 */
> > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
> > +
> > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */
> > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */
> > + < 1 0 >, /* TS 26 */
> > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */
> > + };
> > + };
> > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h
> > new file mode 100644
> > index 000000000000..2cc44e867dbe
> > --- /dev/null
> > +++ b/include/dt-bindings/soc/fsl,tsa.h
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> > +
> > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H
> > +#define __DT_BINDINGS_SOC_FSL_TSA_H
> > +
> > +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */
> > +#define FSL_CPM_TSA_SCC2 1
> > +#define FSL_CPM_TSA_SCC3 2
> > +#define FSL_CPM_TSA_SCC4 3
> > +#define FSL_CPM_TSA_SMC1 4
> > +#define FSL_CPM_TSA_SMC2 5
> > +
> > +#endif
> > --
> > 2.38.1
> >
Thanks for the review,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Hi Krzysztof,
On Tue, 17 Jan 2023 12:31:09 +0100
Krzysztof Kozlowski <[email protected]> wrote:
> On 13/01/2023 11:37, Herve Codina wrote:
> > Add support for the QMC (QUICC Multichannel Controller)
> > available in some PowerQUICC SoC such as MPC885 or MPC866.
> >
> > Signed-off-by: Herve Codina <[email protected]>
> > ---
> > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
> > 1 file changed, 164 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> > new file mode 100644
> > index 000000000000..3ec52f1635c8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> > @@ -0,0 +1,164 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
> > +
> > +maintainers:
> > + - Herve Codina <[email protected]>
> > +
> > +description: |
> > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
> > + one serial controller using the same TDM physical interface routed from
> > + TSA.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,mpc885-scc-qmc
> > + - fsl,mpc866-scc-qmc
> > + - const: fsl,cpm1-scc-qmc
> > +
> > + reg:
> > + items:
> > + - description: SCC (Serial communication controller) register base
> > + - description: SCC parameter ram base
> > + - description: Dual port ram base
> > +
> > + reg-names:
> > + items:
> > + - const: scc_regs
> > + - const: scc_pram
> > + - const: dpram
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: SCC interrupt line in the CPM interrupt controller
> > +
> > + fsl,tsa:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: phandle to the TSA
> > +
> > + fsl,tsa-cell-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [1, 2, 3]
> > + description: |
> > + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> > + - 1: SCC2
> > + - 2: SCC3
> > + - 3: SCC4
>
> Is this used as argument to tsa? If so, this should be part of fsl,tsa
> property, just like we do for all syscon-like phandles.
Yes, indeed.
I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number
pair (the phandle to TSA node and the TSA cell id to use)
>
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 0
> > +
> > + '#chan-cells':
> > + const: 1
> > +
> > +patternProperties:
> > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
> > + description:
> > + A channel managed by this controller
> > + type: object
> > +
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 63
> > + description:
> > + The channel number
> > +
> > + fsl,mode:
> > + $ref: /schemas/types.yaml#/definitions/string
> > + enum: [transparent, hdlc]
> > + default: transparent
> > + description: Operational mode
>
> You still need to explain what do transparent and hdlc mean.
Oups, my bad (already mentioned in the previous version review).
Also, I will rename the property to 'fsl,operational-mode' to be
more precise than just 'fsl,mode'
>
> > +
>
>
> Best regards,
> Krzysztof
>
Thanks for the review,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On 24/01/2023 10:42, Herve Codina wrote:
> Hi Krzysztof,
>
> On Tue, 17 Jan 2023 12:31:09 +0100
> Krzysztof Kozlowski <[email protected]> wrote:
>
>> On 13/01/2023 11:37, Herve Codina wrote:
>>> Add support for the QMC (QUICC Multichannel Controller)
>>> available in some PowerQUICC SoC such as MPC885 or MPC866.
>>>
>>> Signed-off-by: Herve Codina <[email protected]>
>>> ---
>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
>>> 1 file changed, 164 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>> new file mode 100644
>>> index 000000000000..3ec52f1635c8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>> @@ -0,0 +1,164 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
>>> +
>>> +maintainers:
>>> + - Herve Codina <[email protected]>
>>> +
>>> +description: |
>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
>>> + one serial controller using the same TDM physical interface routed from
>>> + TSA.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - fsl,mpc885-scc-qmc
>>> + - fsl,mpc866-scc-qmc
>>> + - const: fsl,cpm1-scc-qmc
>>> +
>>> + reg:
>>> + items:
>>> + - description: SCC (Serial communication controller) register base
>>> + - description: SCC parameter ram base
>>> + - description: Dual port ram base
>>> +
>>> + reg-names:
>>> + items:
>>> + - const: scc_regs
>>> + - const: scc_pram
>>> + - const: dpram
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> + description: SCC interrupt line in the CPM interrupt controller
>>> +
>>> + fsl,tsa:
>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>> + description: phandle to the TSA
>>> +
>>> + fsl,tsa-cell-id:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + enum: [1, 2, 3]
>>> + description: |
>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
>>> + - 1: SCC2
>>> + - 2: SCC3
>>> + - 3: SCC4
>>
>> Is this used as argument to tsa? If so, this should be part of fsl,tsa
>> property, just like we do for all syscon-like phandles.
>
> Yes, indeed.
> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number
> pair (the phandle to TSA node and the TSA cell id to use)
Move to fsl,tsa, not from.
Best regards,
Krzysztof
On Tue, 24 Jan 2023 11:02:52 +0100
Krzysztof Kozlowski <[email protected]> wrote:
> On 24/01/2023 10:42, Herve Codina wrote:
> > Hi Krzysztof,
> >
> > On Tue, 17 Jan 2023 12:31:09 +0100
> > Krzysztof Kozlowski <[email protected]> wrote:
> >
> >> On 13/01/2023 11:37, Herve Codina wrote:
> >>> Add support for the QMC (QUICC Multichannel Controller)
> >>> available in some PowerQUICC SoC such as MPC885 or MPC866.
> >>>
> >>> Signed-off-by: Herve Codina <[email protected]>
> >>> ---
> >>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
> >>> 1 file changed, 164 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>> new file mode 100644
> >>> index 000000000000..3ec52f1635c8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>> @@ -0,0 +1,164 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
> >>> +
> >>> +maintainers:
> >>> + - Herve Codina <[email protected]>
> >>> +
> >>> +description: |
> >>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
> >>> + one serial controller using the same TDM physical interface routed from
> >>> + TSA.
> >>> +
> >>> +properties:
> >>> + compatible:
> >>> + items:
> >>> + - enum:
> >>> + - fsl,mpc885-scc-qmc
> >>> + - fsl,mpc866-scc-qmc
> >>> + - const: fsl,cpm1-scc-qmc
> >>> +
> >>> + reg:
> >>> + items:
> >>> + - description: SCC (Serial communication controller) register base
> >>> + - description: SCC parameter ram base
> >>> + - description: Dual port ram base
> >>> +
> >>> + reg-names:
> >>> + items:
> >>> + - const: scc_regs
> >>> + - const: scc_pram
> >>> + - const: dpram
> >>> +
> >>> + interrupts:
> >>> + maxItems: 1
> >>> + description: SCC interrupt line in the CPM interrupt controller
> >>> +
> >>> + fsl,tsa:
> >>> + $ref: /schemas/types.yaml#/definitions/phandle
> >>> + description: phandle to the TSA
> >>> +
> >>> + fsl,tsa-cell-id:
> >>> + $ref: /schemas/types.yaml#/definitions/uint32
> >>> + enum: [1, 2, 3]
> >>> + description: |
> >>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> >>> + - 1: SCC2
> >>> + - 2: SCC3
> >>> + - 3: SCC4
> >>
> >> Is this used as argument to tsa? If so, this should be part of fsl,tsa
> >> property, just like we do for all syscon-like phandles.
> >
> > Yes, indeed.
> > I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number
> > pair (the phandle to TSA node and the TSA cell id to use)
>
> Move to fsl,tsa, not from.
Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this:
fsl,tsa-cell:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to TSA node
- enum: [1, 2, 3]
description: |
TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
- 1: SCC2
- 2: SCC3
- 3: SCC4
description:
Should be a phandle/number pair. The phandle to TSA node and the TSA
cell ID to use.
Is that what you were thinking about ?
Best regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On 24/01/2023 12:23, Herve Codina wrote:
> On Tue, 24 Jan 2023 11:02:52 +0100
> Krzysztof Kozlowski <[email protected]> wrote:
>
>> On 24/01/2023 10:42, Herve Codina wrote:
>>> Hi Krzysztof,
>>>
>>> On Tue, 17 Jan 2023 12:31:09 +0100
>>> Krzysztof Kozlowski <[email protected]> wrote:
>>>
>>>> On 13/01/2023 11:37, Herve Codina wrote:
>>>>> Add support for the QMC (QUICC Multichannel Controller)
>>>>> available in some PowerQUICC SoC such as MPC885 or MPC866.
>>>>>
>>>>> Signed-off-by: Herve Codina <[email protected]>
>>>>> ---
>>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
>>>>> 1 file changed, 164 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..3ec52f1635c8
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
>>>>> @@ -0,0 +1,164 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
>>>>> +
>>>>> +maintainers:
>>>>> + - Herve Codina <[email protected]>
>>>>> +
>>>>> +description: |
>>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
>>>>> + one serial controller using the same TDM physical interface routed from
>>>>> + TSA.
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + items:
>>>>> + - enum:
>>>>> + - fsl,mpc885-scc-qmc
>>>>> + - fsl,mpc866-scc-qmc
>>>>> + - const: fsl,cpm1-scc-qmc
>>>>> +
>>>>> + reg:
>>>>> + items:
>>>>> + - description: SCC (Serial communication controller) register base
>>>>> + - description: SCC parameter ram base
>>>>> + - description: Dual port ram base
>>>>> +
>>>>> + reg-names:
>>>>> + items:
>>>>> + - const: scc_regs
>>>>> + - const: scc_pram
>>>>> + - const: dpram
>>>>> +
>>>>> + interrupts:
>>>>> + maxItems: 1
>>>>> + description: SCC interrupt line in the CPM interrupt controller
>>>>> +
>>>>> + fsl,tsa:
>>>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>>>> + description: phandle to the TSA
>>>>> +
>>>>> + fsl,tsa-cell-id:
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>>> + enum: [1, 2, 3]
>>>>> + description: |
>>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
>>>>> + - 1: SCC2
>>>>> + - 2: SCC3
>>>>> + - 3: SCC4
>>>>
>>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa
>>>> property, just like we do for all syscon-like phandles.
>>>
>>> Yes, indeed.
>>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number
>>> pair (the phandle to TSA node and the TSA cell id to use)
>>
>> Move to fsl,tsa, not from.
>
> Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this:
> fsl,tsa-cell:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> items:
> - items:
> - description: phandle to TSA node
> - enum: [1, 2, 3]
> description: |
> TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> - 1: SCC2
> - 2: SCC3
> - 3: SCC4
> description:
> Should be a phandle/number pair. The phandle to TSA node and the TSA
> cell ID to use.
>
> Is that what you were thinking about ?
Yes, except again, so third time, why calling this "cell"? Move it to
fsl,tsa.
Best regards,
Krzysztof
On Tue, 24 Jan 2023 13:24:48 +0100
Krzysztof Kozlowski <[email protected]> wrote:
> On 24/01/2023 12:23, Herve Codina wrote:
> > On Tue, 24 Jan 2023 11:02:52 +0100
> > Krzysztof Kozlowski <[email protected]> wrote:
> >
> >> On 24/01/2023 10:42, Herve Codina wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Tue, 17 Jan 2023 12:31:09 +0100
> >>> Krzysztof Kozlowski <[email protected]> wrote:
> >>>
> >>>> On 13/01/2023 11:37, Herve Codina wrote:
> >>>>> Add support for the QMC (QUICC Multichannel Controller)
> >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866.
> >>>>>
> >>>>> Signed-off-by: Herve Codina <[email protected]>
> >>>>> ---
> >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++
> >>>>> 1 file changed, 164 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..3ec52f1635c8
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
> >>>>> @@ -0,0 +1,164 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - Herve Codina <[email protected]>
> >>>>> +
> >>>>> +description: |
> >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
> >>>>> + one serial controller using the same TDM physical interface routed from
> >>>>> + TSA.
> >>>>> +
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>> + - fsl,mpc885-scc-qmc
> >>>>> + - fsl,mpc866-scc-qmc
> >>>>> + - const: fsl,cpm1-scc-qmc
> >>>>> +
> >>>>> + reg:
> >>>>> + items:
> >>>>> + - description: SCC (Serial communication controller) register base
> >>>>> + - description: SCC parameter ram base
> >>>>> + - description: Dual port ram base
> >>>>> +
> >>>>> + reg-names:
> >>>>> + items:
> >>>>> + - const: scc_regs
> >>>>> + - const: scc_pram
> >>>>> + - const: dpram
> >>>>> +
> >>>>> + interrupts:
> >>>>> + maxItems: 1
> >>>>> + description: SCC interrupt line in the CPM interrupt controller
> >>>>> +
> >>>>> + fsl,tsa:
> >>>>> + $ref: /schemas/types.yaml#/definitions/phandle
> >>>>> + description: phandle to the TSA
> >>>>> +
> >>>>> + fsl,tsa-cell-id:
> >>>>> + $ref: /schemas/types.yaml#/definitions/uint32
> >>>>> + enum: [1, 2, 3]
> >>>>> + description: |
> >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> >>>>> + - 1: SCC2
> >>>>> + - 2: SCC3
> >>>>> + - 3: SCC4
> >>>>
> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa
> >>>> property, just like we do for all syscon-like phandles.
> >>>
> >>> Yes, indeed.
> >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number
> >>> pair (the phandle to TSA node and the TSA cell id to use)
> >>
> >> Move to fsl,tsa, not from.
> >
> > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this:
> > fsl,tsa-cell:
> > $ref: /schemas/types.yaml#/definitions/phandle-array
> > items:
> > - items:
> > - description: phandle to TSA node
> > - enum: [1, 2, 3]
> > description: |
> > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values)
> > - 1: SCC2
> > - 2: SCC3
> > - 3: SCC4
> > description:
> > Should be a phandle/number pair. The phandle to TSA node and the TSA
> > cell ID to use.
> >
> > Is that what you were thinking about ?
>
> Yes, except again, so third time, why calling this "cell"? Move it to
> fsl,tsa.
>
Why calling this "cell" ? Just because we reference a "cell" using the TSA
cell ID inside TSA and not the TSA itself.
Maybe the problem is the term "cell" as it is not the DT definition of
"cell" but the source/destination of the TSA routing.
TSA can route data from/to some "serial controller".
These serial controllers are :
- SCC (Serial Communication Controller)
- SMC (Serial Management Controller)
- UCC (Unified Communication Controller)
Only SCCs are handled here.
Maybe the term "serial" makes more sense which will lead to
fsl,tsa-serial = <&tsa, SCC4>;
Best regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On 24/01/2023 15:15, Herve Codina wrote:
>>> Is that what you were thinking about ?
>>
>> Yes, except again, so third time, why calling this "cell"? Move it to
>> fsl,tsa.
>>
>
> Why calling this "cell" ? Just because we reference a "cell" using the TSA
> cell ID inside TSA and not the TSA itself.
>
> Maybe the problem is the term "cell" as it is not the DT definition of
> "cell" but the source/destination of the TSA routing.
>
> TSA can route data from/to some "serial controller".
> These serial controllers are :
> - SCC (Serial Communication Controller)
> - SMC (Serial Management Controller)
> - UCC (Unified Communication Controller)
>
> Only SCCs are handled here.
>
> Maybe the term "serial" makes more sense which will lead to
> fsl,tsa-serial = <&tsa, SCC4>;
Yes, that's better. Thanks.
Best regards,
Krzysztof