LinuxLists.cc - [PATCH 00/18] arm64: qcom: add support for sa8775p-ride

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Subject: [PATCH 11/18] arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P platforms

From: Bartosz Golaszewski <[email protected]>

Enable the Qualcomm SA8775P TLMM pinctrl and GPIO driver. It needs to be
built-in for UART to provide a console.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d5c938adbd2d..6c752b9a4565 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -555,6 +555,7 @@ CONFIG_PINCTRL_QCM2290=y
CONFIG_PINCTRL_QCS404=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_PINCTRL_SA8775P=y
CONFIG_PINCTRL_SC7180=y
CONFIG_PINCTRL_SC7280=y
CONFIG_PINCTRL_SC8180X=y
--
2.37.2

2023-01-09 17:58:34

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Subject: [PATCH 12/18] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform

From: Bartosz Golaszewski <[email protected]>

Add a compatible for the ipcc on sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index f5c73437fef4..de56640cecca 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,sa8775p-ipcc
- qcom,sc7280-ipcc
- qcom,sc8280xp-ipcc
- qcom,sm6350-ipcc
--
2.37.2

2023-01-09 18:00:08

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Subject: [PATCH 01/18] dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p

From: Bartosz Golaszewski <[email protected]>

Add DT bindings for the GCC clock on SA8775P platforms. Add relevant
DT include definitions as well.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
.../bindings/clock/qcom,gcc-sa8775p.yaml | 77 +++++
include/dt-bindings/clock/qcom,gcc-sa8775p.h | 320 ++++++++++++++++++
2 files changed, 397 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
new file mode 100644
index 000000000000..35d92d94495a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sa8775p.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on sa8775p
+
+maintainers:
+ - Bartosz Golaszewski <[email protected]>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and
+ power domains on sa8775p.
+
+ See also:: include/dt-bindings/clock/qcom,gcc-sa8775p.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sa8775p
+
+ clocks:
+ items:
+ - description: XO reference clock
+ - description: Sleep clock
+ - description: UFS memory first RX symbol clock
+ - description: UFS memory second RX symbol clock
+ - description: UFS memory first TX symbol clock
+ - description: UFS card first RX symbol clock
+ - description: UFS card second RX symbol clock
+ - description: UFS card first TX symbol clock
+ - description: Primary USB3 PHY wrapper pipe clock
+ - description: Secondary USB3 PHY wrapper pipe clock
+ - description: PCIe 0 pipe clock
+ - description: PCIe 1 pipe clock
+ - description: PCIe PHY clock
+ - description: First EMAC controller reference clock
+ - description: Second EMAC controller reference clock
+
+ protected-clocks:
+ maxItems: 240
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sa8775p";
+ reg = <0x100000 0xc7018>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&usb_0_ssphy>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-sa8775p.h b/include/dt-bindings/clock/qcom,gcc-sa8775p.h
new file mode 100644
index 000000000000..badc253379c9
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sa8775p.h
@@ -0,0 +1,320 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H
+
+/* GCC clocks */
+#define GCC_GPLL0 0
+#define GCC_GPLL0_OUT_EVEN 1
+#define GCC_GPLL1 2
+#define GCC_GPLL4 3
+#define GCC_GPLL5 4
+#define GCC_GPLL7 5
+#define GCC_GPLL9 6
+#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 8
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
+#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 12
+#define GCC_AHB2PHY0_CLK 13
+#define GCC_AHB2PHY2_CLK 14
+#define GCC_AHB2PHY3_CLK 15
+#define GCC_BOOT_ROM_AHB_CLK 16
+#define GCC_CAMERA_AHB_CLK 17
+#define GCC_CAMERA_HF_AXI_CLK 18
+#define GCC_CAMERA_SF_AXI_CLK 19
+#define GCC_CAMERA_THROTTLE_XO_CLK 20
+#define GCC_CAMERA_XO_CLK 21
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24
+#define GCC_DDRSS_GPU_AXI_CLK 25
+#define GCC_DISP1_AHB_CLK 26
+#define GCC_DISP1_HF_AXI_CLK 27
+#define GCC_DISP1_XO_CLK 28
+#define GCC_DISP_AHB_CLK 29
+#define GCC_DISP_HF_AXI_CLK 30
+#define GCC_DISP_XO_CLK 31
+#define GCC_EDP_REF_CLKREF_EN 32
+#define GCC_EMAC0_AXI_CLK 33
+#define GCC_EMAC0_PHY_AUX_CLK 34
+#define GCC_EMAC0_PHY_AUX_CLK_SRC 35
+#define GCC_EMAC0_PTP_CLK 36
+#define GCC_EMAC0_PTP_CLK_SRC 37
+#define GCC_EMAC0_RGMII_CLK 38
+#define GCC_EMAC0_RGMII_CLK_SRC 39
+#define GCC_EMAC0_SLV_AHB_CLK 40
+#define GCC_EMAC1_AXI_CLK 41
+#define GCC_EMAC1_PHY_AUX_CLK 42
+#define GCC_EMAC1_PHY_AUX_CLK_SRC 43
+#define GCC_EMAC1_PTP_CLK 44
+#define GCC_EMAC1_PTP_CLK_SRC 45
+#define GCC_EMAC1_RGMII_CLK 46
+#define GCC_EMAC1_RGMII_CLK_SRC 47
+#define GCC_EMAC1_SLV_AHB_CLK 48
+#define GCC_GP1_CLK 49
+#define GCC_GP1_CLK_SRC 50
+#define GCC_GP2_CLK 51
+#define GCC_GP2_CLK_SRC 52
+#define GCC_GP3_CLK 53
+#define GCC_GP3_CLK_SRC 54
+#define GCC_GP4_CLK 55
+#define GCC_GP4_CLK_SRC 56
+#define GCC_GP5_CLK 57
+#define GCC_GP5_CLK_SRC 58
+#define GCC_GPU_CFG_AHB_CLK 59
+#define GCC_GPU_GPLL0_CLK_SRC 60
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 61
+#define GCC_GPU_MEMNOC_GFX_CLK 62
+#define GCC_GPU_SNOC_DVM_GFX_CLK 63
+#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64
+#define GCC_GPU_TCU_THROTTLE_CLK 65
+#define GCC_PCIE_0_AUX_CLK 66
+#define GCC_PCIE_0_AUX_CLK_SRC 67
+#define GCC_PCIE_0_CFG_AHB_CLK 68
+#define GCC_PCIE_0_MSTR_AXI_CLK 69
+#define GCC_PCIE_0_PHY_AUX_CLK 70
+#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71
+#define GCC_PCIE_0_PHY_RCHNG_CLK 72
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73
+#define GCC_PCIE_0_PIPE_CLK 74
+#define GCC_PCIE_0_PIPE_CLK_SRC 75
+#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76
+#define GCC_PCIE_0_PIPEDIV2_CLK 77
+#define GCC_PCIE_0_SLV_AXI_CLK 78
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79
+#define GCC_PCIE_1_AUX_CLK 80
+#define GCC_PCIE_1_AUX_CLK_SRC 81
+#define GCC_PCIE_1_CFG_AHB_CLK 82
+#define GCC_PCIE_1_MSTR_AXI_CLK 83
+#define GCC_PCIE_1_PHY_AUX_CLK 84
+#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85
+#define GCC_PCIE_1_PHY_RCHNG_CLK 86
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87
+#define GCC_PCIE_1_PIPE_CLK 88
+#define GCC_PCIE_1_PIPE_CLK_SRC 89
+#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90
+#define GCC_PCIE_1_PIPEDIV2_CLK 91
+#define GCC_PCIE_1_SLV_AXI_CLK 92
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93
+#define GCC_PCIE_CLKREF_EN 94
+#define GCC_PCIE_THROTTLE_CFG_CLK 95
+#define GCC_PDM2_CLK 96
+#define GCC_PDM2_CLK_SRC 97
+#define GCC_PDM_AHB_CLK 98
+#define GCC_PDM_XO4_CLK 99
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 101
+#define GCC_QMIP_DISP1_AHB_CLK 102
+#define GCC_QMIP_DISP1_ROT_AHB_CLK 103
+#define GCC_QMIP_DISP_AHB_CLK 104
+#define GCC_QMIP_DISP_ROT_AHB_CLK 105
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107
+#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109
+#define GCC_QUPV3_WRAP0_CORE_CLK 110
+#define GCC_QUPV3_WRAP0_S0_CLK 111
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112
+#define GCC_QUPV3_WRAP0_S1_CLK 113
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114
+#define GCC_QUPV3_WRAP0_S2_CLK 115
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116
+#define GCC_QUPV3_WRAP0_S3_CLK 117
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118
+#define GCC_QUPV3_WRAP0_S4_CLK 119
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120
+#define GCC_QUPV3_WRAP0_S5_CLK 121
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122
+#define GCC_QUPV3_WRAP0_S6_CLK 123
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125
+#define GCC_QUPV3_WRAP1_CORE_CLK 126
+#define GCC_QUPV3_WRAP1_S0_CLK 127
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128
+#define GCC_QUPV3_WRAP1_S1_CLK 129
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130
+#define GCC_QUPV3_WRAP1_S2_CLK 131
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132
+#define GCC_QUPV3_WRAP1_S3_CLK 133
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134
+#define GCC_QUPV3_WRAP1_S4_CLK 135
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136
+#define GCC_QUPV3_WRAP1_S5_CLK 137
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138
+#define GCC_QUPV3_WRAP1_S6_CLK 139
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141
+#define GCC_QUPV3_WRAP2_CORE_CLK 142
+#define GCC_QUPV3_WRAP2_S0_CLK 143
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144
+#define GCC_QUPV3_WRAP2_S1_CLK 145
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146
+#define GCC_QUPV3_WRAP2_S2_CLK 147
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148
+#define GCC_QUPV3_WRAP2_S3_CLK 149
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150
+#define GCC_QUPV3_WRAP2_S4_CLK 151
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152
+#define GCC_QUPV3_WRAP2_S5_CLK 153
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154
+#define GCC_QUPV3_WRAP2_S6_CLK 155
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157
+#define GCC_QUPV3_WRAP3_CORE_CLK 158
+#define GCC_QUPV3_WRAP3_QSPI_CLK 159
+#define GCC_QUPV3_WRAP3_S0_CLK 160
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161
+#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170
+#define GCC_SDCC1_AHB_CLK 171
+#define GCC_SDCC1_APPS_CLK 172
+#define GCC_SDCC1_APPS_CLK_SRC 173
+#define GCC_SDCC1_ICE_CORE_CLK 174
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 175
+#define GCC_SGMI_CLKREF_EN 176
+#define GCC_TSCSS_AHB_CLK 177
+#define GCC_TSCSS_CNTR_CLK_SRC 178
+#define GCC_TSCSS_ETU_CLK 179
+#define GCC_TSCSS_GLOBAL_CNTR_CLK 180
+#define GCC_UFS_CARD_AHB_CLK 181
+#define GCC_UFS_CARD_AXI_CLK 182
+#define GCC_UFS_CARD_AXI_CLK_SRC 183
+#define GCC_UFS_CARD_ICE_CORE_CLK 184
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185
+#define GCC_UFS_CARD_PHY_AUX_CLK 186
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195
+#define GCC_UFS_PHY_AHB_CLK 196
+#define GCC_UFS_PHY_AXI_CLK 197
+#define GCC_UFS_PHY_AXI_CLK_SRC 198
+#define GCC_UFS_PHY_ICE_CORE_CLK 199
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200
+#define GCC_UFS_PHY_PHY_AUX_CLK 201
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210
+#define GCC_USB20_MASTER_CLK 211
+#define GCC_USB20_MASTER_CLK_SRC 212
+#define GCC_USB20_MOCK_UTMI_CLK 213
+#define GCC_USB20_MOCK_UTMI_CLK_SRC 214
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215
+#define GCC_USB20_SLEEP_CLK 216
+#define GCC_USB30_PRIM_MASTER_CLK 217
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 218
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221
+#define GCC_USB30_PRIM_SLEEP_CLK 222
+#define GCC_USB30_SEC_MASTER_CLK 223
+#define GCC_USB30_SEC_MASTER_CLK_SRC 224
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 225
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227
+#define GCC_USB30_SEC_SLEEP_CLK 228
+#define GCC_USB3_PRIM_PHY_AUX_CLK 229
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 232
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233
+#define GCC_USB3_SEC_PHY_AUX_CLK 234
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236
+#define GCC_USB3_SEC_PHY_PIPE_CLK 237
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238
+#define GCC_USB_CLKREF_EN 239
+#define GCC_VIDEO_AHB_CLK 240
+#define GCC_VIDEO_AXI0_CLK 241
+#define GCC_VIDEO_AXI1_CLK 242
+#define GCC_VIDEO_XO_CLK 243
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248
+
+/* GCC resets */
+#define GCC_CAMERA_BCR 0
+#define GCC_DISPLAY1_BCR 1
+#define GCC_DISPLAY_BCR 2
+#define GCC_EMAC0_BCR 3
+#define GCC_EMAC1_BCR 4
+#define GCC_GPU_BCR 5
+#define GCC_MMSS_BCR 6
+#define GCC_PCIE_0_BCR 7
+#define GCC_PCIE_0_LINK_DOWN_BCR 8
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_0_PHY_BCR 10
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11
+#define GCC_PCIE_1_BCR 12
+#define GCC_PCIE_1_LINK_DOWN_BCR 13
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14
+#define GCC_PCIE_1_PHY_BCR 15
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16
+#define GCC_PDM_BCR 17
+#define GCC_QUPV3_WRAPPER_0_BCR 18
+#define GCC_QUPV3_WRAPPER_1_BCR 19
+#define GCC_QUPV3_WRAPPER_2_BCR 20
+#define GCC_QUPV3_WRAPPER_3_BCR 21
+#define GCC_SDCC1_BCR 22
+#define GCC_TSCSS_BCR 23
+#define GCC_UFS_CARD_BCR 24
+#define GCC_UFS_PHY_BCR 25
+#define GCC_USB20_PRIM_BCR 26
+#define GCC_USB2_PHY_PRIM_BCR 27
+#define GCC_USB2_PHY_SEC_BCR 28
+#define GCC_USB30_PRIM_BCR 29
+#define GCC_USB30_SEC_BCR 30
+#define GCC_USB3_DP_PHY_PRIM_BCR 31
+#define GCC_USB3_DP_PHY_SEC_BCR 32
+#define GCC_USB3_PHY_PRIM_BCR 33
+#define GCC_USB3_PHY_SEC_BCR 34
+#define GCC_USB3_PHY_TERT_BCR 35
+#define GCC_USB3_UNIPHY_MP0_BCR 36
+#define GCC_USB3_UNIPHY_MP1_BCR 37
+#define GCC_USB3PHY_PHY_PRIM_BCR 38
+#define GCC_USB3PHY_PHY_SEC_BCR 39
+#define GCC_USB3UNIPHY_PHY_MP0_BCR 40
+#define GCC_USB3UNIPHY_PHY_MP1_BCR 41
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
+#define GCC_VIDEO_BCR 43
+#define GCC_VIDEO_AXI0_CLK_ARES 44
+#define GCC_VIDEO_AXI1_CLK_ARES 45
+
+/* GCC GDSCs */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define UFS_CARD_GDSC 2
+#define UFS_PHY_GDSC 3
+#define USB20_PRIM_GDSC 4
+#define USB30_PRIM_GDSC 5
+#define USB30_SEC_GDSC 6
+#define EMAC0_GDSC 7
+#define EMAC1_GDSC 8
+
+#endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */
--
2.37.2

2023-01-09 18:11:01

[permalink] [raw]

Subject: [PATCH 18/18] arm64: dts: qcom: add initial support for qcom sa8775p-ride

From: Bartosz Golaszewski <[email protected]>

This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
SoC and enable booting to shell.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 +
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 ++++++++++++++++++++++
3 files changed, 881 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 3e79496292e7..39b8206f7131 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
new file mode 100644
index 000000000000..d4dae32a84cc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+
+/ {
+ model = "Qualcomm SA8875P Ride";
+ compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
+
+ aliases {
+ serial0 = &uart10;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&uart10 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart10_state>;
+};
+
+&tlmm {
+ qup_uart10_state: qup_uart10_state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
new file mode 100644
index 000000000000..1a3b11628e38
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -0,0 +1,841 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sa8775p.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L2_4>;
+ L2_4: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_1>;
+ L3_1: l3-cache {
+ compatible = "cache";
+ };
+
+ };
+ };
+
+ CPU5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_5>;
+ L2_5: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_1>;
+ };
+ };
+
+ CPU6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_6>;
+ L2_6: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_1>;
+ };
+ };
+
+ CPU7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_7>;
+ L2_7: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ /* Will be updated by the bootloader. */
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sail_ss_mem: sail_ss_region@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x10000000>;
+ };
+
+ hyp_mem: hyp_region@90000000 {
+ no-map;
+ reg = <0x0 0x90000000 0x0 0x600000>;
+ };
+
+ xbl_boot_mem: xbl_boot_region@90600000 {
+ no-map;
+ reg = <0x0 0x90600000 0x0 0x200000>;
+ };
+
+ aop_image_mem: aop_image_region@90800000 {
+ no-map;
+ reg = <0x0 0x90800000 0x0 0x60000>;
+ };
+
+ aop_cmd_db_mem: aop_cmd_db_region@90860000 {
+ compatible = "qcom,cmd-db";
+ no-map;
+ reg = <0x0 0x90860000 0x0 0x20000>;
+ };
+
+ uefi_log: uefi_log_region@908b0000 {
+ no-map;
+ reg = <0x0 0x908b0000 0x0 0x10000>;
+ };
+
+ reserved_mem: reserved_region@908f0000 {
+ no-map;
+ reg = <0x0 0x908f0000 0x0 0xf000>;
+ };
+
+ secdata_apss_mem: secdata_apss_region@908ff000 {
+ no-map;
+ reg = <0x0 0x908ff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@90900000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x90900000 0x0 0x200000>;
+ no-map;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ cpucp_fw_mem: cpucp_fw_region@90b00000 {
+ no-map;
+ reg = <0x0 0x90b00000 0x0 0x100000>;
+ };
+
+ lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 {
+ no-map;
+ reg = <0x0 0x93b00000 0x0 0xf00000>;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 {
+ no-map;
+ reg = <0x0 0x94a00000 0x0 0x800000>;
+ };
+
+ pil_camera_mem: pil_camera_region@95200000 {
+ no-map;
+ reg = <0x0 0x95200000 0x0 0x500000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@95c00000 {
+ no-map;
+ reg = <0x0 0x95c00000 0x0 0x1e00000>;
+ };
+
+ pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
+ no-map;
+ reg = <0x0 0x97b00000 0x0 0x1e00000>;
+ };
+
+ pil_gdsp1_mem: pil_gdsp1_region@99900000 {
+ no-map;
+ reg = <0x0 0x99900000 0x0 0x1e00000>;
+ };
+
+ pil_cdsp0_mem: pil_cdsp0_region@9b800000 {
+ no-map;
+ reg = <0x0 0x9b800000 0x0 0x1e00000>;
+ };
+
+ pil_gpu_mem: pil_gpu_region@9d600000 {
+ no-map;
+ reg = <0x0 0x9d600000 0x0 0x2000>;
+ };
+
+ pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
+ no-map;
+ reg = <0x0 0x9d700000 0x0 0x1e00000>;
+ };
+
+ pil_cvp_mem: pil_cvp_region@9f500000 {
+ no-map;
+ reg = <0x0 0x9f500000 0x0 0x700000>;
+ };
+
+ pil_video_mem: pil_video_region@9fc00000 {
+ no-map;
+ reg = <0x0 0x9fc00000 0x0 0x700000>;
+ };
+
+ hyptz_reserved_mem: hyptz_reserved_region@beb00000 {
+ no-map;
+ reg = <0x0 0xbeb00000 0x0 0x11500000>;
+ };
+
+ tz_stat_mem: tz_stat_region@d0000000 {
+ no-map;
+ reg = <0x0 0xd0000000 0x0 0x100000>;
+ };
+
+ tags_mem: tags_region@d0100000 {
+ no-map;
+ reg = <0x0 0xd0100000 0x0 0x1200000>;
+ };
+
+ qtee_mem: qtee_region@d1300000 {
+ no-map;
+ reg = <0x0 0xd1300000 0x0 0x500000>;
+ };
+
+ trusted_apps_mem: trusted_apps_region@d1800000 {
+ no-map;
+ reg = <0x0 0xd1800000 0x0 0x3900000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x3000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm";
+ };
+ };
+
+ qup_opp_table_100mhz: qup-100mhz-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sa8775p";
+ reg = <0x100000 0xc7018>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>, /* TODO: usb_0_ssphy */
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ ipcc: mailbox@408000 {
+ compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
+ reg = <0x408000 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ aggre1_noc:interconnect-aggre1-noc {
+ compatible = "qcom,sa8775p-aggre1-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect-aggre2-noc {
+ compatible = "qcom,sa8775p-aggre2-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ clk_virt: interconnect-clk-virt {
+ compatible = "qcom,sa8775p-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ config_noc: interconnect-config-noc {
+ compatible = "qcom,sa8775p-config-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ dc_noc: interconnect-dc-noc {
+ compatible = "qcom,sa8775p-dc-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect-gem-noc {
+ compatible = "qcom,sa8775p-gem-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpdsp_anoc: interconnect-gpdsp-anoc {
+ compatible = "qcom,sa8775p-gpdsp-anoc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect-lpass-ag-noc {
+ compatible = "qcom,sa8775p-lpass-ag-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-mc-virt {
+ compatible = "qcom,sa8775p-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect-mmss-noc {
+ compatible = "qcom,sa8775p-mmss-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ nspa_noc: interconnect-nspa-noc {
+ compatible = "qcom,sa8775p-nspa-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ nspb_noc: interconnect-nspb-noc {
+ compatible = "qcom,sa8775p-nspb-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_anoc: interconnect-pcie-anoc {
+ compatible = "qcom,sa8775p-pcie-anoc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect-system-noc {
+ compatible = "qcom,sa8775p-system-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17a60000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 0>;
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sa8775p-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board_clk>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sa8775p-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ arch_timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ memtimer: timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17c20000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c27000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x1f40000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,sa8775p-pinctrl";
+ reg = <0xf000000 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 149>;
+ };
+
+ qcom-wdt@17c10000 {
+ compatible = "qcom,kpss-wdt";
+ reg = <0x17c10000 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0xac0000 0x6000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x443 0x0>;
+ status = "disabled";
+
+ uart10: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0xa8c000 0x4000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ status = "disabled";
+ };
+ };
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
+ reg = <0x15000000 0x100000>, <0x15182000 0x28>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <2>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
--
2.37.2

2023-01-09 18:11:14

[permalink] [raw]

Subject: [PATCH 07/18] interconnect: qcom: add a driver for sa8775p

From: Shazad Hussain <[email protected]>

Introduce QTI SA8775P-specific interconnect driver.

Signed-off-by: Shazad Hussain <[email protected]>
[Bartosz: made the driver ready for upstream]
Co-developed-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/sa8775p.c | 2542 +++++++++++++++++++++++++++
3 files changed, 2553 insertions(+)
create mode 100644 drivers/interconnect/qcom/sa8775p.c

diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 1a1c941635a2..023e42ebe365 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -83,6 +83,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE
config INTERCONNECT_QCOM_RPMH
tristate

+config INTERCONNECT_QCOM_SA8775P
+ tristate "Qualcomm SA8775P interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
+ platforms.
+
config INTERCONNECT_QCOM_SC7180
tristate "Qualcomm SC7180 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 8e357528185d..32d90ff7960e 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -12,6 +12,7 @@ icc-osm-l3-objs := osm-l3.o
qnoc-qcm2290-objs := qcm2290.o
qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
+qnoc-sa8775p-objs := sa8775p.o
qnoc-sc7180-objs := sc7180.o
qnoc-sc7280-objs := sc7280.o
qnoc-sc8180x-objs := sc8180x.o
@@ -36,6 +37,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
new file mode 100644
index 000000000000..bb23234eaad5
--- /dev/null
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -0,0 +1,2542 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,sa8775p.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+#define LEMANS_MASTER_GPU_TCU 0
+#define LEMANS_MASTER_PCIE_TCU 1
+#define LEMANS_MASTER_SYS_TCU 2
+#define LEMANS_MASTER_APPSS_PROC 3
+#define LEMANS_MASTER_LLCC 4
+#define LEMANS_MASTER_CNOC_LPASS_AG_NOC 5
+#define LEMANS_MASTER_GIC_AHB 6
+#define LEMANS_MASTER_CDSP_NOC_CFG 7
+#define LEMANS_MASTER_CDSPB_NOC_CFG 8
+#define LEMANS_MASTER_QDSS_BAM 9
+#define LEMANS_MASTER_QUP_0 10
+#define LEMANS_MASTER_QUP_1 11
+#define LEMANS_MASTER_QUP_2 12
+#define LEMANS_MASTER_A1NOC_SNOC 13
+#define LEMANS_MASTER_A2NOC_SNOC 14
+#define LEMANS_MASTER_CAMNOC_HF 15
+#define LEMANS_MASTER_CAMNOC_ICP 16
+#define LEMANS_MASTER_CAMNOC_SF 17
+#define LEMANS_MASTER_COMPUTE_NOC 18
+#define LEMANS_MASTER_COMPUTE_NOC_1 19
+#define LEMANS_MASTER_CNOC_A2NOC 20
+#define LEMANS_MASTER_CNOC_DC_NOC 21
+#define LEMANS_MASTER_GEM_NOC_CFG 22
+#define LEMANS_MASTER_GEM_NOC_CNOC 23
+#define LEMANS_MASTER_GEM_NOC_PCIE_SNOC 24
+#define LEMANS_MASTER_GPDSP_SAIL 25
+#define LEMANS_MASTER_GFX3D 26
+#define LEMANS_MASTER_LPASS_ANOC 27
+#define LEMANS_MASTER_MDP0 28
+#define LEMANS_MASTER_MDP1 29
+#define LEMANS_MASTER_MDP_CORE1_0 30
+#define LEMANS_MASTER_MDP_CORE1_1 31
+#define LEMANS_MASTER_MNOC_HF_MEM_NOC 32
+#define LEMANS_MASTER_CNOC_MNOC_HF_CFG 33
+#define LEMANS_MASTER_MNOC_SF_MEM_NOC 34
+#define LEMANS_MASTER_CNOC_MNOC_SF_CFG 35
+#define LEMANS_MASTER_ANOC_PCIE_GEM_NOC 36
+#define LEMANS_MASTER_SNOC_CFG 37
+#define LEMANS_MASTER_SNOC_GC_MEM_NOC 38
+#define LEMANS_MASTER_SNOC_SF_MEM_NOC 39
+#define LEMANS_MASTER_VIDEO_P0 40
+#define LEMANS_MASTER_VIDEO_P1 41
+#define LEMANS_MASTER_VIDEO_PROC 42
+#define LEMANS_MASTER_VIDEO_V_PROC 43
+#define LEMANS_MASTER_QUP_CORE_0 44
+#define LEMANS_MASTER_QUP_CORE_1 45
+#define LEMANS_MASTER_QUP_CORE_2 46
+#define LEMANS_MASTER_QUP_CORE_3 47
+#define LEMANS_MASTER_CRYPTO_CORE0 48
+#define LEMANS_MASTER_CRYPTO_CORE1 49
+#define LEMANS_MASTER_DSP0 50
+#define LEMANS_MASTER_DSP1 51
+#define LEMANS_MASTER_IPA 52
+#define LEMANS_MASTER_LPASS_PROC 53
+#define LEMANS_MASTER_CDSP_PROC 54
+#define LEMANS_MASTER_CDSP_PROC_B 55
+#define LEMANS_MASTER_PIMEM 56
+#define LEMANS_MASTER_QUP_3 57
+#define LEMANS_MASTER_EMAC 58
+#define LEMANS_MASTER_EMAC_1 59
+#define LEMANS_MASTER_GIC 60
+#define LEMANS_MASTER_PCIE_0 61
+#define LEMANS_MASTER_PCIE_1 62
+#define LEMANS_MASTER_QDSS_ETR_0 63
+#define LEMANS_MASTER_QDSS_ETR_1 64
+#define LEMANS_MASTER_SDC 65
+#define LEMANS_MASTER_UFS_CARD 66
+#define LEMANS_MASTER_UFS_MEM 67
+#define LEMANS_MASTER_USB2 68
+#define LEMANS_MASTER_USB3_0 69
+#define LEMANS_MASTER_USB3_1 70
+#define LEMANS_SLAVE_EBI1 512
+#define LEMANS_SLAVE_AHB2PHY_0 513
+#define LEMANS_SLAVE_AHB2PHY_1 514
+#define LEMANS_SLAVE_AHB2PHY_2 515
+#define LEMANS_SLAVE_AHB2PHY_3 516
+#define LEMANS_SLAVE_ANOC_THROTTLE_CFG 517
+#define LEMANS_SLAVE_AOSS 518
+#define LEMANS_SLAVE_APPSS 519
+#define LEMANS_SLAVE_BOOT_ROM 520
+#define LEMANS_SLAVE_CAMERA_CFG 521
+#define LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG 522
+#define LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG 523
+#define LEMANS_SLAVE_CLK_CTL 524
+#define LEMANS_SLAVE_CDSP_CFG 525
+#define LEMANS_SLAVE_CDSP1_CFG 526
+#define LEMANS_SLAVE_RBCPR_CX_CFG 527
+#define LEMANS_SLAVE_RBCPR_MMCX_CFG 528
+#define LEMANS_SLAVE_RBCPR_MX_CFG 529
+#define LEMANS_SLAVE_CPR_NSPCX 530
+#define LEMANS_SLAVE_CRYPTO_0_CFG 531
+#define LEMANS_SLAVE_CX_RDPM 532
+#define LEMANS_SLAVE_DISPLAY_CFG 533
+#define LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG 534
+#define LEMANS_SLAVE_DISPLAY1_CFG 535
+#define LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536
+#define LEMANS_SLAVE_EMAC_CFG 537
+#define LEMANS_SLAVE_EMAC1_CFG 538
+#define LEMANS_SLAVE_GP_DSP0_CFG 539
+#define LEMANS_SLAVE_GP_DSP1_CFG 540
+#define LEMANS_SLAVE_GPDSP0_THROTTLE_CFG 541
+#define LEMANS_SLAVE_GPDSP1_THROTTLE_CFG 542
+#define LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG 543
+#define LEMANS_SLAVE_GFX3D_CFG 544
+#define LEMANS_SLAVE_HWKM 545
+#define LEMANS_SLAVE_IMEM_CFG 546
+#define LEMANS_SLAVE_IPA_CFG 547
+#define LEMANS_SLAVE_IPC_ROUTER_CFG 548
+#define LEMANS_SLAVE_LLCC_CFG 549
+#define LEMANS_SLAVE_LPASS 550
+#define LEMANS_SLAVE_LPASS_CORE_CFG 551
+#define LEMANS_SLAVE_LPASS_LPI_CFG 552
+#define LEMANS_SLAVE_LPASS_MPU_CFG 553
+#define LEMANS_SLAVE_LPASS_THROTTLE_CFG 554
+#define LEMANS_SLAVE_LPASS_TOP_CFG 555
+#define LEMANS_SLAVE_MX_RDPM 556
+#define LEMANS_SLAVE_MXC_RDPM 557
+#define LEMANS_SLAVE_PCIE_0_CFG 558
+#define LEMANS_SLAVE_PCIE_1_CFG 559
+#define LEMANS_SLAVE_PCIE_RSC_CFG 560
+#define LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG 561
+#define LEMANS_SLAVE_PCIE_THROTTLE_CFG 562
+#define LEMANS_SLAVE_PDM 563
+#define LEMANS_SLAVE_PIMEM_CFG 564
+#define LEMANS_SLAVE_PKA_WRAPPER_CFG 565
+#define LEMANS_SLAVE_QDSS_CFG 566
+#define LEMANS_SLAVE_QM_CFG 567
+#define LEMANS_SLAVE_QM_MPU_CFG 568
+#define LEMANS_SLAVE_QUP_0 569
+#define LEMANS_SLAVE_QUP_1 570
+#define LEMANS_SLAVE_QUP_2 571
+#define LEMANS_SLAVE_QUP_3 572
+#define LEMANS_SLAVE_SAIL_THROTTLE_CFG 573
+#define LEMANS_SLAVE_SDC1 574
+#define LEMANS_SLAVE_SECURITY 575
+#define LEMANS_SLAVE_SNOC_THROTTLE_CFG 576
+#define LEMANS_SLAVE_TCSR 577
+#define LEMANS_SLAVE_TLMM 578
+#define LEMANS_SLAVE_TSC_CFG 579
+#define LEMANS_SLAVE_UFS_CARD_CFG 580
+#define LEMANS_SLAVE_UFS_MEM_CFG 581
+#define LEMANS_SLAVE_USB2 582
+#define LEMANS_SLAVE_USB3_0 583
+#define LEMANS_SLAVE_USB3_1 584
+#define LEMANS_SLAVE_VENUS_CFG 585
+#define LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG 586
+#define LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587
+#define LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588
+#define LEMANS_SLAVE_A1NOC_SNOC 589
+#define LEMANS_SLAVE_A2NOC_SNOC 590
+#define LEMANS_SLAVE_DDRSS_CFG 591
+#define LEMANS_SLAVE_GEM_NOC_CNOC 592
+#define LEMANS_SLAVE_GEM_NOC_CFG 593
+#define LEMANS_SLAVE_SNOC_GEM_NOC_GC 594
+#define LEMANS_SLAVE_SNOC_GEM_NOC_SF 595
+#define LEMANS_SLAVE_GP_DSP_SAIL_NOC 596
+#define LEMANS_SLAVE_GPDSP_NOC_CFG 597
+#define LEMANS_SLAVE_HCP_A 598
+#define LEMANS_SLAVE_LLCC 599
+#define LEMANS_SLAVE_MNOC_HF_MEM_NOC 600
+#define LEMANS_SLAVE_MNOC_SF_MEM_NOC 601
+#define LEMANS_SLAVE_CNOC_MNOC_HF_CFG 602
+#define LEMANS_SLAVE_CNOC_MNOC_SF_CFG 603
+#define LEMANS_SLAVE_CDSP_MEM_NOC 604
+#define LEMANS_SLAVE_CDSPB_MEM_NOC 605
+#define LEMANS_SLAVE_HCP_B 606
+#define LEMANS_SLAVE_GEM_NOC_PCIE_CNOC 607
+#define LEMANS_SLAVE_PCIE_ANOC_CFG 608
+#define LEMANS_SLAVE_ANOC_PCIE_GEM_NOC 609
+#define LEMANS_SLAVE_SNOC_CFG 610
+#define LEMANS_SLAVE_LPASS_SNOC 611
+#define LEMANS_SLAVE_QUP_CORE_0 612
+#define LEMANS_SLAVE_QUP_CORE_1 613
+#define LEMANS_SLAVE_QUP_CORE_2 614
+#define LEMANS_SLAVE_QUP_CORE_3 615
+#define LEMANS_SLAVE_BOOT_IMEM 616
+#define LEMANS_SLAVE_IMEM 617
+#define LEMANS_SLAVE_PIMEM 618
+#define LEMANS_SLAVE_SERVICE_NSP_NOC 619
+#define LEMANS_SLAVE_SERVICE_NSPB_NOC 620
+#define LEMANS_SLAVE_SERVICE_GEM_NOC_1 621
+#define LEMANS_SLAVE_SERVICE_MNOC_HF 622
+#define LEMANS_SLAVE_SERVICE_MNOC_SF 623
+#define LEMANS_SLAVE_SERVICES_LPASS_AML_NOC 624
+#define LEMANS_SLAVE_SERVICE_LPASS_AG_NOC 625
+#define LEMANS_SLAVE_SERVICE_GEM_NOC_2 626
+#define LEMANS_SLAVE_SERVICE_SNOC 627
+#define LEMANS_SLAVE_SERVICE_GEM_NOC 628
+#define LEMANS_SLAVE_SERVICE_GEM_NOC2 629
+#define LEMANS_SLAVE_PCIE_0 630
+#define LEMANS_SLAVE_PCIE_1 631
+#define LEMANS_SLAVE_QDSS_STM 632
+#define LEMANS_SLAVE_TCU 633
+
+static struct qcom_icc_node qxm_qup3 = {
+ .name = "qxm_qup3",
+ .id = LEMANS_MASTER_QUP_3,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_emac_0 = {
+ .name = "xm_emac_0",
+ .id = LEMANS_MASTER_EMAC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_emac_1 = {
+ .name = "xm_emac_1",
+ .id = LEMANS_MASTER_EMAC_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_sdc1 = {
+ .name = "xm_sdc1",
+ .id = LEMANS_MASTER_SDC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_ufs_mem = {
+ .name = "xm_ufs_mem",
+ .id = LEMANS_MASTER_UFS_MEM,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_usb2_2 = {
+ .name = "xm_usb2_2",
+ .id = LEMANS_MASTER_USB2,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_usb3_0 = {
+ .name = "xm_usb3_0",
+ .id = LEMANS_MASTER_USB3_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_usb3_1 = {
+ .name = "xm_usb3_1",
+ .id = LEMANS_MASTER_USB3_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node qhm_qdss_bam = {
+ .name = "qhm_qdss_bam",
+ .id = LEMANS_MASTER_QDSS_BAM,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qhm_qup0 = {
+ .name = "qhm_qup0",
+ .id = LEMANS_MASTER_QUP_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qhm_qup1 = {
+ .name = "qhm_qup1",
+ .id = LEMANS_MASTER_QUP_1,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qhm_qup2 = {
+ .name = "qhm_qup2",
+ .id = LEMANS_MASTER_QUP_2,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qnm_cnoc_datapath = {
+ .name = "qnm_cnoc_datapath",
+ .id = LEMANS_MASTER_CNOC_A2NOC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qxm_crypto_0 = {
+ .name = "qxm_crypto_0",
+ .id = LEMANS_MASTER_CRYPTO_CORE0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qxm_crypto_1 = {
+ .name = "qxm_crypto_1",
+ .id = LEMANS_MASTER_CRYPTO_CORE1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .id = LEMANS_MASTER_IPA,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_qdss_etr_0 = {
+ .name = "xm_qdss_etr_0",
+ .id = LEMANS_MASTER_QDSS_ETR_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_qdss_etr_1 = {
+ .name = "xm_qdss_etr_1",
+ .id = LEMANS_MASTER_QDSS_ETR_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node xm_ufs_card = {
+ .name = "xm_ufs_card",
+ .id = LEMANS_MASTER_UFS_CARD,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .id = LEMANS_MASTER_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_QUP_CORE_0 },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .id = LEMANS_MASTER_QUP_CORE_1,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_QUP_CORE_1 },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .id = LEMANS_MASTER_QUP_CORE_2,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_QUP_CORE_2 },
+};
+
+static struct qcom_icc_node qup3_core_master = {
+ .name = "qup3_core_master",
+ .id = LEMANS_MASTER_QUP_CORE_3,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_QUP_CORE_3 },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .id = LEMANS_MASTER_GEM_NOC_CNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 82,
+ .links = { LEMANS_SLAVE_AHB2PHY_0,
+ LEMANS_SLAVE_AHB2PHY_1,
+ LEMANS_SLAVE_AHB2PHY_2,
+ LEMANS_SLAVE_AHB2PHY_3,
+ LEMANS_SLAVE_ANOC_THROTTLE_CFG,
+ LEMANS_SLAVE_AOSS,
+ LEMANS_SLAVE_APPSS,
+ LEMANS_SLAVE_BOOT_ROM,
+ LEMANS_SLAVE_CAMERA_CFG,
+ LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
+ LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
+ LEMANS_SLAVE_CLK_CTL,
+ LEMANS_SLAVE_CDSP_CFG,
+ LEMANS_SLAVE_CDSP1_CFG,
+ LEMANS_SLAVE_RBCPR_CX_CFG,
+ LEMANS_SLAVE_RBCPR_MMCX_CFG,
+ LEMANS_SLAVE_RBCPR_MX_CFG,
+ LEMANS_SLAVE_CPR_NSPCX,
+ LEMANS_SLAVE_CRYPTO_0_CFG,
+ LEMANS_SLAVE_CX_RDPM,
+ LEMANS_SLAVE_DISPLAY_CFG,
+ LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
+ LEMANS_SLAVE_DISPLAY1_CFG,
+ LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
+ LEMANS_SLAVE_EMAC_CFG,
+ LEMANS_SLAVE_EMAC1_CFG,
+ LEMANS_SLAVE_GP_DSP0_CFG,
+ LEMANS_SLAVE_GP_DSP1_CFG,
+ LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
+ LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
+ LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
+ LEMANS_SLAVE_GFX3D_CFG,
+ LEMANS_SLAVE_HWKM,
+ LEMANS_SLAVE_IMEM_CFG,
+ LEMANS_SLAVE_IPA_CFG,
+ LEMANS_SLAVE_IPC_ROUTER_CFG,
+ LEMANS_SLAVE_LPASS,
+ LEMANS_SLAVE_LPASS_THROTTLE_CFG,
+ LEMANS_SLAVE_MX_RDPM,
+ LEMANS_SLAVE_MXC_RDPM,
+ LEMANS_SLAVE_PCIE_0_CFG,
+ LEMANS_SLAVE_PCIE_1_CFG,
+ LEMANS_SLAVE_PCIE_RSC_CFG,
+ LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
+ LEMANS_SLAVE_PCIE_THROTTLE_CFG,
+ LEMANS_SLAVE_PDM,
+ LEMANS_SLAVE_PIMEM_CFG,
+ LEMANS_SLAVE_PKA_WRAPPER_CFG,
+ LEMANS_SLAVE_QDSS_CFG,
+ LEMANS_SLAVE_QM_CFG,
+ LEMANS_SLAVE_QM_MPU_CFG,
+ LEMANS_SLAVE_QUP_0,
+ LEMANS_SLAVE_QUP_1,
+ LEMANS_SLAVE_QUP_2,
+ LEMANS_SLAVE_QUP_3,
+ LEMANS_SLAVE_SAIL_THROTTLE_CFG,
+ LEMANS_SLAVE_SDC1,
+ LEMANS_SLAVE_SECURITY,
+ LEMANS_SLAVE_SNOC_THROTTLE_CFG,
+ LEMANS_SLAVE_TCSR,
+ LEMANS_SLAVE_TLMM,
+ LEMANS_SLAVE_TSC_CFG,
+ LEMANS_SLAVE_UFS_CARD_CFG,
+ LEMANS_SLAVE_UFS_MEM_CFG,
+ LEMANS_SLAVE_USB2,
+ LEMANS_SLAVE_USB3_0,
+ LEMANS_SLAVE_USB3_1,
+ LEMANS_SLAVE_VENUS_CFG,
+ LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
+ LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
+ LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
+ LEMANS_SLAVE_DDRSS_CFG,
+ LEMANS_SLAVE_GPDSP_NOC_CFG,
+ LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
+ LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
+ LEMANS_SLAVE_PCIE_ANOC_CFG,
+ LEMANS_SLAVE_SNOC_CFG,
+ LEMANS_SLAVE_BOOT_IMEM,
+ LEMANS_SLAVE_IMEM,
+ LEMANS_SLAVE_PIMEM,
+ LEMANS_SLAVE_QDSS_STM,
+ LEMANS_SLAVE_TCU
+ },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .id = LEMANS_MASTER_GEM_NOC_PCIE_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_PCIE_0,
+ LEMANS_SLAVE_PCIE_1
+ },
+};
+
+static struct qcom_icc_node qnm_cnoc_dc_noc = {
+ .name = "qnm_cnoc_dc_noc",
+ .id = LEMANS_MASTER_CNOC_DC_NOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_LLCC_CFG,
+ LEMANS_SLAVE_GEM_NOC_CFG
+ },
+};
+
+static struct qcom_icc_node alm_gpu_tcu = {
+ .name = "alm_gpu_tcu",
+ .id = LEMANS_MASTER_GPU_TCU,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node alm_pcie_tcu = {
+ .name = "alm_pcie_tcu",
+ .id = LEMANS_MASTER_PCIE_TCU,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .id = LEMANS_MASTER_SYS_TCU,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .id = LEMANS_MASTER_APPSS_PROC,
+ .channels = 4,
+ .buswidth = 32,
+ .num_links = 3,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC,
+ LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
+ },
+};
+
+static struct qcom_icc_node qnm_cmpnoc0 = {
+ .name = "qnm_cmpnoc0",
+ .id = LEMANS_MASTER_COMPUTE_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node qnm_cmpnoc1 = {
+ .name = "qnm_cmpnoc1",
+ .id = LEMANS_MASTER_COMPUTE_NOC_1,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cfg = {
+ .name = "qnm_gemnoc_cfg",
+ .id = LEMANS_MASTER_GEM_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 4,
+ .links = { LEMANS_SLAVE_SERVICE_GEM_NOC_1,
+ LEMANS_SLAVE_SERVICE_GEM_NOC_2,
+ LEMANS_SLAVE_SERVICE_GEM_NOC,
+ LEMANS_SLAVE_SERVICE_GEM_NOC2
+ },
+};
+
+static struct qcom_icc_node qnm_gpdsp_sail = {
+ .name = "qnm_gpdsp_sail",
+ .id = LEMANS_MASTER_GPDSP_SAIL,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node qnm_gpu = {
+ .name = "qnm_gpu",
+ .id = LEMANS_MASTER_GFX3D,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf = {
+ .name = "qnm_mnoc_hf",
+ .id = LEMANS_MASTER_MNOC_HF_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_LLCC,
+ LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
+ },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf = {
+ .name = "qnm_mnoc_sf",
+ .id = LEMANS_MASTER_MNOC_SF_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 3,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC,
+ LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
+ },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .id = LEMANS_MASTER_ANOC_PCIE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC
+ },
+};
+
+static struct qcom_icc_node qnm_snoc_gc = {
+ .name = "qnm_snoc_gc",
+ .id = LEMANS_MASTER_SNOC_GC_MEM_NOC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_LLCC },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .id = LEMANS_MASTER_SNOC_SF_MEM_NOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
+ LEMANS_SLAVE_LLCC,
+ LEMANS_SLAVE_GEM_NOC_PCIE_CNOC },
+};
+
+static struct qcom_icc_node qxm_dsp0 = {
+ .name = "qxm_dsp0",
+ .id = LEMANS_MASTER_DSP0,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
+};
+
+static struct qcom_icc_node qxm_dsp1 = {
+ .name = "qxm_dsp1",
+ .id = LEMANS_MASTER_DSP1,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
+};
+
+static struct qcom_icc_node qhm_config_noc = {
+ .name = "qhm_config_noc",
+ .id = LEMANS_MASTER_CNOC_LPASS_AG_NOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 6,
+ .links = { LEMANS_SLAVE_LPASS_CORE_CFG,
+ LEMANS_SLAVE_LPASS_LPI_CFG,
+ LEMANS_SLAVE_LPASS_MPU_CFG,
+ LEMANS_SLAVE_LPASS_TOP_CFG,
+ LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
+ LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
+ },
+};
+
+static struct qcom_icc_node qxm_lpass_dsp = {
+ .name = "qxm_lpass_dsp",
+ .id = LEMANS_MASTER_LPASS_PROC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 4,
+ .links = { LEMANS_SLAVE_LPASS_TOP_CFG,
+ LEMANS_SLAVE_LPASS_SNOC,
+ LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
+ LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
+ },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .id = LEMANS_MASTER_LLCC,
+ .channels = 8,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_EBI1 },
+};
+
+static struct qcom_icc_node qnm_camnoc_hf = {
+ .name = "qnm_camnoc_hf",
+ .id = LEMANS_MASTER_CAMNOC_HF,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_camnoc_icp = {
+ .name = "qnm_camnoc_icp",
+ .id = LEMANS_MASTER_CAMNOC_ICP,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_camnoc_sf = {
+ .name = "qnm_camnoc_sf",
+ .id = LEMANS_MASTER_CAMNOC_SF,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mdp0_0 = {
+ .name = "qnm_mdp0_0",
+ .id = LEMANS_MASTER_MDP0,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mdp0_1 = {
+ .name = "qnm_mdp0_1",
+ .id = LEMANS_MASTER_MDP1,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mdp1_0 = {
+ .name = "qnm_mdp1_0",
+ .id = LEMANS_MASTER_MDP_CORE1_0,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mdp1_1 = {
+ .name = "qnm_mdp1_1",
+ .id = LEMANS_MASTER_MDP_CORE1_1,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf_cfg = {
+ .name = "qnm_mnoc_hf_cfg",
+ .id = LEMANS_MASTER_CNOC_MNOC_HF_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SERVICE_MNOC_HF },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf_cfg = {
+ .name = "qnm_mnoc_sf_cfg",
+ .id = LEMANS_MASTER_CNOC_MNOC_SF_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SERVICE_MNOC_SF },
+};
+
+static struct qcom_icc_node qnm_video0 = {
+ .name = "qnm_video0",
+ .id = LEMANS_MASTER_VIDEO_P0,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_video1 = {
+ .name = "qnm_video1",
+ .id = LEMANS_MASTER_VIDEO_P1,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_video_cvp = {
+ .name = "qnm_video_cvp",
+ .id = LEMANS_MASTER_VIDEO_PROC,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_video_v_cpu = {
+ .name = "qnm_video_v_cpu",
+ .id = LEMANS_MASTER_VIDEO_V_PROC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qhm_nsp_noc_config = {
+ .name = "qhm_nsp_noc_config",
+ .id = LEMANS_MASTER_CDSP_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SERVICE_NSP_NOC },
+};
+
+static struct qcom_icc_node qxm_nsp = {
+ .name = "qxm_nsp",
+ .id = LEMANS_MASTER_CDSP_PROC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
+};
+
+static struct qcom_icc_node qhm_nspb_noc_config = {
+ .name = "qhm_nspb_noc_config",
+ .id = LEMANS_MASTER_CDSPB_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SERVICE_NSPB_NOC },
+};
+
+static struct qcom_icc_node qxm_nspb = {
+ .name = "qxm_nspb",
+ .id = LEMANS_MASTER_CDSP_PROC_B,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 2,
+ .links = { LEMANS_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
+};
+
+static struct qcom_icc_node xm_pcie3_0 = {
+ .name = "xm_pcie3_0",
+ .id = LEMANS_MASTER_PCIE_0,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node xm_pcie3_1 = {
+ .name = "xm_pcie3_1",
+ .id = LEMANS_MASTER_PCIE_1,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node qhm_gic = {
+ .name = "qhm_gic",
+ .id = LEMANS_MASTER_GIC_AHB,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qnm_aggre1_noc = {
+ .name = "qnm_aggre1_noc",
+ .id = LEMANS_MASTER_A1NOC_SNOC,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qnm_aggre2_noc = {
+ .name = "qnm_aggre2_noc",
+ .id = LEMANS_MASTER_A2NOC_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qnm_lpass_noc = {
+ .name = "qnm_lpass_noc",
+ .id = LEMANS_MASTER_LPASS_ANOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qnm_snoc_cfg = {
+ .name = "qnm_snoc_cfg",
+ .id = LEMANS_MASTER_SNOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SERVICE_SNOC },
+};
+
+static struct qcom_icc_node qxm_pimem = {
+ .name = "qxm_pimem",
+ .id = LEMANS_MASTER_PIMEM,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
+};
+
+static struct qcom_icc_node xm_gic = {
+ .name = "xm_gic",
+ .id = LEMANS_MASTER_GIC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+ .name = "qns_a1noc_snoc",
+ .id = LEMANS_SLAVE_A1NOC_SNOC,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node qns_a2noc_snoc = {
+ .name = "qns_a2noc_snoc",
+ .id = LEMANS_SLAVE_A2NOC_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_A2NOC_SNOC },
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .id = LEMANS_SLAVE_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .id = LEMANS_SLAVE_QUP_CORE_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .id = LEMANS_SLAVE_QUP_CORE_2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup3_core_slave = {
+ .name = "qup3_core_slave",
+ .id = LEMANS_SLAVE_QUP_CORE_3,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy0 = {
+ .name = "qhs_ahb2phy0",
+ .id = LEMANS_SLAVE_AHB2PHY_0,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy1 = {
+ .name = "qhs_ahb2phy1",
+ .id = LEMANS_SLAVE_AHB2PHY_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy2 = {
+ .name = "qhs_ahb2phy2",
+ .id = LEMANS_SLAVE_AHB2PHY_2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy3 = {
+ .name = "qhs_ahb2phy3",
+ .id = LEMANS_SLAVE_AHB2PHY_3,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_anoc_throttle_cfg = {
+ .name = "qhs_anoc_throttle_cfg",
+ .id = LEMANS_SLAVE_ANOC_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_aoss = {
+ .name = "qhs_aoss",
+ .id = LEMANS_SLAVE_AOSS,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_apss = {
+ .name = "qhs_apss",
+ .id = LEMANS_SLAVE_APPSS,
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_boot_rom = {
+ .name = "qhs_boot_rom",
+ .id = LEMANS_SLAVE_BOOT_ROM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_cfg = {
+ .name = "qhs_camera_cfg",
+ .id = LEMANS_SLAVE_CAMERA_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
+ .name = "qhs_camera_nrt_throttle_cfg",
+ .id = LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
+ .name = "qhs_camera_rt_throttle_cfg",
+ .id = LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .id = LEMANS_SLAVE_CLK_CTL,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_compute0_cfg = {
+ .name = "qhs_compute0_cfg",
+ .id = LEMANS_SLAVE_CDSP_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CDSP_NOC_CFG },
+};
+
+static struct qcom_icc_node qhs_compute1_cfg = {
+ .name = "qhs_compute1_cfg",
+ .id = LEMANS_SLAVE_CDSP1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CDSPB_NOC_CFG },
+};
+
+static struct qcom_icc_node qhs_cpr_cx = {
+ .name = "qhs_cpr_cx",
+ .id = LEMANS_SLAVE_RBCPR_CX_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_cpr_mmcx = {
+ .name = "qhs_cpr_mmcx",
+ .id = LEMANS_SLAVE_RBCPR_MMCX_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_cpr_mx = {
+ .name = "qhs_cpr_mx",
+ .id = LEMANS_SLAVE_RBCPR_MX_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_cpr_nspcx = {
+ .name = "qhs_cpr_nspcx",
+ .id = LEMANS_SLAVE_CPR_NSPCX,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_crypto0_cfg = {
+ .name = "qhs_crypto0_cfg",
+ .id = LEMANS_SLAVE_CRYPTO_0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_cx_rdpm = {
+ .name = "qhs_cx_rdpm",
+ .id = LEMANS_SLAVE_CX_RDPM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display0_cfg = {
+ .name = "qhs_display0_cfg",
+ .id = LEMANS_SLAVE_DISPLAY_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
+ .name = "qhs_display0_rt_throttle_cfg",
+ .id = LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display1_cfg = {
+ .name = "qhs_display1_cfg",
+ .id = LEMANS_SLAVE_DISPLAY1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
+ .name = "qhs_display1_rt_throttle_cfg",
+ .id = LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_emac0_cfg = {
+ .name = "qhs_emac0_cfg",
+ .id = LEMANS_SLAVE_EMAC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_emac1_cfg = {
+ .name = "qhs_emac1_cfg",
+ .id = LEMANS_SLAVE_EMAC1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gp_dsp0_cfg = {
+ .name = "qhs_gp_dsp0_cfg",
+ .id = LEMANS_SLAVE_GP_DSP0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gp_dsp1_cfg = {
+ .name = "qhs_gp_dsp1_cfg",
+ .id = LEMANS_SLAVE_GP_DSP1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
+ .name = "qhs_gpdsp0_throttle_cfg",
+ .id = LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
+ .name = "qhs_gpdsp1_throttle_cfg",
+ .id = LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
+ .name = "qhs_gpu_tcu_throttle_cfg",
+ .id = LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpuss_cfg = {
+ .name = "qhs_gpuss_cfg",
+ .id = LEMANS_SLAVE_GFX3D_CFG,
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_hwkm = {
+ .name = "qhs_hwkm",
+ .id = LEMANS_SLAVE_HWKM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .id = LEMANS_SLAVE_IMEM_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .id = LEMANS_SLAVE_IPA_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .id = LEMANS_SLAVE_IPC_ROUTER_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_lpass_cfg = {
+ .name = "qhs_lpass_cfg",
+ .id = LEMANS_SLAVE_LPASS,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CNOC_LPASS_AG_NOC },
+};
+
+static struct qcom_icc_node qhs_lpass_throttle_cfg = {
+ .name = "qhs_lpass_throttle_cfg",
+ .id = LEMANS_SLAVE_LPASS_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mx_rdpm = {
+ .name = "qhs_mx_rdpm",
+ .id = LEMANS_SLAVE_MX_RDPM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mxc_rdpm = {
+ .name = "qhs_mxc_rdpm",
+ .id = LEMANS_SLAVE_MXC_RDPM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie0_cfg = {
+ .name = "qhs_pcie0_cfg",
+ .id = LEMANS_SLAVE_PCIE_0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie1_cfg = {
+ .name = "qhs_pcie1_cfg",
+ .id = LEMANS_SLAVE_PCIE_1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_rsc_cfg = {
+ .name = "qhs_pcie_rsc_cfg",
+ .id = LEMANS_SLAVE_PCIE_RSC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
+ .name = "qhs_pcie_tcu_throttle_cfg",
+ .id = LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_throttle_cfg = {
+ .name = "qhs_pcie_throttle_cfg",
+ .id = LEMANS_SLAVE_PCIE_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pdm = {
+ .name = "qhs_pdm",
+ .id = LEMANS_SLAVE_PDM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pimem_cfg = {
+ .name = "qhs_pimem_cfg",
+ .id = LEMANS_SLAVE_PIMEM_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pke_wrapper_cfg = {
+ .name = "qhs_pke_wrapper_cfg",
+ .id = LEMANS_SLAVE_PKA_WRAPPER_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qdss_cfg = {
+ .name = "qhs_qdss_cfg",
+ .id = LEMANS_SLAVE_QDSS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qm_cfg = {
+ .name = "qhs_qm_cfg",
+ .id = LEMANS_SLAVE_QM_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qm_mpu_cfg = {
+ .name = "qhs_qm_mpu_cfg",
+ .id = LEMANS_SLAVE_QM_MPU_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup0 = {
+ .name = "qhs_qup0",
+ .id = LEMANS_SLAVE_QUP_0,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup1 = {
+ .name = "qhs_qup1",
+ .id = LEMANS_SLAVE_QUP_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup2 = {
+ .name = "qhs_qup2",
+ .id = LEMANS_SLAVE_QUP_2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup3 = {
+ .name = "qhs_qup3",
+ .id = LEMANS_SLAVE_QUP_3,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sail_throttle_cfg = {
+ .name = "qhs_sail_throttle_cfg",
+ .id = LEMANS_SLAVE_SAIL_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc1 = {
+ .name = "qhs_sdc1",
+ .id = LEMANS_SLAVE_SDC1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_security = {
+ .name = "qhs_security",
+ .id = LEMANS_SLAVE_SECURITY,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_snoc_throttle_cfg = {
+ .name = "qhs_snoc_throttle_cfg",
+ .id = LEMANS_SLAVE_SNOC_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tcsr = {
+ .name = "qhs_tcsr",
+ .id = LEMANS_SLAVE_TCSR,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .id = LEMANS_SLAVE_TLMM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tsc_cfg = {
+ .name = "qhs_tsc_cfg",
+ .id = LEMANS_SLAVE_TSC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_card_cfg = {
+ .name = "qhs_ufs_card_cfg",
+ .id = LEMANS_SLAVE_UFS_CARD_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+ .name = "qhs_ufs_mem_cfg",
+ .id = LEMANS_SLAVE_UFS_MEM_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb2_0 = {
+ .name = "qhs_usb2_0",
+ .id = LEMANS_SLAVE_USB2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3_0 = {
+ .name = "qhs_usb3_0",
+ .id = LEMANS_SLAVE_USB3_0,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3_1 = {
+ .name = "qhs_usb3_1",
+ .id = LEMANS_SLAVE_USB3_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_venus_cfg = {
+ .name = "qhs_venus_cfg",
+ .id = LEMANS_SLAVE_VENUS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
+ .name = "qhs_venus_cvp_throttle_cfg",
+ .id = LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
+ .name = "qhs_venus_v_cpu_throttle_cfg",
+ .id = LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
+ .name = "qhs_venus_vcodec_throttle_cfg",
+ .id = LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_ddrss_cfg = {
+ .name = "qns_ddrss_cfg",
+ .id = LEMANS_SLAVE_DDRSS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CNOC_DC_NOC },
+};
+
+static struct qcom_icc_node qns_gpdsp_noc_cfg = {
+ .name = "qns_gpdsp_noc_cfg",
+ .id = LEMANS_SLAVE_GPDSP_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_mnoc_hf_cfg = {
+ .name = "qns_mnoc_hf_cfg",
+ .id = LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CNOC_MNOC_HF_CFG },
+};
+
+static struct qcom_icc_node qns_mnoc_sf_cfg = {
+ .name = "qns_mnoc_sf_cfg",
+ .id = LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_CNOC_MNOC_SF_CFG },
+};
+
+static struct qcom_icc_node qns_pcie_anoc_cfg = {
+ .name = "qns_pcie_anoc_cfg",
+ .id = LEMANS_SLAVE_PCIE_ANOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_snoc_cfg = {
+ .name = "qns_snoc_cfg",
+ .id = LEMANS_SLAVE_SNOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_SNOC_CFG },
+};
+
+static struct qcom_icc_node qxs_boot_imem = {
+ .name = "qxs_boot_imem",
+ .id = LEMANS_SLAVE_BOOT_IMEM,
+ .channels = 1,
+ .buswidth = 16,
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .id = LEMANS_SLAVE_IMEM,
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qxs_pimem = {
+ .name = "qxs_pimem",
+ .id = LEMANS_SLAVE_PIMEM,
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie_0 = {
+ .name = "xs_pcie_0",
+ .id = LEMANS_SLAVE_PCIE_0,
+ .channels = 1,
+ .buswidth = 16,
+};
+
+static struct qcom_icc_node xs_pcie_1 = {
+ .name = "xs_pcie_1",
+ .id = LEMANS_SLAVE_PCIE_1,
+ .channels = 1,
+ .buswidth = 32,
+};
+
+static struct qcom_icc_node xs_qdss_stm = {
+ .name = "xs_qdss_stm",
+ .id = LEMANS_SLAVE_QDSS_STM,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .id = LEMANS_SLAVE_TCU,
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_llcc = {
+ .name = "qhs_llcc",
+ .id = LEMANS_SLAVE_LLCC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_gemnoc = {
+ .name = "qns_gemnoc",
+ .id = LEMANS_SLAVE_GEM_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_GEM_NOC_CFG },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+ .name = "qns_gem_noc_cnoc",
+ .id = LEMANS_SLAVE_GEM_NOC_CNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_GEM_NOC_CNOC },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .id = LEMANS_SLAVE_LLCC,
+ .channels = 6,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_LLCC },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .id = LEMANS_SLAVE_GEM_NOC_PCIE_CNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_GEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node srvc_even_gemnoc = {
+ .name = "srvc_even_gemnoc",
+ .id = LEMANS_SLAVE_SERVICE_GEM_NOC_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_odd_gemnoc = {
+ .name = "srvc_odd_gemnoc",
+ .id = LEMANS_SLAVE_SERVICE_GEM_NOC_2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_sys_gemnoc = {
+ .name = "srvc_sys_gemnoc",
+ .id = LEMANS_SLAVE_SERVICE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_sys_gemnoc_2 = {
+ .name = "srvc_sys_gemnoc_2",
+ .id = LEMANS_SLAVE_SERVICE_GEM_NOC2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_gp_dsp_sail_noc = {
+ .name = "qns_gp_dsp_sail_noc",
+ .id = LEMANS_SLAVE_GP_DSP_SAIL_NOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_GPDSP_SAIL },
+};
+
+static struct qcom_icc_node qhs_lpass_core = {
+ .name = "qhs_lpass_core",
+ .id = LEMANS_SLAVE_LPASS_CORE_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_lpass_lpi = {
+ .name = "qhs_lpass_lpi",
+ .id = LEMANS_SLAVE_LPASS_LPI_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_lpass_mpu = {
+ .name = "qhs_lpass_mpu",
+ .id = LEMANS_SLAVE_LPASS_MPU_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_lpass_top = {
+ .name = "qhs_lpass_top",
+ .id = LEMANS_SLAVE_LPASS_TOP_CFG,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_sysnoc = {
+ .name = "qns_sysnoc",
+ .id = LEMANS_SLAVE_LPASS_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_LPASS_ANOC },
+};
+
+static struct qcom_icc_node srvc_niu_aml_noc = {
+ .name = "srvc_niu_aml_noc",
+ .id = LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_niu_lpass_agnoc = {
+ .name = "srvc_niu_lpass_agnoc",
+ .id = LEMANS_SLAVE_SERVICE_LPASS_AG_NOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .id = LEMANS_SLAVE_EBI1,
+ .channels = 8,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_mem_noc_hf = {
+ .name = "qns_mem_noc_hf",
+ .id = LEMANS_SLAVE_MNOC_HF_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_MNOC_HF_MEM_NOC },
+};
+
+static struct qcom_icc_node qns_mem_noc_sf = {
+ .name = "qns_mem_noc_sf",
+ .id = LEMANS_SLAVE_MNOC_SF_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_MNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node srvc_mnoc_hf = {
+ .name = "srvc_mnoc_hf",
+ .id = LEMANS_SLAVE_SERVICE_MNOC_HF,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_mnoc_sf = {
+ .name = "srvc_mnoc_sf",
+ .id = LEMANS_SLAVE_SERVICE_MNOC_SF,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_hcp = {
+ .name = "qns_hcp",
+ .id = LEMANS_SLAVE_HCP_A,
+ .channels = 2,
+ .buswidth = 32,
+};
+
+static struct qcom_icc_node qns_nsp_gemnoc = {
+ .name = "qns_nsp_gemnoc",
+ .id = LEMANS_SLAVE_CDSP_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_COMPUTE_NOC },
+};
+
+static struct qcom_icc_node service_nsp_noc = {
+ .name = "service_nsp_noc",
+ .id = LEMANS_SLAVE_SERVICE_NSP_NOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_nspb_gemnoc = {
+ .name = "qns_nspb_gemnoc",
+ .id = LEMANS_SLAVE_CDSPB_MEM_NOC,
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_COMPUTE_NOC_1 },
+};
+
+static struct qcom_icc_node qns_nspb_hcp = {
+ .name = "qns_nspb_hcp",
+ .id = LEMANS_SLAVE_HCP_B,
+ .channels = 2,
+ .buswidth = 32,
+};
+
+static struct qcom_icc_node service_nspb_noc = {
+ .name = "service_nspb_noc",
+ .id = LEMANS_SLAVE_SERVICE_NSPB_NOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_pcie_mem_noc = {
+ .name = "qns_pcie_mem_noc",
+ .id = LEMANS_SLAVE_ANOC_PCIE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node qns_gemnoc_gc = {
+ .name = "qns_gemnoc_gc",
+ .id = LEMANS_SLAVE_SNOC_GEM_NOC_GC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_SNOC_GC_MEM_NOC },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .id = LEMANS_SLAVE_SNOC_GEM_NOC_SF,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { LEMANS_MASTER_SNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node srvc_snoc = {
+ .name = "srvc_snoc",
+ .id = LEMANS_SLAVE_SERVICE_SNOC,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+ .name = "ACV",
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 2,
+ .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .keepalive = true,
+ .num_nodes = 2,
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
+};
+
+static struct qcom_icc_bcm bcm_cn1 = {
+ .name = "CN1",
+ .num_nodes = 76,
+ .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_ahb2phy2, &qhs_ahb2phy3,
+ &qhs_anoc_throttle_cfg, &qhs_aoss,
+ &qhs_apss, &qhs_boot_rom,
+ &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
+ &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
+ &qhs_compute0_cfg, &qhs_compute1_cfg,
+ &qhs_cpr_cx, &qhs_cpr_mmcx,
+ &qhs_cpr_mx, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
+ &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
+ &qhs_emac0_cfg, &qhs_emac1_cfg,
+ &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
+ &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
+ &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
+ &qhs_mx_rdpm, &qhs_mxc_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
+ &qhs_pcie_throttle_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
+ &qhs_qdss_cfg, &qhs_qm_cfg,
+ &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
+ &qhs_sdc1, &qhs_security,
+ &qhs_snoc_throttle_cfg, &qhs_tcsr,
+ &qhs_tlmm, &qhs_tsc_cfg,
+ &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
+ &qhs_usb2_0, &qhs_usb3_0,
+ &qhs_usb3_1, &qhs_venus_cfg,
+ &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
+ &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
+ &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
+ &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
+ &qns_snoc_cfg, &qxs_boot_imem,
+ &qxs_imem, &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_bcm bcm_cn2 = {
+ .name = "CN2",
+ .num_nodes = 4,
+ .nodes = { &qhs_qup0, &qhs_qup1,
+ &qhs_qup2, &qhs_qup3 },
+};
+
+static struct qcom_icc_bcm bcm_cn3 = {
+ .name = "CN3",
+ .num_nodes = 2,
+ .nodes = { &xs_pcie_0, &xs_pcie_1 },
+};
+
+static struct qcom_icc_bcm bcm_gna0 = {
+ .name = "GNA0",
+ .num_nodes = 1,
+ .nodes = { &qxm_dsp0 },
+};
+
+static struct qcom_icc_bcm bcm_gnb0 = {
+ .name = "GNB0",
+ .num_nodes = 1,
+ .nodes = { &qxm_dsp1 },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mm0 = {
+ .name = "MM0",
+ .keepalive = true,
+ .num_nodes = 5,
+ .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
+ &qnm_mdp0_1, &qnm_mdp1_0,
+ &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_bcm bcm_mm1 = {
+ .name = "MM1",
+ .num_nodes = 7,
+ .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
+ &qnm_video0, &qnm_video1,
+ &qnm_video_cvp, &qnm_video_v_cpu,
+ &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_bcm bcm_nsa0 = {
+ .name = "NSA0",
+ .num_nodes = 2,
+ .nodes = { &qns_hcp, &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_nsa1 = {
+ .name = "NSA1",
+ .num_nodes = 1,
+ .nodes = { &qxm_nsp },
+};
+
+static struct qcom_icc_bcm bcm_nsb0 = {
+ .name = "NSB0",
+ .num_nodes = 2,
+ .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
+};
+
+static struct qcom_icc_bcm bcm_nsb1 = {
+ .name = "NSB1",
+ .num_nodes = 1,
+ .nodes = { &qxm_nspb },
+};
+
+static struct qcom_icc_bcm bcm_pci0 = {
+ .name = "PCI0",
+ .num_nodes = 1,
+ .nodes = { &qns_pcie_mem_noc },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup1 = {
+ .name = "QUP1",
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup2 = {
+ .name = "QUP2",
+ .vote_scale = 1,
+ .num_nodes = 2,
+ .nodes = { &qup2_core_slave, &qup3_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh2 = {
+ .name = "SH2",
+ .num_nodes = 1,
+ .nodes = { &chm_apps },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn1 = {
+ .name = "SN1",
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_gc },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 1,
+ .nodes = { &qxs_pimem },
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+ .name = "SN3",
+ .num_nodes = 2,
+ .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn4 = {
+ .name = "SN4",
+ .num_nodes = 2,
+ .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn9 = {
+ .name = "SN9",
+ .num_nodes = 2,
+ .nodes = { &qns_sysnoc, &qnm_lpass_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn10 = {
+ .name = "SN10",
+ .num_nodes = 1,
+ .nodes = { &xs_qdss_stm },
+};
+
+static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node *aggre1_noc_nodes[] = {
+ [MASTER_QUP_3] = &qxm_qup3,
+ [MASTER_EMAC] = &xm_emac_0,
+ [MASTER_EMAC_1] = &xm_emac_1,
+ [MASTER_SDC] = &xm_sdc1,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB2] = &xm_usb2_2,
+ [MASTER_USB3_0] = &xm_usb3_0,
+ [MASTER_USB3_1] = &xm_usb3_1,
+ [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static struct qcom_icc_desc sa8775p_aggre1_noc = {
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+};
+
+static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
+ &bcm_ce0,
+ &bcm_sn4,
+};
+
+static struct qcom_icc_node *aggre2_noc_nodes[] = {
+ [MASTER_QDSS_BAM] = &qhm_qdss_bam,
+ [MASTER_QUP_0] = &qhm_qup0,
+ [MASTER_QUP_1] = &qhm_qup1,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
+ [MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
+ [MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
+ [MASTER_UFS_CARD] = &xm_ufs_card,
+ [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
+};
+
+static struct qcom_icc_desc sa8775p_aggre2_noc = {
+ .nodes = aggre2_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
+ .bcms = aggre2_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+};
+
+static struct qcom_icc_bcm *clk_virt_bcms[] = {
+ &bcm_qup0,
+ &bcm_qup1,
+ &bcm_qup2,
+};
+
+static struct qcom_icc_node *clk_virt_nodes[] = {
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [MASTER_QUP_CORE_3] = &qup3_core_master,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+ [SLAVE_QUP_CORE_3] = &qup3_core_slave,
+};
+
+static struct qcom_icc_desc sa8775p_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm *config_noc_bcms[] = {
+ &bcm_cn0,
+ &bcm_cn1,
+ &bcm_cn2,
+ &bcm_cn3,
+ &bcm_sn2,
+ &bcm_sn10,
+};
+
+static struct qcom_icc_node *config_noc_nodes[] = {
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
+ [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
+ [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
+ [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
+ [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_APPSS] = &qhs_apss,
+ [SLAVE_BOOT_ROM] = &qhs_boot_rom,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
+ [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
+ [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
+ [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
+ [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
+ [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
+ [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
+ [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
+ [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
+ [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
+ [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
+ [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
+ [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
+ [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
+ [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
+ [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
+ [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
+ [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
+ [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_HWKM] = &qhs_hwkm,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_LPASS] = &qhs_lpass_cfg,
+ [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
+ [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
+ [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+ [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
+ [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
+ [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
+ [SLAVE_PDM] = &qhs_pdm,
+ [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
+ [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+ [SLAVE_QM_CFG] = &qhs_qm_cfg,
+ [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
+ [SLAVE_QUP_0] = &qhs_qup0,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_QUP_3] = &qhs_qup3,
+ [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
+ [SLAVE_SDC1] = &qhs_sdc1,
+ [SLAVE_SECURITY] = &qhs_security,
+ [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
+ [SLAVE_TCSR] = &qhs_tcsr,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
+ [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB2] = &qhs_usb2_0,
+ [SLAVE_USB3_0] = &qhs_usb3_0,
+ [SLAVE_USB3_1] = &qhs_usb3_1,
+ [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
+ [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
+ [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
+ [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
+ [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
+ [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
+ [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
+ [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
+ [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
+ [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_PIMEM] = &qxs_pimem,
+ [SLAVE_PCIE_0] = &xs_pcie_0,
+ [SLAVE_PCIE_1] = &xs_pcie_1,
+ [SLAVE_QDSS_STM] = &xs_qdss_stm,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static struct qcom_icc_desc sa8775p_config_noc = {
+ .nodes = config_noc_nodes,
+ .num_nodes = ARRAY_SIZE(config_noc_nodes),
+ .bcms = config_noc_bcms,
+ .num_bcms = ARRAY_SIZE(config_noc_bcms),
+};
+
+static struct qcom_icc_bcm *dc_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *dc_noc_nodes[] = {
+ [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
+ [SLAVE_LLCC_CFG] = &qhs_llcc,
+ [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
+};
+
+static struct qcom_icc_desc sa8775p_dc_noc = {
+ .nodes = dc_noc_nodes,
+ .num_nodes = ARRAY_SIZE(dc_noc_nodes),
+ .bcms = dc_noc_bcms,
+ .num_bcms = ARRAY_SIZE(dc_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_bcms[] = {
+ &bcm_sh0,
+ &bcm_sh2,
+};
+
+static struct qcom_icc_node *gem_noc_nodes[] = {
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_PCIE_TCU] = &alm_pcie_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
+ [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
+ [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
+ [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
+ [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
+ [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
+ [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
+ [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
+};
+
+static struct qcom_icc_desc sa8775p_gem_noc = {
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
+ &bcm_gna0,
+ &bcm_gnb0,
+};
+
+static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
+ [MASTER_DSP0] = &qxm_dsp0,
+ [MASTER_DSP1] = &qxm_dsp1,
+ [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
+};
+
+static struct qcom_icc_desc sa8775p_gpdsp_anoc = {
+ .nodes = gpdsp_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
+ .bcms = gpdsp_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
+};
+
+static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
+ &bcm_sn9,
+};
+
+static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
+ [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
+ [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
+ [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
+ [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
+ [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
+ [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
+ [SLAVE_LPASS_SNOC] = &qns_sysnoc,
+ [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
+ [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
+};
+
+static struct qcom_icc_desc sa8775p_lpass_ag_noc = {
+ .nodes = lpass_ag_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+ .bcms = lpass_ag_noc_bcms,
+ .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_mc0,
+};
+
+static struct qcom_icc_node *mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [SLAVE_EBI1] = &ebi,
+};
+
+static struct qcom_icc_desc sa8775p_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node *mmss_noc_nodes[] = {
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_MDP0] = &qnm_mdp0_0,
+ [MASTER_MDP1] = &qnm_mdp0_1,
+ [MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
+ [MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
+ [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
+ [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
+ [MASTER_VIDEO_P0] = &qnm_video0,
+ [MASTER_VIDEO_P1] = &qnm_video1,
+ [MASTER_VIDEO_PROC] = &qnm_video_cvp,
+ [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+ [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
+ [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
+};
+
+static struct qcom_icc_desc sa8775p_mmss_noc = {
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm *nspa_noc_bcms[] = {
+ &bcm_nsa0,
+ &bcm_nsa1,
+};
+
+static struct qcom_icc_node *nspa_noc_nodes[] = {
+ [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
+ [MASTER_CDSP_PROC] = &qxm_nsp,
+ [SLAVE_HCP_A] = &qns_hcp,
+ [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+ [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
+};
+
+static struct qcom_icc_desc sa8775p_nspa_noc = {
+ .nodes = nspa_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
+ .bcms = nspa_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
+};
+
+static struct qcom_icc_bcm *nspb_noc_bcms[] = {
+ &bcm_nsb0,
+ &bcm_nsb1,
+};
+
+static struct qcom_icc_node *nspb_noc_nodes[] = {
+ [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
+ [MASTER_CDSP_PROC_B] = &qxm_nspb,
+ [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
+ [SLAVE_HCP_B] = &qns_nspb_hcp,
+ [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
+};
+
+static struct qcom_icc_desc sa8775p_nspb_noc = {
+ .nodes = nspb_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nspb_noc_nodes),
+ .bcms = nspb_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nspb_noc_bcms),
+
+};
+
+static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
+ &bcm_pci0,
+};
+
+static struct qcom_icc_node *pcie_anoc_nodes[] = {
+ [MASTER_PCIE_0] = &xm_pcie3_0,
+ [MASTER_PCIE_1] = &xm_pcie3_1,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
+};
+
+static struct qcom_icc_desc sa8775p_pcie_anoc = {
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+};
+
+static struct qcom_icc_bcm *system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn1,
+ &bcm_sn3,
+ &bcm_sn4,
+ &bcm_sn9,
+};
+
+static struct qcom_icc_node *system_noc_nodes[] = {
+ [MASTER_GIC_AHB] = &qhm_gic,
+ [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
+ [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
+ [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
+ [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
+ [MASTER_PIMEM] = &qxm_pimem,
+ [MASTER_GIC] = &xm_gic,
+ [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+ [SLAVE_SERVICE_SNOC] = &srvc_snoc,
+};
+
+static struct qcom_icc_desc sa8775p_system_noc = {
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
+ { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
+ { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
+ { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
+ { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
+ { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
+ { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
+ { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
+ { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
+ { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
+ { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
+ { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
+ { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
+ { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-sa8775p",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
+MODULE_LICENSE("GPL");
--
2.37.2

2023-01-09 18:20:48

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Subject: Re: [PATCH 07/18] interconnect: qcom: add a driver for sa8775p

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Shazad Hussain <[email protected]>
>
> Introduce QTI SA8775P-specific interconnect driver.
>
> Signed-off-by: Shazad Hussain <[email protected]>
> [Bartosz: made the driver ready for upstream]
> Co-developed-by: Bartosz Golaszewski <[email protected]>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> drivers/interconnect/qcom/Kconfig | 9 +
> drivers/interconnect/qcom/Makefile | 2 +
> drivers/interconnect/qcom/sa8775p.c | 2542 +++++++++++++++++++++++++++
> 3 files changed, 2553 insertions(+)
> create mode 100644 drivers/interconnect/qcom/sa8775p.c
>
> diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
> index 1a1c941635a2..023e42ebe365 100644
> --- a/drivers/interconnect/qcom/Kconfig
> +++ b/drivers/interconnect/qcom/Kconfig
> @@ -83,6 +83,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE
> config INTERCONNECT_QCOM_RPMH
> tristate
>
> +config INTERCONNECT_QCOM_SA8775P
> + tristate "Qualcomm SA8775P interconnect driver"
> + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
> + select INTERCONNECT_QCOM_RPMH
> + select INTERCONNECT_QCOM_BCM_VOTER
> + help
> + This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
> + platforms.
> +
> config INTERCONNECT_QCOM_SC7180
> tristate "Qualcomm SC7180 interconnect driver"
> depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
> diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
> index 8e357528185d..32d90ff7960e 100644
> --- a/drivers/interconnect/qcom/Makefile
> +++ b/drivers/interconnect/qcom/Makefile
> @@ -12,6 +12,7 @@ icc-osm-l3-objs := osm-l3.o
> qnoc-qcm2290-objs := qcm2290.o
> qnoc-qcs404-objs := qcs404.o
> icc-rpmh-obj := icc-rpmh.o
> +qnoc-sa8775p-objs := sa8775p.o
> qnoc-sc7180-objs := sc7180.o
> qnoc-sc7280-objs := sc7280.o
> qnoc-sc8180x-objs := sc8180x.o
> @@ -36,6 +37,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
> obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
> obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
> obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
> +obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
> obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
> obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
> obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
> diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
> new file mode 100644
> index 000000000000..bb23234eaad5
> --- /dev/null
> +++ b/drivers/interconnect/qcom/sa8775p.c
> @@ -0,0 +1,2542 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <linux/device.h>
> +#include <linux/interconnect.h>
> +#include <linux/interconnect-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +
> +#include "bcm-voter.h"
> +#include "icc-rpmh.h"
> +
> +#define LEMANS_MASTER_GPU_TCU 0
s/LEMANS/SA8775P; Qualcomm codenames are not really deterministic
and hence we use the numeric names upstream.

Konrad
> +#define LEMANS_MASTER_PCIE_TCU 1
> +#define LEMANS_MASTER_SYS_TCU 2
> +#define LEMANS_MASTER_APPSS_PROC 3
> +#define LEMANS_MASTER_LLCC 4
> +#define LEMANS_MASTER_CNOC_LPASS_AG_NOC 5
> +#define LEMANS_MASTER_GIC_AHB 6
> +#define LEMANS_MASTER_CDSP_NOC_CFG 7
> +#define LEMANS_MASTER_CDSPB_NOC_CFG 8
> +#define LEMANS_MASTER_QDSS_BAM 9
> +#define LEMANS_MASTER_QUP_0 10
> +#define LEMANS_MASTER_QUP_1 11
> +#define LEMANS_MASTER_QUP_2 12
> +#define LEMANS_MASTER_A1NOC_SNOC 13
> +#define LEMANS_MASTER_A2NOC_SNOC 14
> +#define LEMANS_MASTER_CAMNOC_HF 15
> +#define LEMANS_MASTER_CAMNOC_ICP 16
> +#define LEMANS_MASTER_CAMNOC_SF 17
> +#define LEMANS_MASTER_COMPUTE_NOC 18
> +#define LEMANS_MASTER_COMPUTE_NOC_1 19
> +#define LEMANS_MASTER_CNOC_A2NOC 20
> +#define LEMANS_MASTER_CNOC_DC_NOC 21
> +#define LEMANS_MASTER_GEM_NOC_CFG 22
> +#define LEMANS_MASTER_GEM_NOC_CNOC 23
> +#define LEMANS_MASTER_GEM_NOC_PCIE_SNOC 24
> +#define LEMANS_MASTER_GPDSP_SAIL 25
> +#define LEMANS_MASTER_GFX3D 26
> +#define LEMANS_MASTER_LPASS_ANOC 27
> +#define LEMANS_MASTER_MDP0 28
> +#define LEMANS_MASTER_MDP1 29
> +#define LEMANS_MASTER_MDP_CORE1_0 30
> +#define LEMANS_MASTER_MDP_CORE1_1 31
> +#define LEMANS_MASTER_MNOC_HF_MEM_NOC 32
> +#define LEMANS_MASTER_CNOC_MNOC_HF_CFG 33
> +#define LEMANS_MASTER_MNOC_SF_MEM_NOC 34
> +#define LEMANS_MASTER_CNOC_MNOC_SF_CFG 35
> +#define LEMANS_MASTER_ANOC_PCIE_GEM_NOC 36
> +#define LEMANS_MASTER_SNOC_CFG 37
> +#define LEMANS_MASTER_SNOC_GC_MEM_NOC 38
> +#define LEMANS_MASTER_SNOC_SF_MEM_NOC 39
> +#define LEMANS_MASTER_VIDEO_P0 40
> +#define LEMANS_MASTER_VIDEO_P1 41
> +#define LEMANS_MASTER_VIDEO_PROC 42
> +#define LEMANS_MASTER_VIDEO_V_PROC 43
> +#define LEMANS_MASTER_QUP_CORE_0 44
> +#define LEMANS_MASTER_QUP_CORE_1 45
> +#define LEMANS_MASTER_QUP_CORE_2 46
> +#define LEMANS_MASTER_QUP_CORE_3 47
> +#define LEMANS_MASTER_CRYPTO_CORE0 48
> +#define LEMANS_MASTER_CRYPTO_CORE1 49
> +#define LEMANS_MASTER_DSP0 50
> +#define LEMANS_MASTER_DSP1 51
> +#define LEMANS_MASTER_IPA 52
> +#define LEMANS_MASTER_LPASS_PROC 53
> +#define LEMANS_MASTER_CDSP_PROC 54
> +#define LEMANS_MASTER_CDSP_PROC_B 55
> +#define LEMANS_MASTER_PIMEM 56
> +#define LEMANS_MASTER_QUP_3 57
> +#define LEMANS_MASTER_EMAC 58
> +#define LEMANS_MASTER_EMAC_1 59
> +#define LEMANS_MASTER_GIC 60
> +#define LEMANS_MASTER_PCIE_0 61
> +#define LEMANS_MASTER_PCIE_1 62
> +#define LEMANS_MASTER_QDSS_ETR_0 63
> +#define LEMANS_MASTER_QDSS_ETR_1 64
> +#define LEMANS_MASTER_SDC 65
> +#define LEMANS_MASTER_UFS_CARD 66
> +#define LEMANS_MASTER_UFS_MEM 67
> +#define LEMANS_MASTER_USB2 68
> +#define LEMANS_MASTER_USB3_0 69
> +#define LEMANS_MASTER_USB3_1 70
> +#define LEMANS_SLAVE_EBI1 512
> +#define LEMANS_SLAVE_AHB2PHY_0 513
> +#define LEMANS_SLAVE_AHB2PHY_1 514
> +#define LEMANS_SLAVE_AHB2PHY_2 515
> +#define LEMANS_SLAVE_AHB2PHY_3 516
> +#define LEMANS_SLAVE_ANOC_THROTTLE_CFG 517
> +#define LEMANS_SLAVE_AOSS 518
> +#define LEMANS_SLAVE_APPSS 519
> +#define LEMANS_SLAVE_BOOT_ROM 520
> +#define LEMANS_SLAVE_CAMERA_CFG 521
> +#define LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG 522
> +#define LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG 523
> +#define LEMANS_SLAVE_CLK_CTL 524
> +#define LEMANS_SLAVE_CDSP_CFG 525
> +#define LEMANS_SLAVE_CDSP1_CFG 526
> +#define LEMANS_SLAVE_RBCPR_CX_CFG 527
> +#define LEMANS_SLAVE_RBCPR_MMCX_CFG 528
> +#define LEMANS_SLAVE_RBCPR_MX_CFG 529
> +#define LEMANS_SLAVE_CPR_NSPCX 530
> +#define LEMANS_SLAVE_CRYPTO_0_CFG 531
> +#define LEMANS_SLAVE_CX_RDPM 532
> +#define LEMANS_SLAVE_DISPLAY_CFG 533
> +#define LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG 534
> +#define LEMANS_SLAVE_DISPLAY1_CFG 535
> +#define LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536
> +#define LEMANS_SLAVE_EMAC_CFG 537
> +#define LEMANS_SLAVE_EMAC1_CFG 538
> +#define LEMANS_SLAVE_GP_DSP0_CFG 539
> +#define LEMANS_SLAVE_GP_DSP1_CFG 540
> +#define LEMANS_SLAVE_GPDSP0_THROTTLE_CFG 541
> +#define LEMANS_SLAVE_GPDSP1_THROTTLE_CFG 542
> +#define LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG 543
> +#define LEMANS_SLAVE_GFX3D_CFG 544
> +#define LEMANS_SLAVE_HWKM 545
> +#define LEMANS_SLAVE_IMEM_CFG 546
> +#define LEMANS_SLAVE_IPA_CFG 547
> +#define LEMANS_SLAVE_IPC_ROUTER_CFG 548
> +#define LEMANS_SLAVE_LLCC_CFG 549
> +#define LEMANS_SLAVE_LPASS 550
> +#define LEMANS_SLAVE_LPASS_CORE_CFG 551
> +#define LEMANS_SLAVE_LPASS_LPI_CFG 552
> +#define LEMANS_SLAVE_LPASS_MPU_CFG 553
> +#define LEMANS_SLAVE_LPASS_THROTTLE_CFG 554
> +#define LEMANS_SLAVE_LPASS_TOP_CFG 555
> +#define LEMANS_SLAVE_MX_RDPM 556
> +#define LEMANS_SLAVE_MXC_RDPM 557
> +#define LEMANS_SLAVE_PCIE_0_CFG 558
> +#define LEMANS_SLAVE_PCIE_1_CFG 559
> +#define LEMANS_SLAVE_PCIE_RSC_CFG 560
> +#define LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG 561
> +#define LEMANS_SLAVE_PCIE_THROTTLE_CFG 562
> +#define LEMANS_SLAVE_PDM 563
> +#define LEMANS_SLAVE_PIMEM_CFG 564
> +#define LEMANS_SLAVE_PKA_WRAPPER_CFG 565
> +#define LEMANS_SLAVE_QDSS_CFG 566
> +#define LEMANS_SLAVE_QM_CFG 567
> +#define LEMANS_SLAVE_QM_MPU_CFG 568
> +#define LEMANS_SLAVE_QUP_0 569
> +#define LEMANS_SLAVE_QUP_1 570
> +#define LEMANS_SLAVE_QUP_2 571
> +#define LEMANS_SLAVE_QUP_3 572
> +#define LEMANS_SLAVE_SAIL_THROTTLE_CFG 573
> +#define LEMANS_SLAVE_SDC1 574
> +#define LEMANS_SLAVE_SECURITY 575
> +#define LEMANS_SLAVE_SNOC_THROTTLE_CFG 576
> +#define LEMANS_SLAVE_TCSR 577
> +#define LEMANS_SLAVE_TLMM 578
> +#define LEMANS_SLAVE_TSC_CFG 579
> +#define LEMANS_SLAVE_UFS_CARD_CFG 580
> +#define LEMANS_SLAVE_UFS_MEM_CFG 581
> +#define LEMANS_SLAVE_USB2 582
> +#define LEMANS_SLAVE_USB3_0 583
> +#define LEMANS_SLAVE_USB3_1 584
> +#define LEMANS_SLAVE_VENUS_CFG 585
> +#define LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG 586
> +#define LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587
> +#define LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588
> +#define LEMANS_SLAVE_A1NOC_SNOC 589
> +#define LEMANS_SLAVE_A2NOC_SNOC 590
> +#define LEMANS_SLAVE_DDRSS_CFG 591
> +#define LEMANS_SLAVE_GEM_NOC_CNOC 592
> +#define LEMANS_SLAVE_GEM_NOC_CFG 593
> +#define LEMANS_SLAVE_SNOC_GEM_NOC_GC 594
> +#define LEMANS_SLAVE_SNOC_GEM_NOC_SF 595
> +#define LEMANS_SLAVE_GP_DSP_SAIL_NOC 596
> +#define LEMANS_SLAVE_GPDSP_NOC_CFG 597
> +#define LEMANS_SLAVE_HCP_A 598
> +#define LEMANS_SLAVE_LLCC 599
> +#define LEMANS_SLAVE_MNOC_HF_MEM_NOC 600
> +#define LEMANS_SLAVE_MNOC_SF_MEM_NOC 601
> +#define LEMANS_SLAVE_CNOC_MNOC_HF_CFG 602
> +#define LEMANS_SLAVE_CNOC_MNOC_SF_CFG 603
> +#define LEMANS_SLAVE_CDSP_MEM_NOC 604
> +#define LEMANS_SLAVE_CDSPB_MEM_NOC 605
> +#define LEMANS_SLAVE_HCP_B 606
> +#define LEMANS_SLAVE_GEM_NOC_PCIE_CNOC 607
> +#define LEMANS_SLAVE_PCIE_ANOC_CFG 608
> +#define LEMANS_SLAVE_ANOC_PCIE_GEM_NOC 609
> +#define LEMANS_SLAVE_SNOC_CFG 610
> +#define LEMANS_SLAVE_LPASS_SNOC 611
> +#define LEMANS_SLAVE_QUP_CORE_0 612
> +#define LEMANS_SLAVE_QUP_CORE_1 613
> +#define LEMANS_SLAVE_QUP_CORE_2 614
> +#define LEMANS_SLAVE_QUP_CORE_3 615
> +#define LEMANS_SLAVE_BOOT_IMEM 616
> +#define LEMANS_SLAVE_IMEM 617
> +#define LEMANS_SLAVE_PIMEM 618
> +#define LEMANS_SLAVE_SERVICE_NSP_NOC 619
> +#define LEMANS_SLAVE_SERVICE_NSPB_NOC 620
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC_1 621
> +#define LEMANS_SLAVE_SERVICE_MNOC_HF 622
> +#define LEMANS_SLAVE_SERVICE_MNOC_SF 623
> +#define LEMANS_SLAVE_SERVICES_LPASS_AML_NOC 624
> +#define LEMANS_SLAVE_SERVICE_LPASS_AG_NOC 625
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC_2 626
> +#define LEMANS_SLAVE_SERVICE_SNOC 627
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC 628
> +#define LEMANS_SLAVE_SERVICE_GEM_NOC2 629
> +#define LEMANS_SLAVE_PCIE_0 630
> +#define LEMANS_SLAVE_PCIE_1 631
> +#define LEMANS_SLAVE_QDSS_STM 632
> +#define LEMANS_SLAVE_TCU 633
> +
> +static struct qcom_icc_node qxm_qup3 = {
> + .name = "qxm_qup3",
> + .id = LEMANS_MASTER_QUP_3,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_emac_0 = {
> + .name = "xm_emac_0",
> + .id = LEMANS_MASTER_EMAC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_emac_1 = {
> + .name = "xm_emac_1",
> + .id = LEMANS_MASTER_EMAC_1,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_sdc1 = {
> + .name = "xm_sdc1",
> + .id = LEMANS_MASTER_SDC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_ufs_mem = {
> + .name = "xm_ufs_mem",
> + .id = LEMANS_MASTER_UFS_MEM,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb2_2 = {
> + .name = "xm_usb2_2",
> + .id = LEMANS_MASTER_USB2,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb3_0 = {
> + .name = "xm_usb3_0",
> + .id = LEMANS_MASTER_USB3_0,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_usb3_1 = {
> + .name = "xm_usb3_1",
> + .id = LEMANS_MASTER_USB3_1,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qdss_bam = {
> + .name = "qhm_qdss_bam",
> + .id = LEMANS_MASTER_QDSS_BAM,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup0 = {
> + .name = "qhm_qup0",
> + .id = LEMANS_MASTER_QUP_0,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup1 = {
> + .name = "qhm_qup1",
> + .id = LEMANS_MASTER_QUP_1,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qhm_qup2 = {
> + .name = "qhm_qup2",
> + .id = LEMANS_MASTER_QUP_2,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qnm_cnoc_datapath = {
> + .name = "qnm_cnoc_datapath",
> + .id = LEMANS_MASTER_CNOC_A2NOC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_crypto_0 = {
> + .name = "qxm_crypto_0",
> + .id = LEMANS_MASTER_CRYPTO_CORE0,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_crypto_1 = {
> + .name = "qxm_crypto_1",
> + .id = LEMANS_MASTER_CRYPTO_CORE1,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_ipa = {
> + .name = "qxm_ipa",
> + .id = LEMANS_MASTER_IPA,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_qdss_etr_0 = {
> + .name = "xm_qdss_etr_0",
> + .id = LEMANS_MASTER_QDSS_ETR_0,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_qdss_etr_1 = {
> + .name = "xm_qdss_etr_1",
> + .id = LEMANS_MASTER_QDSS_ETR_1,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node xm_ufs_card = {
> + .name = "xm_ufs_card",
> + .id = LEMANS_MASTER_UFS_CARD,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qup0_core_master = {
> + .name = "qup0_core_master",
> + .id = LEMANS_MASTER_QUP_CORE_0,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_QUP_CORE_0 },
> +};
> +
> +static struct qcom_icc_node qup1_core_master = {
> + .name = "qup1_core_master",
> + .id = LEMANS_MASTER_QUP_CORE_1,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_QUP_CORE_1 },
> +};
> +
> +static struct qcom_icc_node qup2_core_master = {
> + .name = "qup2_core_master",
> + .id = LEMANS_MASTER_QUP_CORE_2,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_QUP_CORE_2 },
> +};
> +
> +static struct qcom_icc_node qup3_core_master = {
> + .name = "qup3_core_master",
> + .id = LEMANS_MASTER_QUP_CORE_3,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_QUP_CORE_3 },
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_cnoc = {
> + .name = "qnm_gemnoc_cnoc",
> + .id = LEMANS_MASTER_GEM_NOC_CNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 82,
> + .links = { LEMANS_SLAVE_AHB2PHY_0,
> + LEMANS_SLAVE_AHB2PHY_1,
> + LEMANS_SLAVE_AHB2PHY_2,
> + LEMANS_SLAVE_AHB2PHY_3,
> + LEMANS_SLAVE_ANOC_THROTTLE_CFG,
> + LEMANS_SLAVE_AOSS,
> + LEMANS_SLAVE_APPSS,
> + LEMANS_SLAVE_BOOT_ROM,
> + LEMANS_SLAVE_CAMERA_CFG,
> + LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
> + LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
> + LEMANS_SLAVE_CLK_CTL,
> + LEMANS_SLAVE_CDSP_CFG,
> + LEMANS_SLAVE_CDSP1_CFG,
> + LEMANS_SLAVE_RBCPR_CX_CFG,
> + LEMANS_SLAVE_RBCPR_MMCX_CFG,
> + LEMANS_SLAVE_RBCPR_MX_CFG,
> + LEMANS_SLAVE_CPR_NSPCX,
> + LEMANS_SLAVE_CRYPTO_0_CFG,
> + LEMANS_SLAVE_CX_RDPM,
> + LEMANS_SLAVE_DISPLAY_CFG,
> + LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
> + LEMANS_SLAVE_DISPLAY1_CFG,
> + LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
> + LEMANS_SLAVE_EMAC_CFG,
> + LEMANS_SLAVE_EMAC1_CFG,
> + LEMANS_SLAVE_GP_DSP0_CFG,
> + LEMANS_SLAVE_GP_DSP1_CFG,
> + LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
> + LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
> + LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
> + LEMANS_SLAVE_GFX3D_CFG,
> + LEMANS_SLAVE_HWKM,
> + LEMANS_SLAVE_IMEM_CFG,
> + LEMANS_SLAVE_IPA_CFG,
> + LEMANS_SLAVE_IPC_ROUTER_CFG,
> + LEMANS_SLAVE_LPASS,
> + LEMANS_SLAVE_LPASS_THROTTLE_CFG,
> + LEMANS_SLAVE_MX_RDPM,
> + LEMANS_SLAVE_MXC_RDPM,
> + LEMANS_SLAVE_PCIE_0_CFG,
> + LEMANS_SLAVE_PCIE_1_CFG,
> + LEMANS_SLAVE_PCIE_RSC_CFG,
> + LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
> + LEMANS_SLAVE_PCIE_THROTTLE_CFG,
> + LEMANS_SLAVE_PDM,
> + LEMANS_SLAVE_PIMEM_CFG,
> + LEMANS_SLAVE_PKA_WRAPPER_CFG,
> + LEMANS_SLAVE_QDSS_CFG,
> + LEMANS_SLAVE_QM_CFG,
> + LEMANS_SLAVE_QM_MPU_CFG,
> + LEMANS_SLAVE_QUP_0,
> + LEMANS_SLAVE_QUP_1,
> + LEMANS_SLAVE_QUP_2,
> + LEMANS_SLAVE_QUP_3,
> + LEMANS_SLAVE_SAIL_THROTTLE_CFG,
> + LEMANS_SLAVE_SDC1,
> + LEMANS_SLAVE_SECURITY,
> + LEMANS_SLAVE_SNOC_THROTTLE_CFG,
> + LEMANS_SLAVE_TCSR,
> + LEMANS_SLAVE_TLMM,
> + LEMANS_SLAVE_TSC_CFG,
> + LEMANS_SLAVE_UFS_CARD_CFG,
> + LEMANS_SLAVE_UFS_MEM_CFG,
> + LEMANS_SLAVE_USB2,
> + LEMANS_SLAVE_USB3_0,
> + LEMANS_SLAVE_USB3_1,
> + LEMANS_SLAVE_VENUS_CFG,
> + LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
> + LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
> + LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
> + LEMANS_SLAVE_DDRSS_CFG,
> + LEMANS_SLAVE_GPDSP_NOC_CFG,
> + LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
> + LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
> + LEMANS_SLAVE_PCIE_ANOC_CFG,
> + LEMANS_SLAVE_SNOC_CFG,
> + LEMANS_SLAVE_BOOT_IMEM,
> + LEMANS_SLAVE_IMEM,
> + LEMANS_SLAVE_PIMEM,
> + LEMANS_SLAVE_QDSS_STM,
> + LEMANS_SLAVE_TCU
> + },
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_pcie = {
> + .name = "qnm_gemnoc_pcie",
> + .id = LEMANS_MASTER_GEM_NOC_PCIE_SNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_PCIE_0,
> + LEMANS_SLAVE_PCIE_1
> + },
> +};
> +
> +static struct qcom_icc_node qnm_cnoc_dc_noc = {
> + .name = "qnm_cnoc_dc_noc",
> + .id = LEMANS_MASTER_CNOC_DC_NOC,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_LLCC_CFG,
> + LEMANS_SLAVE_GEM_NOC_CFG
> + },
> +};
> +
> +static struct qcom_icc_node alm_gpu_tcu = {
> + .name = "alm_gpu_tcu",
> + .id = LEMANS_MASTER_GPU_TCU,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node alm_pcie_tcu = {
> + .name = "alm_pcie_tcu",
> + .id = LEMANS_MASTER_PCIE_TCU,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node alm_sys_tcu = {
> + .name = "alm_sys_tcu",
> + .id = LEMANS_MASTER_SYS_TCU,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node chm_apps = {
> + .name = "chm_apps",
> + .id = LEMANS_MASTER_APPSS_PROC,
> + .channels = 4,
> + .buswidth = 32,
> + .num_links = 3,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC,
> + LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_cmpnoc0 = {
> + .name = "qnm_cmpnoc0",
> + .id = LEMANS_MASTER_COMPUTE_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_cmpnoc1 = {
> + .name = "qnm_cmpnoc1",
> + .id = LEMANS_MASTER_COMPUTE_NOC_1,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_gemnoc_cfg = {
> + .name = "qnm_gemnoc_cfg",
> + .id = LEMANS_MASTER_GEM_NOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 4,
> + .links = { LEMANS_SLAVE_SERVICE_GEM_NOC_1,
> + LEMANS_SLAVE_SERVICE_GEM_NOC_2,
> + LEMANS_SLAVE_SERVICE_GEM_NOC,
> + LEMANS_SLAVE_SERVICE_GEM_NOC2
> + },
> +};
> +
> +static struct qcom_icc_node qnm_gpdsp_sail = {
> + .name = "qnm_gpdsp_sail",
> + .id = LEMANS_MASTER_GPDSP_SAIL,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_gpu = {
> + .name = "qnm_gpu",
> + .id = LEMANS_MASTER_GFX3D,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_hf = {
> + .name = "qnm_mnoc_hf",
> + .id = LEMANS_MASTER_MNOC_HF_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_LLCC,
> + LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_sf = {
> + .name = "qnm_mnoc_sf",
> + .id = LEMANS_MASTER_MNOC_SF_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 3,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC,
> + LEMANS_SLAVE_GEM_NOC_PCIE_CNOC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_pcie = {
> + .name = "qnm_pcie",
> + .id = LEMANS_MASTER_ANOC_PCIE_GEM_NOC,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC
> + },
> +};
> +
> +static struct qcom_icc_node qnm_snoc_gc = {
> + .name = "qnm_snoc_gc",
> + .id = LEMANS_MASTER_SNOC_GC_MEM_NOC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_LLCC },
> +};
> +
> +static struct qcom_icc_node qnm_snoc_sf = {
> + .name = "qnm_snoc_sf",
> + .id = LEMANS_MASTER_SNOC_SF_MEM_NOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 3,
> + .links = { LEMANS_SLAVE_GEM_NOC_CNOC,
> + LEMANS_SLAVE_LLCC,
> + LEMANS_SLAVE_GEM_NOC_PCIE_CNOC },
> +};
> +
> +static struct qcom_icc_node qxm_dsp0 = {
> + .name = "qxm_dsp0",
> + .id = LEMANS_MASTER_DSP0,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_dsp1 = {
> + .name = "qxm_dsp1",
> + .id = LEMANS_MASTER_DSP1,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_GP_DSP_SAIL_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_config_noc = {
> + .name = "qhm_config_noc",
> + .id = LEMANS_MASTER_CNOC_LPASS_AG_NOC,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 6,
> + .links = { LEMANS_SLAVE_LPASS_CORE_CFG,
> + LEMANS_SLAVE_LPASS_LPI_CFG,
> + LEMANS_SLAVE_LPASS_MPU_CFG,
> + LEMANS_SLAVE_LPASS_TOP_CFG,
> + LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> + LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
> + },
> +};
> +
> +static struct qcom_icc_node qxm_lpass_dsp = {
> + .name = "qxm_lpass_dsp",
> + .id = LEMANS_MASTER_LPASS_PROC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 4,
> + .links = { LEMANS_SLAVE_LPASS_TOP_CFG,
> + LEMANS_SLAVE_LPASS_SNOC,
> + LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> + LEMANS_SLAVE_SERVICE_LPASS_AG_NOC
> + },
> +};
> +
> +static struct qcom_icc_node llcc_mc = {
> + .name = "llcc_mc",
> + .id = LEMANS_MASTER_LLCC,
> + .channels = 8,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_EBI1 },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_hf = {
> + .name = "qnm_camnoc_hf",
> + .id = LEMANS_MASTER_CAMNOC_HF,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_icp = {
> + .name = "qnm_camnoc_icp",
> + .id = LEMANS_MASTER_CAMNOC_ICP,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_camnoc_sf = {
> + .name = "qnm_camnoc_sf",
> + .id = LEMANS_MASTER_CAMNOC_SF,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp0_0 = {
> + .name = "qnm_mdp0_0",
> + .id = LEMANS_MASTER_MDP0,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp0_1 = {
> + .name = "qnm_mdp0_1",
> + .id = LEMANS_MASTER_MDP1,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp1_0 = {
> + .name = "qnm_mdp1_0",
> + .id = LEMANS_MASTER_MDP_CORE1_0,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mdp1_1 = {
> + .name = "qnm_mdp1_1",
> + .id = LEMANS_MASTER_MDP_CORE1_1,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_hf_cfg = {
> + .name = "qnm_mnoc_hf_cfg",
> + .id = LEMANS_MASTER_CNOC_MNOC_HF_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SERVICE_MNOC_HF },
> +};
> +
> +static struct qcom_icc_node qnm_mnoc_sf_cfg = {
> + .name = "qnm_mnoc_sf_cfg",
> + .id = LEMANS_MASTER_CNOC_MNOC_SF_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SERVICE_MNOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_video0 = {
> + .name = "qnm_video0",
> + .id = LEMANS_MASTER_VIDEO_P0,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video1 = {
> + .name = "qnm_video1",
> + .id = LEMANS_MASTER_VIDEO_P1,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video_cvp = {
> + .name = "qnm_video_cvp",
> + .id = LEMANS_MASTER_VIDEO_PROC,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qnm_video_v_cpu = {
> + .name = "qnm_video_v_cpu",
> + .id = LEMANS_MASTER_VIDEO_V_PROC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_nsp_noc_config = {
> + .name = "qhm_nsp_noc_config",
> + .id = LEMANS_MASTER_CDSP_NOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SERVICE_NSP_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_nsp = {
> + .name = "qxm_nsp",
> + .id = LEMANS_MASTER_CDSP_PROC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_nspb_noc_config = {
> + .name = "qhm_nspb_noc_config",
> + .id = LEMANS_MASTER_CDSPB_NOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SERVICE_NSPB_NOC },
> +};
> +
> +static struct qcom_icc_node qxm_nspb = {
> + .name = "qxm_nspb",
> + .id = LEMANS_MASTER_CDSP_PROC_B,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 2,
> + .links = { LEMANS_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node xm_pcie3_0 = {
> + .name = "xm_pcie3_0",
> + .id = LEMANS_MASTER_PCIE_0,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node xm_pcie3_1 = {
> + .name = "xm_pcie3_1",
> + .id = LEMANS_MASTER_PCIE_1,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node qhm_gic = {
> + .name = "qhm_gic",
> + .id = LEMANS_MASTER_GIC_AHB,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_aggre1_noc = {
> + .name = "qnm_aggre1_noc",
> + .id = LEMANS_MASTER_A1NOC_SNOC,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_aggre2_noc = {
> + .name = "qnm_aggre2_noc",
> + .id = LEMANS_MASTER_A2NOC_SNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_lpass_noc = {
> + .name = "qnm_lpass_noc",
> + .id = LEMANS_MASTER_LPASS_ANOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_SF },
> +};
> +
> +static struct qcom_icc_node qnm_snoc_cfg = {
> + .name = "qnm_snoc_cfg",
> + .id = LEMANS_MASTER_SNOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SERVICE_SNOC },
> +};
> +
> +static struct qcom_icc_node qxm_pimem = {
> + .name = "qxm_pimem",
> + .id = LEMANS_MASTER_PIMEM,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
> +};
> +
> +static struct qcom_icc_node xm_gic = {
> + .name = "xm_gic",
> + .id = LEMANS_MASTER_GIC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_SLAVE_SNOC_GEM_NOC_GC },
> +};
> +
> +static struct qcom_icc_node qns_a1noc_snoc = {
> + .name = "qns_a1noc_snoc",
> + .id = LEMANS_SLAVE_A1NOC_SNOC,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_A1NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qns_a2noc_snoc = {
> + .name = "qns_a2noc_snoc",
> + .id = LEMANS_SLAVE_A2NOC_SNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_A2NOC_SNOC },
> +};
> +
> +static struct qcom_icc_node qup0_core_slave = {
> + .name = "qup0_core_slave",
> + .id = LEMANS_SLAVE_QUP_CORE_0,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup1_core_slave = {
> + .name = "qup1_core_slave",
> + .id = LEMANS_SLAVE_QUP_CORE_1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup2_core_slave = {
> + .name = "qup2_core_slave",
> + .id = LEMANS_SLAVE_QUP_CORE_2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qup3_core_slave = {
> + .name = "qup3_core_slave",
> + .id = LEMANS_SLAVE_QUP_CORE_3,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy0 = {
> + .name = "qhs_ahb2phy0",
> + .id = LEMANS_SLAVE_AHB2PHY_0,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy1 = {
> + .name = "qhs_ahb2phy1",
> + .id = LEMANS_SLAVE_AHB2PHY_1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy2 = {
> + .name = "qhs_ahb2phy2",
> + .id = LEMANS_SLAVE_AHB2PHY_2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ahb2phy3 = {
> + .name = "qhs_ahb2phy3",
> + .id = LEMANS_SLAVE_AHB2PHY_3,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_anoc_throttle_cfg = {
> + .name = "qhs_anoc_throttle_cfg",
> + .id = LEMANS_SLAVE_ANOC_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_aoss = {
> + .name = "qhs_aoss",
> + .id = LEMANS_SLAVE_AOSS,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_apss = {
> + .name = "qhs_apss",
> + .id = LEMANS_SLAVE_APPSS,
> + .channels = 1,
> + .buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_boot_rom = {
> + .name = "qhs_boot_rom",
> + .id = LEMANS_SLAVE_BOOT_ROM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_cfg = {
> + .name = "qhs_camera_cfg",
> + .id = LEMANS_SLAVE_CAMERA_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
> + .name = "qhs_camera_nrt_throttle_cfg",
> + .id = LEMANS_SLAVE_CAMERA_NRT_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
> + .name = "qhs_camera_rt_throttle_cfg",
> + .id = LEMANS_SLAVE_CAMERA_RT_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_clk_ctl = {
> + .name = "qhs_clk_ctl",
> + .id = LEMANS_SLAVE_CLK_CTL,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_compute0_cfg = {
> + .name = "qhs_compute0_cfg",
> + .id = LEMANS_SLAVE_CDSP_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CDSP_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qhs_compute1_cfg = {
> + .name = "qhs_compute1_cfg",
> + .id = LEMANS_SLAVE_CDSP1_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CDSPB_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qhs_cpr_cx = {
> + .name = "qhs_cpr_cx",
> + .id = LEMANS_SLAVE_RBCPR_CX_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_mmcx = {
> + .name = "qhs_cpr_mmcx",
> + .id = LEMANS_SLAVE_RBCPR_MMCX_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_mx = {
> + .name = "qhs_cpr_mx",
> + .id = LEMANS_SLAVE_RBCPR_MX_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cpr_nspcx = {
> + .name = "qhs_cpr_nspcx",
> + .id = LEMANS_SLAVE_CPR_NSPCX,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_crypto0_cfg = {
> + .name = "qhs_crypto0_cfg",
> + .id = LEMANS_SLAVE_CRYPTO_0_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_cx_rdpm = {
> + .name = "qhs_cx_rdpm",
> + .id = LEMANS_SLAVE_CX_RDPM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display0_cfg = {
> + .name = "qhs_display0_cfg",
> + .id = LEMANS_SLAVE_DISPLAY_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
> + .name = "qhs_display0_rt_throttle_cfg",
> + .id = LEMANS_SLAVE_DISPLAY_RT_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display1_cfg = {
> + .name = "qhs_display1_cfg",
> + .id = LEMANS_SLAVE_DISPLAY1_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
> + .name = "qhs_display1_rt_throttle_cfg",
> + .id = LEMANS_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_emac0_cfg = {
> + .name = "qhs_emac0_cfg",
> + .id = LEMANS_SLAVE_EMAC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_emac1_cfg = {
> + .name = "qhs_emac1_cfg",
> + .id = LEMANS_SLAVE_EMAC1_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gp_dsp0_cfg = {
> + .name = "qhs_gp_dsp0_cfg",
> + .id = LEMANS_SLAVE_GP_DSP0_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gp_dsp1_cfg = {
> + .name = "qhs_gp_dsp1_cfg",
> + .id = LEMANS_SLAVE_GP_DSP1_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
> + .name = "qhs_gpdsp0_throttle_cfg",
> + .id = LEMANS_SLAVE_GPDSP0_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
> + .name = "qhs_gpdsp1_throttle_cfg",
> + .id = LEMANS_SLAVE_GPDSP1_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
> + .name = "qhs_gpu_tcu_throttle_cfg",
> + .id = LEMANS_SLAVE_GPU_TCU_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_gpuss_cfg = {
> + .name = "qhs_gpuss_cfg",
> + .id = LEMANS_SLAVE_GFX3D_CFG,
> + .channels = 1,
> + .buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_hwkm = {
> + .name = "qhs_hwkm",
> + .id = LEMANS_SLAVE_HWKM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_imem_cfg = {
> + .name = "qhs_imem_cfg",
> + .id = LEMANS_SLAVE_IMEM_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ipa = {
> + .name = "qhs_ipa",
> + .id = LEMANS_SLAVE_IPA_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ipc_router = {
> + .name = "qhs_ipc_router",
> + .id = LEMANS_SLAVE_IPC_ROUTER_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_cfg = {
> + .name = "qhs_lpass_cfg",
> + .id = LEMANS_SLAVE_LPASS,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CNOC_LPASS_AG_NOC },
> +};
> +
> +static struct qcom_icc_node qhs_lpass_throttle_cfg = {
> + .name = "qhs_lpass_throttle_cfg",
> + .id = LEMANS_SLAVE_LPASS_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_mx_rdpm = {
> + .name = "qhs_mx_rdpm",
> + .id = LEMANS_SLAVE_MX_RDPM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_mxc_rdpm = {
> + .name = "qhs_mxc_rdpm",
> + .id = LEMANS_SLAVE_MXC_RDPM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie0_cfg = {
> + .name = "qhs_pcie0_cfg",
> + .id = LEMANS_SLAVE_PCIE_0_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie1_cfg = {
> + .name = "qhs_pcie1_cfg",
> + .id = LEMANS_SLAVE_PCIE_1_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_rsc_cfg = {
> + .name = "qhs_pcie_rsc_cfg",
> + .id = LEMANS_SLAVE_PCIE_RSC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
> + .name = "qhs_pcie_tcu_throttle_cfg",
> + .id = LEMANS_SLAVE_PCIE_TCU_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pcie_throttle_cfg = {
> + .name = "qhs_pcie_throttle_cfg",
> + .id = LEMANS_SLAVE_PCIE_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pdm = {
> + .name = "qhs_pdm",
> + .id = LEMANS_SLAVE_PDM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pimem_cfg = {
> + .name = "qhs_pimem_cfg",
> + .id = LEMANS_SLAVE_PIMEM_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_pke_wrapper_cfg = {
> + .name = "qhs_pke_wrapper_cfg",
> + .id = LEMANS_SLAVE_PKA_WRAPPER_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qdss_cfg = {
> + .name = "qhs_qdss_cfg",
> + .id = LEMANS_SLAVE_QDSS_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qm_cfg = {
> + .name = "qhs_qm_cfg",
> + .id = LEMANS_SLAVE_QM_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qm_mpu_cfg = {
> + .name = "qhs_qm_mpu_cfg",
> + .id = LEMANS_SLAVE_QM_MPU_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup0 = {
> + .name = "qhs_qup0",
> + .id = LEMANS_SLAVE_QUP_0,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup1 = {
> + .name = "qhs_qup1",
> + .id = LEMANS_SLAVE_QUP_1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup2 = {
> + .name = "qhs_qup2",
> + .id = LEMANS_SLAVE_QUP_2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_qup3 = {
> + .name = "qhs_qup3",
> + .id = LEMANS_SLAVE_QUP_3,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_sail_throttle_cfg = {
> + .name = "qhs_sail_throttle_cfg",
> + .id = LEMANS_SLAVE_SAIL_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_sdc1 = {
> + .name = "qhs_sdc1",
> + .id = LEMANS_SLAVE_SDC1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_security = {
> + .name = "qhs_security",
> + .id = LEMANS_SLAVE_SECURITY,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_snoc_throttle_cfg = {
> + .name = "qhs_snoc_throttle_cfg",
> + .id = LEMANS_SLAVE_SNOC_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tcsr = {
> + .name = "qhs_tcsr",
> + .id = LEMANS_SLAVE_TCSR,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tlmm = {
> + .name = "qhs_tlmm",
> + .id = LEMANS_SLAVE_TLMM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_tsc_cfg = {
> + .name = "qhs_tsc_cfg",
> + .id = LEMANS_SLAVE_TSC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ufs_card_cfg = {
> + .name = "qhs_ufs_card_cfg",
> + .id = LEMANS_SLAVE_UFS_CARD_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_ufs_mem_cfg = {
> + .name = "qhs_ufs_mem_cfg",
> + .id = LEMANS_SLAVE_UFS_MEM_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb2_0 = {
> + .name = "qhs_usb2_0",
> + .id = LEMANS_SLAVE_USB2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb3_0 = {
> + .name = "qhs_usb3_0",
> + .id = LEMANS_SLAVE_USB3_0,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_usb3_1 = {
> + .name = "qhs_usb3_1",
> + .id = LEMANS_SLAVE_USB3_1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_cfg = {
> + .name = "qhs_venus_cfg",
> + .id = LEMANS_SLAVE_VENUS_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
> + .name = "qhs_venus_cvp_throttle_cfg",
> + .id = LEMANS_SLAVE_VENUS_CVP_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
> + .name = "qhs_venus_v_cpu_throttle_cfg",
> + .id = LEMANS_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
> + .name = "qhs_venus_vcodec_throttle_cfg",
> + .id = LEMANS_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_ddrss_cfg = {
> + .name = "qns_ddrss_cfg",
> + .id = LEMANS_SLAVE_DDRSS_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CNOC_DC_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gpdsp_noc_cfg = {
> + .name = "qns_gpdsp_noc_cfg",
> + .id = LEMANS_SLAVE_GPDSP_NOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_mnoc_hf_cfg = {
> + .name = "qns_mnoc_hf_cfg",
> + .id = LEMANS_SLAVE_CNOC_MNOC_HF_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CNOC_MNOC_HF_CFG },
> +};
> +
> +static struct qcom_icc_node qns_mnoc_sf_cfg = {
> + .name = "qns_mnoc_sf_cfg",
> + .id = LEMANS_SLAVE_CNOC_MNOC_SF_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_CNOC_MNOC_SF_CFG },
> +};
> +
> +static struct qcom_icc_node qns_pcie_anoc_cfg = {
> + .name = "qns_pcie_anoc_cfg",
> + .id = LEMANS_SLAVE_PCIE_ANOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_snoc_cfg = {
> + .name = "qns_snoc_cfg",
> + .id = LEMANS_SLAVE_SNOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_SNOC_CFG },
> +};
> +
> +static struct qcom_icc_node qxs_boot_imem = {
> + .name = "qxs_boot_imem",
> + .id = LEMANS_SLAVE_BOOT_IMEM,
> + .channels = 1,
> + .buswidth = 16,
> +};
> +
> +static struct qcom_icc_node qxs_imem = {
> + .name = "qxs_imem",
> + .id = LEMANS_SLAVE_IMEM,
> + .channels = 1,
> + .buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qxs_pimem = {
> + .name = "qxs_pimem",
> + .id = LEMANS_SLAVE_PIMEM,
> + .channels = 1,
> + .buswidth = 8,
> +};
> +
> +static struct qcom_icc_node xs_pcie_0 = {
> + .name = "xs_pcie_0",
> + .id = LEMANS_SLAVE_PCIE_0,
> + .channels = 1,
> + .buswidth = 16,
> +};
> +
> +static struct qcom_icc_node xs_pcie_1 = {
> + .name = "xs_pcie_1",
> + .id = LEMANS_SLAVE_PCIE_1,
> + .channels = 1,
> + .buswidth = 32,
> +};
> +
> +static struct qcom_icc_node xs_qdss_stm = {
> + .name = "xs_qdss_stm",
> + .id = LEMANS_SLAVE_QDSS_STM,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node xs_sys_tcu_cfg = {
> + .name = "xs_sys_tcu_cfg",
> + .id = LEMANS_SLAVE_TCU,
> + .channels = 1,
> + .buswidth = 8,
> +};
> +
> +static struct qcom_icc_node qhs_llcc = {
> + .name = "qhs_llcc",
> + .id = LEMANS_SLAVE_LLCC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_gemnoc = {
> + .name = "qns_gemnoc",
> + .id = LEMANS_SLAVE_GEM_NOC_CFG,
> + .channels = 1,
> + .buswidth = 4,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_GEM_NOC_CFG },
> +};
> +
> +static struct qcom_icc_node qns_gem_noc_cnoc = {
> + .name = "qns_gem_noc_cnoc",
> + .id = LEMANS_SLAVE_GEM_NOC_CNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_GEM_NOC_CNOC },
> +};
> +
> +static struct qcom_icc_node qns_llcc = {
> + .name = "qns_llcc",
> + .id = LEMANS_SLAVE_LLCC,
> + .channels = 6,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_LLCC },
> +};
> +
> +static struct qcom_icc_node qns_pcie = {
> + .name = "qns_pcie",
> + .id = LEMANS_SLAVE_GEM_NOC_PCIE_CNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_GEM_NOC_PCIE_SNOC },
> +};
> +
> +static struct qcom_icc_node srvc_even_gemnoc = {
> + .name = "srvc_even_gemnoc",
> + .id = LEMANS_SLAVE_SERVICE_GEM_NOC_1,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_odd_gemnoc = {
> + .name = "srvc_odd_gemnoc",
> + .id = LEMANS_SLAVE_SERVICE_GEM_NOC_2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_sys_gemnoc = {
> + .name = "srvc_sys_gemnoc",
> + .id = LEMANS_SLAVE_SERVICE_GEM_NOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_sys_gemnoc_2 = {
> + .name = "srvc_sys_gemnoc_2",
> + .id = LEMANS_SLAVE_SERVICE_GEM_NOC2,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_gp_dsp_sail_noc = {
> + .name = "qns_gp_dsp_sail_noc",
> + .id = LEMANS_SLAVE_GP_DSP_SAIL_NOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_GPDSP_SAIL },
> +};
> +
> +static struct qcom_icc_node qhs_lpass_core = {
> + .name = "qhs_lpass_core",
> + .id = LEMANS_SLAVE_LPASS_CORE_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_lpi = {
> + .name = "qhs_lpass_lpi",
> + .id = LEMANS_SLAVE_LPASS_LPI_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_mpu = {
> + .name = "qhs_lpass_mpu",
> + .id = LEMANS_SLAVE_LPASS_MPU_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qhs_lpass_top = {
> + .name = "qhs_lpass_top",
> + .id = LEMANS_SLAVE_LPASS_TOP_CFG,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_sysnoc = {
> + .name = "qns_sysnoc",
> + .id = LEMANS_SLAVE_LPASS_SNOC,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_LPASS_ANOC },
> +};
> +
> +static struct qcom_icc_node srvc_niu_aml_noc = {
> + .name = "srvc_niu_aml_noc",
> + .id = LEMANS_SLAVE_SERVICES_LPASS_AML_NOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_niu_lpass_agnoc = {
> + .name = "srvc_niu_lpass_agnoc",
> + .id = LEMANS_SLAVE_SERVICE_LPASS_AG_NOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node ebi = {
> + .name = "ebi",
> + .id = LEMANS_SLAVE_EBI1,
> + .channels = 8,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_mem_noc_hf = {
> + .name = "qns_mem_noc_hf",
> + .id = LEMANS_SLAVE_MNOC_HF_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_MNOC_HF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_mem_noc_sf = {
> + .name = "qns_mem_noc_sf",
> + .id = LEMANS_SLAVE_MNOC_SF_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_MNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node srvc_mnoc_hf = {
> + .name = "srvc_mnoc_hf",
> + .id = LEMANS_SLAVE_SERVICE_MNOC_HF,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node srvc_mnoc_sf = {
> + .name = "srvc_mnoc_sf",
> + .id = LEMANS_SLAVE_SERVICE_MNOC_SF,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_hcp = {
> + .name = "qns_hcp",
> + .id = LEMANS_SLAVE_HCP_A,
> + .channels = 2,
> + .buswidth = 32,
> +};
> +
> +static struct qcom_icc_node qns_nsp_gemnoc = {
> + .name = "qns_nsp_gemnoc",
> + .id = LEMANS_SLAVE_CDSP_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_COMPUTE_NOC },
> +};
> +
> +static struct qcom_icc_node service_nsp_noc = {
> + .name = "service_nsp_noc",
> + .id = LEMANS_SLAVE_SERVICE_NSP_NOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_nspb_gemnoc = {
> + .name = "qns_nspb_gemnoc",
> + .id = LEMANS_SLAVE_CDSPB_MEM_NOC,
> + .channels = 2,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_COMPUTE_NOC_1 },
> +};
> +
> +static struct qcom_icc_node qns_nspb_hcp = {
> + .name = "qns_nspb_hcp",
> + .id = LEMANS_SLAVE_HCP_B,
> + .channels = 2,
> + .buswidth = 32,
> +};
> +
> +static struct qcom_icc_node service_nspb_noc = {
> + .name = "service_nspb_noc",
> + .id = LEMANS_SLAVE_SERVICE_NSPB_NOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_node qns_pcie_mem_noc = {
> + .name = "qns_pcie_mem_noc",
> + .id = LEMANS_SLAVE_ANOC_PCIE_GEM_NOC,
> + .channels = 1,
> + .buswidth = 32,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_ANOC_PCIE_GEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gemnoc_gc = {
> + .name = "qns_gemnoc_gc",
> + .id = LEMANS_SLAVE_SNOC_GEM_NOC_GC,
> + .channels = 1,
> + .buswidth = 8,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_SNOC_GC_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node qns_gemnoc_sf = {
> + .name = "qns_gemnoc_sf",
> + .id = LEMANS_SLAVE_SNOC_GEM_NOC_SF,
> + .channels = 1,
> + .buswidth = 16,
> + .num_links = 1,
> + .links = { LEMANS_MASTER_SNOC_SF_MEM_NOC },
> +};
> +
> +static struct qcom_icc_node srvc_snoc = {
> + .name = "srvc_snoc",
> + .id = LEMANS_SLAVE_SERVICE_SNOC,
> + .channels = 1,
> + .buswidth = 4,
> +};
> +
> +static struct qcom_icc_bcm bcm_acv = {
> + .name = "ACV",
> + .num_nodes = 1,
> + .nodes = { &ebi },
> +};
> +
> +static struct qcom_icc_bcm bcm_ce0 = {
> + .name = "CE0",
> + .num_nodes = 2,
> + .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn0 = {
> + .name = "CN0",
> + .keepalive = true,
> + .num_nodes = 2,
> + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn1 = {
> + .name = "CN1",
> + .num_nodes = 76,
> + .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
> + &qhs_ahb2phy2, &qhs_ahb2phy3,
> + &qhs_anoc_throttle_cfg, &qhs_aoss,
> + &qhs_apss, &qhs_boot_rom,
> + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
> + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
> + &qhs_compute0_cfg, &qhs_compute1_cfg,
> + &qhs_cpr_cx, &qhs_cpr_mmcx,
> + &qhs_cpr_mx, &qhs_cpr_nspcx,
> + &qhs_crypto0_cfg, &qhs_cx_rdpm,
> + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
> + &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
> + &qhs_emac0_cfg, &qhs_emac1_cfg,
> + &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
> + &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
> + &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
> + &qhs_hwkm, &qhs_imem_cfg,
> + &qhs_ipa, &qhs_ipc_router,
> + &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
> + &qhs_mx_rdpm, &qhs_mxc_rdpm,
> + &qhs_pcie0_cfg, &qhs_pcie1_cfg,
> + &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
> + &qhs_pcie_throttle_cfg, &qhs_pdm,
> + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
> + &qhs_qdss_cfg, &qhs_qm_cfg,
> + &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
> + &qhs_sdc1, &qhs_security,
> + &qhs_snoc_throttle_cfg, &qhs_tcsr,
> + &qhs_tlmm, &qhs_tsc_cfg,
> + &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
> + &qhs_usb2_0, &qhs_usb3_0,
> + &qhs_usb3_1, &qhs_venus_cfg,
> + &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
> + &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
> + &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
> + &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
> + &qns_snoc_cfg, &qxs_boot_imem,
> + &qxs_imem, &xs_sys_tcu_cfg },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn2 = {
> + .name = "CN2",
> + .num_nodes = 4,
> + .nodes = { &qhs_qup0, &qhs_qup1,
> + &qhs_qup2, &qhs_qup3 },
> +};
> +
> +static struct qcom_icc_bcm bcm_cn3 = {
> + .name = "CN3",
> + .num_nodes = 2,
> + .nodes = { &xs_pcie_0, &xs_pcie_1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_gna0 = {
> + .name = "GNA0",
> + .num_nodes = 1,
> + .nodes = { &qxm_dsp0 },
> +};
> +
> +static struct qcom_icc_bcm bcm_gnb0 = {
> + .name = "GNB0",
> + .num_nodes = 1,
> + .nodes = { &qxm_dsp1 },
> +};
> +
> +static struct qcom_icc_bcm bcm_mc0 = {
> + .name = "MC0",
> + .keepalive = true,
> + .num_nodes = 1,
> + .nodes = { &ebi },
> +};
> +
> +static struct qcom_icc_bcm bcm_mm0 = {
> + .name = "MM0",
> + .keepalive = true,
> + .num_nodes = 5,
> + .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
> + &qnm_mdp0_1, &qnm_mdp1_0,
> + &qns_mem_noc_hf },
> +};
> +
> +static struct qcom_icc_bcm bcm_mm1 = {
> + .name = "MM1",
> + .num_nodes = 7,
> + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
> + &qnm_video0, &qnm_video1,
> + &qnm_video_cvp, &qnm_video_v_cpu,
> + &qns_mem_noc_sf },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsa0 = {
> + .name = "NSA0",
> + .num_nodes = 2,
> + .nodes = { &qns_hcp, &qns_nsp_gemnoc },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsa1 = {
> + .name = "NSA1",
> + .num_nodes = 1,
> + .nodes = { &qxm_nsp },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsb0 = {
> + .name = "NSB0",
> + .num_nodes = 2,
> + .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
> +};
> +
> +static struct qcom_icc_bcm bcm_nsb1 = {
> + .name = "NSB1",
> + .num_nodes = 1,
> + .nodes = { &qxm_nspb },
> +};
> +
> +static struct qcom_icc_bcm bcm_pci0 = {
> + .name = "PCI0",
> + .num_nodes = 1,
> + .nodes = { &qns_pcie_mem_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup0 = {
> + .name = "QUP0",
> + .vote_scale = 1,
> + .num_nodes = 1,
> + .nodes = { &qup0_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup1 = {
> + .name = "QUP1",
> + .vote_scale = 1,
> + .num_nodes = 1,
> + .nodes = { &qup1_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_qup2 = {
> + .name = "QUP2",
> + .vote_scale = 1,
> + .num_nodes = 2,
> + .nodes = { &qup2_core_slave, &qup3_core_slave },
> +};
> +
> +static struct qcom_icc_bcm bcm_sh0 = {
> + .name = "SH0",
> + .keepalive = true,
> + .num_nodes = 1,
> + .nodes = { &qns_llcc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sh2 = {
> + .name = "SH2",
> + .num_nodes = 1,
> + .nodes = { &chm_apps },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn0 = {
> + .name = "SN0",
> + .keepalive = true,
> + .num_nodes = 1,
> + .nodes = { &qns_gemnoc_sf },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn1 = {
> + .name = "SN1",
> + .num_nodes = 1,
> + .nodes = { &qns_gemnoc_gc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn2 = {
> + .name = "SN2",
> + .num_nodes = 1,
> + .nodes = { &qxs_pimem },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn3 = {
> + .name = "SN3",
> + .num_nodes = 2,
> + .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn4 = {
> + .name = "SN4",
> + .num_nodes = 2,
> + .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn9 = {
> + .name = "SN9",
> + .num_nodes = 2,
> + .nodes = { &qns_sysnoc, &qnm_lpass_noc },
> +};
> +
> +static struct qcom_icc_bcm bcm_sn10 = {
> + .name = "SN10",
> + .num_nodes = 1,
> + .nodes = { &xs_qdss_stm },
> +};
> +
> +static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
> + &bcm_sn3,
> +};
> +
> +static struct qcom_icc_node *aggre1_noc_nodes[] = {
> + [MASTER_QUP_3] = &qxm_qup3,
> + [MASTER_EMAC] = &xm_emac_0,
> + [MASTER_EMAC_1] = &xm_emac_1,
> + [MASTER_SDC] = &xm_sdc1,
> + [MASTER_UFS_MEM] = &xm_ufs_mem,
> + [MASTER_USB2] = &xm_usb2_2,
> + [MASTER_USB3_0] = &xm_usb3_0,
> + [MASTER_USB3_1] = &xm_usb3_1,
> + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_aggre1_noc = {
> + .nodes = aggre1_noc_nodes,
> + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
> + .bcms = aggre1_noc_bcms,
> + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
> + &bcm_ce0,
> + &bcm_sn4,
> +};
> +
> +static struct qcom_icc_node *aggre2_noc_nodes[] = {
> + [MASTER_QDSS_BAM] = &qhm_qdss_bam,
> + [MASTER_QUP_0] = &qhm_qup0,
> + [MASTER_QUP_1] = &qhm_qup1,
> + [MASTER_QUP_2] = &qhm_qup2,
> + [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
> + [MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
> + [MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
> + [MASTER_IPA] = &qxm_ipa,
> + [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
> + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
> + [MASTER_UFS_CARD] = &xm_ufs_card,
> + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_aggre2_noc = {
> + .nodes = aggre2_noc_nodes,
> + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
> + .bcms = aggre2_noc_bcms,
> + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *clk_virt_bcms[] = {
> + &bcm_qup0,
> + &bcm_qup1,
> + &bcm_qup2,
> +};
> +
> +static struct qcom_icc_node *clk_virt_nodes[] = {
> + [MASTER_QUP_CORE_0] = &qup0_core_master,
> + [MASTER_QUP_CORE_1] = &qup1_core_master,
> + [MASTER_QUP_CORE_2] = &qup2_core_master,
> + [MASTER_QUP_CORE_3] = &qup3_core_master,
> + [SLAVE_QUP_CORE_0] = &qup0_core_slave,
> + [SLAVE_QUP_CORE_1] = &qup1_core_slave,
> + [SLAVE_QUP_CORE_2] = &qup2_core_slave,
> + [SLAVE_QUP_CORE_3] = &qup3_core_slave,
> +};
> +
> +static struct qcom_icc_desc sa8775p_clk_virt = {
> + .nodes = clk_virt_nodes,
> + .num_nodes = ARRAY_SIZE(clk_virt_nodes),
> + .bcms = clk_virt_bcms,
> + .num_bcms = ARRAY_SIZE(clk_virt_bcms),
> +};
> +
> +static struct qcom_icc_bcm *config_noc_bcms[] = {
> + &bcm_cn0,
> + &bcm_cn1,
> + &bcm_cn2,
> + &bcm_cn3,
> + &bcm_sn2,
> + &bcm_sn10,
> +};
> +
> +static struct qcom_icc_node *config_noc_nodes[] = {
> + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
> + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
> + [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
> + [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
> + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
> + [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
> + [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
> + [SLAVE_AOSS] = &qhs_aoss,
> + [SLAVE_APPSS] = &qhs_apss,
> + [SLAVE_BOOT_ROM] = &qhs_boot_rom,
> + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
> + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
> + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
> + [SLAVE_CLK_CTL] = &qhs_clk_ctl,
> + [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
> + [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
> + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
> + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
> + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
> + [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
> + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
> + [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
> + [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
> + [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
> + [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
> + [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
> + [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
> + [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
> + [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
> + [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
> + [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
> + [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
> + [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
> + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
> + [SLAVE_HWKM] = &qhs_hwkm,
> + [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
> + [SLAVE_IPA_CFG] = &qhs_ipa,
> + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
> + [SLAVE_LPASS] = &qhs_lpass_cfg,
> + [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
> + [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
> + [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
> + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
> + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
> + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
> + [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
> + [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
> + [SLAVE_PDM] = &qhs_pdm,
> + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
> + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
> + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
> + [SLAVE_QM_CFG] = &qhs_qm_cfg,
> + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
> + [SLAVE_QUP_0] = &qhs_qup0,
> + [SLAVE_QUP_1] = &qhs_qup1,
> + [SLAVE_QUP_2] = &qhs_qup2,
> + [SLAVE_QUP_3] = &qhs_qup3,
> + [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
> + [SLAVE_SDC1] = &qhs_sdc1,
> + [SLAVE_SECURITY] = &qhs_security,
> + [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
> + [SLAVE_TCSR] = &qhs_tcsr,
> + [SLAVE_TLMM] = &qhs_tlmm,
> + [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
> + [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
> + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
> + [SLAVE_USB2] = &qhs_usb2_0,
> + [SLAVE_USB3_0] = &qhs_usb3_0,
> + [SLAVE_USB3_1] = &qhs_usb3_1,
> + [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
> + [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
> + [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
> + [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
> + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
> + [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
> + [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
> + [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
> + [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
> + [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
> + [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
> + [SLAVE_IMEM] = &qxs_imem,
> + [SLAVE_PIMEM] = &qxs_pimem,
> + [SLAVE_PCIE_0] = &xs_pcie_0,
> + [SLAVE_PCIE_1] = &xs_pcie_1,
> + [SLAVE_QDSS_STM] = &xs_qdss_stm,
> + [SLAVE_TCU] = &xs_sys_tcu_cfg,
> +};
> +
> +static struct qcom_icc_desc sa8775p_config_noc = {
> + .nodes = config_noc_nodes,
> + .num_nodes = ARRAY_SIZE(config_noc_nodes),
> + .bcms = config_noc_bcms,
> + .num_bcms = ARRAY_SIZE(config_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *dc_noc_bcms[] = {
> +};
> +
> +static struct qcom_icc_node *dc_noc_nodes[] = {
> + [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
> + [SLAVE_LLCC_CFG] = &qhs_llcc,
> + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_dc_noc = {
> + .nodes = dc_noc_nodes,
> + .num_nodes = ARRAY_SIZE(dc_noc_nodes),
> + .bcms = dc_noc_bcms,
> + .num_bcms = ARRAY_SIZE(dc_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *gem_noc_bcms[] = {
> + &bcm_sh0,
> + &bcm_sh2,
> +};
> +
> +static struct qcom_icc_node *gem_noc_nodes[] = {
> + [MASTER_GPU_TCU] = &alm_gpu_tcu,
> + [MASTER_PCIE_TCU] = &alm_pcie_tcu,
> + [MASTER_SYS_TCU] = &alm_sys_tcu,
> + [MASTER_APPSS_PROC] = &chm_apps,
> + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
> + [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
> + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
> + [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
> + [MASTER_GFX3D] = &qnm_gpu,
> + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
> + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
> + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
> + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
> + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
> + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
> + [SLAVE_LLCC] = &qns_llcc,
> + [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
> + [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
> + [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
> + [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
> + [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
> +};
> +
> +static struct qcom_icc_desc sa8775p_gem_noc = {
> + .nodes = gem_noc_nodes,
> + .num_nodes = ARRAY_SIZE(gem_noc_nodes),
> + .bcms = gem_noc_bcms,
> + .num_bcms = ARRAY_SIZE(gem_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
> + &bcm_gna0,
> + &bcm_gnb0,
> +};
> +
> +static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
> + [MASTER_DSP0] = &qxm_dsp0,
> + [MASTER_DSP1] = &qxm_dsp1,
> + [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_gpdsp_anoc = {
> + .nodes = gpdsp_anoc_nodes,
> + .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
> + .bcms = gpdsp_anoc_bcms,
> + .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
> + &bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
> + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
> + [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
> + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
> + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
> + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
> + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
> + [SLAVE_LPASS_SNOC] = &qns_sysnoc,
> + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
> + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_lpass_ag_noc = {
> + .nodes = lpass_ag_noc_nodes,
> + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
> + .bcms = lpass_ag_noc_bcms,
> + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *mc_virt_bcms[] = {
> + &bcm_acv,
> + &bcm_mc0,
> +};
> +
> +static struct qcom_icc_node *mc_virt_nodes[] = {
> + [MASTER_LLCC] = &llcc_mc,
> + [SLAVE_EBI1] = &ebi,
> +};
> +
> +static struct qcom_icc_desc sa8775p_mc_virt = {
> + .nodes = mc_virt_nodes,
> + .num_nodes = ARRAY_SIZE(mc_virt_nodes),
> + .bcms = mc_virt_bcms,
> + .num_bcms = ARRAY_SIZE(mc_virt_bcms),
> +};
> +
> +static struct qcom_icc_bcm *mmss_noc_bcms[] = {
> + &bcm_mm0,
> + &bcm_mm1,
> +};
> +
> +static struct qcom_icc_node *mmss_noc_nodes[] = {
> + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
> + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
> + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
> + [MASTER_MDP0] = &qnm_mdp0_0,
> + [MASTER_MDP1] = &qnm_mdp0_1,
> + [MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
> + [MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
> + [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
> + [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
> + [MASTER_VIDEO_P0] = &qnm_video0,
> + [MASTER_VIDEO_P1] = &qnm_video1,
> + [MASTER_VIDEO_PROC] = &qnm_video_cvp,
> + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
> + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
> + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
> + [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
> + [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
> +};
> +
> +static struct qcom_icc_desc sa8775p_mmss_noc = {
> + .nodes = mmss_noc_nodes,
> + .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
> + .bcms = mmss_noc_bcms,
> + .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *nspa_noc_bcms[] = {
> + &bcm_nsa0,
> + &bcm_nsa1,
> +};
> +
> +static struct qcom_icc_node *nspa_noc_nodes[] = {
> + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
> + [MASTER_CDSP_PROC] = &qxm_nsp,
> + [SLAVE_HCP_A] = &qns_hcp,
> + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
> + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_nspa_noc = {
> + .nodes = nspa_noc_nodes,
> + .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
> + .bcms = nspa_noc_bcms,
> + .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *nspb_noc_bcms[] = {
> + &bcm_nsb0,
> + &bcm_nsb1,
> +};
> +
> +static struct qcom_icc_node *nspb_noc_nodes[] = {
> + [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
> + [MASTER_CDSP_PROC_B] = &qxm_nspb,
> + [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
> + [SLAVE_HCP_B] = &qns_nspb_hcp,
> + [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_nspb_noc = {
> + .nodes = nspb_noc_nodes,
> + .num_nodes = ARRAY_SIZE(nspb_noc_nodes),
> + .bcms = nspb_noc_bcms,
> + .num_bcms = ARRAY_SIZE(nspb_noc_bcms),
> +
> +};
> +
> +static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
> + &bcm_pci0,
> +};
> +
> +static struct qcom_icc_node *pcie_anoc_nodes[] = {
> + [MASTER_PCIE_0] = &xm_pcie3_0,
> + [MASTER_PCIE_1] = &xm_pcie3_1,
> + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_pcie_anoc = {
> + .nodes = pcie_anoc_nodes,
> + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
> + .bcms = pcie_anoc_bcms,
> + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {
> + &bcm_sn0,
> + &bcm_sn1,
> + &bcm_sn3,
> + &bcm_sn4,
> + &bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {
> + [MASTER_GIC_AHB] = &qhm_gic,
> + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
> + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
> + [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
> + [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
> + [MASTER_PIMEM] = &qxm_pimem,
> + [MASTER_GIC] = &xm_gic,
> + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
> + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
> + [SLAVE_SERVICE_SNOC] = &srvc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_system_noc = {
> + .nodes = system_noc_nodes,
> + .num_nodes = ARRAY_SIZE(system_noc_nodes),
> + .bcms = system_noc_bcms,
> + .num_bcms = ARRAY_SIZE(system_noc_bcms),
> +};
> +
> +static const struct of_device_id qnoc_of_match[] = {
> + { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
> + { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
> + { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
> + { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
> + { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
> + { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
> + { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
> + { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
> + { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
> + { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
> + { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
> + { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
> + { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
> + { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, qnoc_of_match);
> +
> +static struct platform_driver qnoc_driver = {
> + .probe = qcom_icc_rpmh_probe,
> + .remove = qcom_icc_rpmh_remove,
> + .driver = {
> + .name = "qnoc-sa8775p",
> + .of_match_table = qnoc_of_match,
> + .sync_state = icc_sync_state,
> + },
> +};
> +
> +static int __init qnoc_driver_init(void)
> +{
> + return platform_driver_register(&qnoc_driver);
> +}
> +core_initcall(qnoc_driver_init);
> +
> +static void __exit qnoc_driver_exit(void)
> +{
> + platform_driver_unregister(&qnoc_driver);
> +}
> +module_exit(qnoc_driver_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
> +MODULE_LICENSE("GPL");

2023-01-09 18:21:36

[permalink] [raw]

Subject: [PATCH 17/18] dt-bindings: arm: qcom: document the sa8775p reference board

From: Bartosz Golaszewski <[email protected]>

Add a new compatible for the sa8775p-ride board.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 27063a045bd0..7490eb0c3e3c 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -751,6 +751,11 @@ properties:
- const: qcom,qcs404-evb
- const: qcom,qcs404

+ - items:
+ - enum:
+ - qcom,sa8775p-ride
+ - const: qcom,sa8775p
+
- items:
- enum:
- qcom,sa8155p-adp
--
2.37.2

2023-01-09 18:22:02

[permalink] [raw]

Subject: [PATCH 13/18] dt-bindings: power: qcom,rpmpd: document sa8775p

From: Bartosz Golaszewski <[email protected]>

Add a compatible for sa8775p platforms and relevant defines to the include
file.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom-rpmpd.h | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 633d49884019..1778d9851510 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,qcs404-rpmpd
- qcom,qdu1000-rpmhpd
- qcom,sa8540p-rpmhpd
+ - qcom,sa8775p-rpmhpd
- qcom,sdm660-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sc7280-rpmhpd
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 1e19e258a74d..3117bf7d5ebf 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -4,6 +4,25 @@
#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
#define _DT_BINDINGS_POWER_QCOM_RPMPD_H

+/* SA8775P Power Domain Indexes */
+#define SA8775P_CX 0
+#define SA8775P_CX_AO 1
+#define SA8775P_DDR 2
+#define SA8775P_EBI 3
+#define SA8775P_GFX 4
+#define SA8775P_LCX 5
+#define SA8775P_LMX 6
+#define SA8775P_MMCX 7
+#define SA8775P_MMCX_AO 8
+#define SA8775P_MSS 9
+#define SA8775P_MX 10
+#define SA8775P_MX_AO 11
+#define SA8775P_MXC 12
+#define SA8775P_MXC_AO 13
+#define SA8775P_NSP0 14
+#define SA8775P_NSP1 15
+#define SA8775P_XO 16
+
/* SDM670 Power Domain Indexes */
#define SDM670_MX 0
#define SDM670_MX_AO 1
--
2.37.2

2023-01-09 18:22:25

[permalink] [raw]

Subject: Re: [PATCH 11/18] arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P platforms

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Enable the Qualcomm SA8775P TLMM pinctrl and GPIO driver. It needs to be
> built-in for UART to provide a console.

One defconfig patch for entire SA8775p patchset. There is no point to
enable piece by piece because anyway each defconfig will have to go via
qcom soc tree.

Best regards,
Krzysztof

2023-01-09 18:35:48

[permalink] [raw]

Subject: Re: [PATCH 12/18] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add a compatible for the ipcc on sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2023-01-09 18:37:36

[permalink] [raw]

Subject: Re: [PATCH 17/18] dt-bindings: arm: qcom: document the sa8775p reference board

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add a new compatible for the sa8775p-ride board.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 27063a045bd0..7490eb0c3e3c 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -751,6 +751,11 @@ properties:
> - const: qcom,qcs404-evb
> - const: qcom,qcs404

You miss the update of SoC in this file (beginning).

>

Best regards,
Krzysztof

2023-01-09 18:38:32

[permalink] [raw]

Subject: Re: [PATCH 18/18] arm64: dts: qcom: add initial support for qcom sa8775p-ride

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> This adds basic support for the Qualcomm sa8775p platform and the
> reference board: sa8775p-ride. The dt files describe the basics of the
> SoC and enable booting to shell.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 +
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 ++++++++++++++++++++++
> 3 files changed, 881 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..39b8206f7131 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> new file mode 100644
> index 000000000000..d4dae32a84cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +
> +/ {
> + model = "Qualcomm SA8875P Ride";
> + compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
> +
> + aliases {
> + serial0 = &uart10;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&uart10 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart10_state>;
> +};
> +
> +&tlmm {
> + qup_uart10_state: qup_uart10_state {
the node names (between ':' and '{') should end in -state,
but the label does not have to. In fact, you'll probably want
to have a "default" and a "sleep" state with different drive-strength
and bias properties.

> + pins = "gpio46", "gpio47";
> + function = "qup1_se3";
> + };
> +};
Missing xo rate override.

> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> new file mode 100644
> index 000000000000..1a3b11628e38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -0,0 +1,841 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
> + xo_board_clk: xo-board-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-release-addr = <0x0 0x90000000>;
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_2>;
> + L2_2: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_3>;
> + L2_3: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@10000 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + next-level-cache = <&L2_4>;
> + L2_4: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + L3_1: l3-cache {
> + compatible = "cache";
> + };
> +
> + };
> + };
> +
> + CPU5: cpu@10100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_5>;
> + L2_5: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + CPU6: cpu@10200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_6>;
> + L2_6: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + CPU7: cpu@10300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_7>;
> + L2_7: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> +
> + core1 {
> + cpu = <&CPU5>;
> + };
> +
> + core2 {
> + cpu = <&CPU6>;
> + };
> +
> + core3 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
On other SoCs we define a single DynamIQ cluster, is it something
we should change?
> + };
> +
> + /* Will be updated by the bootloader. */
> + memory {
The memory node should have a unit address, probably 0x80000000 in
your case, but please doublecheck (for example by reading the value
from /sys/firmware/)
> + device_type = "memory";
> + reg = <0 0 0 0>;
0x0 please

> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + sail_ss_mem: sail_ss_region@80000000 {
No underscores in node names, use -s instead.

> + no-map;
> + reg = <0x0 0x80000000 0x0 0x10000000>;
Please put reg above no-map.

> + };
> +
> + hyp_mem: hyp_region@90000000 {
> + no-map;
> + reg = <0x0 0x90000000 0x0 0x600000>;
> + };
> +
> + xbl_boot_mem: xbl_boot_region@90600000 {
> + no-map;
> + reg = <0x0 0x90600000 0x0 0x200000>;
> + };
> +
> + aop_image_mem: aop_image_region@90800000 {
> + no-map;
> + reg = <0x0 0x90800000 0x0 0x60000>;
> + };
> +
> + aop_cmd_db_mem: aop_cmd_db_region@90860000 {
> + compatible = "qcom,cmd-db";
> + no-map;
> + reg = <0x0 0x90860000 0x0 0x20000>;
> + };
> +
> + uefi_log: uefi_log_region@908b0000 {
> + no-map;
> + reg = <0x0 0x908b0000 0x0 0x10000>;
> + };
> +
> + reserved_mem: reserved_region@908f0000 {
> + no-map;
> + reg = <0x0 0x908f0000 0x0 0xf000>;
> + };
> +
> + secdata_apss_mem: secdata_apss_region@908ff000 {
> + no-map;
> + reg = <0x0 0x908ff000 0x0 0x1000>;
> + };
> +
> + smem_mem: smem_region@90900000 {
> + compatible = "qcom,smem";
> + reg = <0x0 0x90900000 0x0 0x200000>;
> + no-map;
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + cpucp_fw_mem: cpucp_fw_region@90b00000 {
> + no-map;
> + reg = <0x0 0x90b00000 0x0 0x100000>;
> + };
> +
> + lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 {
> + no-map;
> + reg = <0x0 0x93b00000 0x0 0xf00000>;
> + };
> +
> + adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 {
> + no-map;
> + reg = <0x0 0x94a00000 0x0 0x800000>;
> + };
> +
> + pil_camera_mem: pil_camera_region@95200000 {
> + no-map;
> + reg = <0x0 0x95200000 0x0 0x500000>;
> + };
> +
> + pil_adsp_mem: pil_adsp_region@95c00000 {
> + no-map;
> + reg = <0x0 0x95c00000 0x0 0x1e00000>;
> + };
> +
> + pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
> + no-map;
> + reg = <0x0 0x97b00000 0x0 0x1e00000>;
> + };
> +
> + pil_gdsp1_mem: pil_gdsp1_region@99900000 {
> + no-map;
> + reg = <0x0 0x99900000 0x0 0x1e00000>;
> + };
> +
> + pil_cdsp0_mem: pil_cdsp0_region@9b800000 {
> + no-map;
> + reg = <0x0 0x9b800000 0x0 0x1e00000>;
> + };
> +
> + pil_gpu_mem: pil_gpu_region@9d600000 {
> + no-map;
> + reg = <0x0 0x9d600000 0x0 0x2000>;
> + };
> +
> + pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
> + no-map;
> + reg = <0x0 0x9d700000 0x0 0x1e00000>;
> + };
> +
> + pil_cvp_mem: pil_cvp_region@9f500000 {
> + no-map;
> + reg = <0x0 0x9f500000 0x0 0x700000>;
> + };
> +
> + pil_video_mem: pil_video_region@9fc00000 {
> + no-map;
> + reg = <0x0 0x9fc00000 0x0 0x700000>;
> + };
> +
> + hyptz_reserved_mem: hyptz_reserved_region@beb00000 {
> + no-map;
> + reg = <0x0 0xbeb00000 0x0 0x11500000>;
> + };
> +
> + tz_stat_mem: tz_stat_region@d0000000 {
> + no-map;
> + reg = <0x0 0xd0000000 0x0 0x100000>;
> + };
> +
> + tags_mem: tags_region@d0100000 {
> + no-map;
> + reg = <0x0 0xd0100000 0x0 0x1200000>;
> + };
> +
> + qtee_mem: qtee_region@d1300000 {
> + no-map;
> + reg = <0x0 0xd1300000 0x0 0x500000>;
> + };
> +
> + trusted_apps_mem: trusted_apps_region@d1800000 {
> + no-map;
> + reg = <0x0 0xd1800000 0x0 0x3900000>;
> + };
> +
> + dump_mem: mem_dump_region {
> + compatible = "shared-dma-pool";
> + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
> + reusable;
> + size = <0 0x3000000>;
> + };
> +
> + /* global autoconfigured region for contiguous allocations */
> + linux,cma {
> + compatible = "shared-dma-pool";
> + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
> + reusable;
> + alignment = <0x0 0x400000>;
> + size = <0x0 0x2000000>;
> + linux,cma-default;
> + };
Are you sure these last two are useful?

> + };
> +
> + psci {
Top-level nodes should be sorted alphabetically.

> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + firmware {
> + scm {
> + compatible = "qcom,scm";
This one should also have a SoC-specific compatible.

> + };
> + };
> +
> + qup_opp_table_100mhz: qup-100mhz-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
You probably want 36 or more bits of addressing here, otherwise
SMMU translation will be playing jokes on you, cutting off some
bits..

> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sa8775p";
Please update the compatible after you update it in the .c driver.

> + reg = <0x100000 0xc7018>;
The GCC size is usually something more rounded to 0x1000, can you
doublecheck?

> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>, /* TODO: usb_0_ssphy */
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + power-domains = <&rpmhpd SA8775P_CX>;

compatible
reg
clocks
#clock-cells
#reset-cells
power-domains
#power-domain-cells

please
> + };
> +
> + ipcc: mailbox@408000 {
> + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
> + reg = <0x408000 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #mbox-cells = <2>;
> + };
> +
> + aggre1_noc:interconnect-aggre1-noc {
> + compatible = "qcom,sa8775p-aggre1-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect-aggre2-noc {
> + compatible = "qcom,sa8775p-aggre2-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + clk_virt: interconnect-clk-virt {
> + compatible = "qcom,sa8775p-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + config_noc: interconnect-config-noc {
> + compatible = "qcom,sa8775p-config-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + dc_noc: interconnect-dc-noc {
> + compatible = "qcom,sa8775p-dc-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + gem_noc: interconnect-gem-noc {
> + compatible = "qcom,sa8775p-gem-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + gpdsp_anoc: interconnect-gpdsp-anoc {
> + compatible = "qcom,sa8775p-gpdsp-anoc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + lpass_ag_noc: interconnect-lpass-ag-noc {
> + compatible = "qcom,sa8775p-lpass-ag-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect-mc-virt {
> + compatible = "qcom,sa8775p-mc-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mmss_noc: interconnect-mmss-noc {
> + compatible = "qcom,sa8775p-mmss-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + nspa_noc: interconnect-nspa-noc {
> + compatible = "qcom,sa8775p-nspa-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + nspb_noc: interconnect-nspb-noc {
> + compatible = "qcom,sa8775p-nspb-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + pcie_anoc: interconnect-pcie-anoc {
> + compatible = "qcom,sa8775p-pcie-anoc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + system_noc: interconnect-system-noc {
> + compatible = "qcom,sa8775p-system-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x17a00000 0x10000>, /* GICD */
> + <0x17a60000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
compatible
reg
interrupts
interrupt-controller
#interrupt-cells
redistributor-stride
#redistributor-regions

#address-cells
#size-cells
ranges;

please
> + };
> +
> + apps_rsc: rsc@18200000 {
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x18200000 0x10000>,
> + <0x18210000 0x10000>,
> + <0x18220000 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Wrong indentation

> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 0>;
> + label = "apps_rsc";
Is it used anywhere?

> +
> + apps_bcm_voter: bcm_voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sa8775p-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board_clk>;
clocks
clock-names
#clock-cells
please

> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sa8775p-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
operating-points-v2
#power-domain-cells
please
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> + arch_timer: timer {
Unnecessary label

> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Shouldn't the last one be 10?

> + clock-frequency = <19200000>;
Please remove this property, the 100 levels of firmware that boot before
Linux already program this.

> + };
> +
> + memtimer: timer@17c20000 {
Unnecessary label

> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x17c20000 0x1000>;
> + clock-frequency = <19200000>;
Ditto

+ please sort to:
compatible
reg
#addr
#size
ranges
> +
> + frame@17c21000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c21000 0x1000>,
> + <0x17c22000 0x1000>;
reg
interrupts
frame-number
[status]

please
> + };
> +
> + frame@17c23000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c23000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c25000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c25000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c27000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c27000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c29000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c29000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2d000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x1f40000 0x20000>;
> + #hwlock-cells = <1>;
> + };
> +
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,sa8775p-pinctrl";
> + reg = <0xf000000 0x1000000>;
All address fields under /soc should be padded to 8 hex digits and
nodes should be sorted by their unit address.

> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 149>;
> + };
> +
> + qcom-wdt@17c10000 {
> + compatible = "qcom,kpss-wdt";
> + reg = <0x17c10000 0x1000>;
> + clocks = <&sleep_clk>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
Please reorder interrupts and clocks.

> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0xac0000 0x6000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x443 0x0>;
> + status = "disabled";
> +
> + uart10: serial@a8c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0xa8c000 0x4000>;
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + power-domains = <&rpmhpd SA8775P_CX>;
> + operating-points-v2 = <&qup_opp_table_100mhz>;
> + status = "disabled";
> + };
> + };
> +
> + apps_smmu: apps-smmu@15000000 {
> + compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
> + reg = <0x15000000 0x100000>, <0x15182000 0x28>;
Only one reg is used (unless you're nvidia)...

> + reg-names = "base", "tcu-base";
..and this becomes irrelevant.

> + #iommu-cells = <2>;

> + qcom,skip-init;
> + qcom,use-3-lvl-tables;
These two don't exist upstream.
> + #global-interrupts = <2>;

> + #size-cells = <1>;
> + #address-cells = <1>;
> + ranges;
There are no child nodes of SMMU, please remove.
> +
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
Bad indentation (or my mail client is drunk again)

Konrad
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};

2023-01-09 18:44:35

[permalink] [raw]

Subject: Re: [PATCH 18/18] arm64: dts: qcom: add initial support for qcom sa8775p-ride

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> This adds basic support for the Qualcomm sa8775p platform and the
> reference board: sa8775p-ride. The dt files describe the basics of the
> SoC and enable booting to shell.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 +
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 ++++++++++++++++++++++
> 3 files changed, 881 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..39b8206f7131 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> new file mode 100644
> index 000000000000..d4dae32a84cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +
> +/ {
> + model = "Qualcomm SA8875P Ride";
> + compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
> +
> + aliases {
> + serial0 = &uart10;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&uart10 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart10_state>;
> +};
> +
> +&tlmm {
> + qup_uart10_state: qup_uart10_state {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> + pins = "gpio46", "gpio47";
> + function = "qup1_se3";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> new file mode 100644
> index 000000000000..1a3b11628e38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -0,0 +1,841 @@
> +// SPDX-License-Identifier: GPL-2.0-only

Why GPL-2.0-only? Isn't this based on other code which is either
dual-licensed or BSD license?

> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sa8775p.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,sa8775p.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
> + xo_board_clk: xo-board-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;

Your board needs clock frequency.

> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;

Usual comment: this (entire clock or at least its frequency) is usually
not a property of a SoC, but board. Did something change here in SA8775?

> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;

Messed indentation.

> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-release-addr = <0x0 0x90000000>;
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_2>;
> + L2_2: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_3>;
> + L2_3: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@10000 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + next-level-cache = <&L2_4>;
> + L2_4: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + L3_1: l3-cache {
> + compatible = "cache";
> + };
> +
> + };
> + };
> +
> + CPU5: cpu@10100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_5>;
> + L2_5: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + CPU6: cpu@10200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_6>;
> + L2_6: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + CPU7: cpu@10300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x10300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_7>;
> + L2_7: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> +
> + core1 {
> + cpu = <&CPU5>;
> + };
> +
> + core2 {
> + cpu = <&CPU6>;
> + };
> +
> + core3 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> + };
> +
> + /* Will be updated by the bootloader. */
> + memory {
> + device_type = "memory";
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + sail_ss_mem: sail_ss_region@80000000 {

No underscores in node names.

(...)

> +
> + qup_opp_table_100mhz: qup-100mhz-opp-table {

opp-table-....

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sa8775p";
> + reg = <0x100000 0xc7018>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>, /* TODO: usb_0_ssphy */
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + power-domains = <&rpmhpd SA8775P_CX>;
> + };
> +
> + ipcc: mailbox@408000 {
> + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
> + reg = <0x408000 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #mbox-cells = <2>;
> + };
> +
> + aggre1_noc:interconnect-aggre1-noc {

Missing space after :

> + compatible = "qcom,sa8775p-aggre1-noc";

This does not match your bindings, so nothing here was tested against
your own files which you sent.

> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + aggre2_noc: interconnect-aggre2-noc {
> + compatible = "qcom,sa8775p-aggre2-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + clk_virt: interconnect-clk-virt {
> + compatible = "qcom,sa8775p-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + config_noc: interconnect-config-noc {
> + compatible = "qcom,sa8775p-config-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + dc_noc: interconnect-dc-noc {
> + compatible = "qcom,sa8775p-dc-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + gem_noc: interconnect-gem-noc {
> + compatible = "qcom,sa8775p-gem-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + gpdsp_anoc: interconnect-gpdsp-anoc {
> + compatible = "qcom,sa8775p-gpdsp-anoc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + lpass_ag_noc: interconnect-lpass-ag-noc {
> + compatible = "qcom,sa8775p-lpass-ag-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect-mc-virt {
> + compatible = "qcom,sa8775p-mc-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mmss_noc: interconnect-mmss-noc {
> + compatible = "qcom,sa8775p-mmss-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + nspa_noc: interconnect-nspa-noc {
> + compatible = "qcom,sa8775p-nspa-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + nspb_noc: interconnect-nspb-noc {
> + compatible = "qcom,sa8775p-nspb-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + pcie_anoc: interconnect-pcie-anoc {
> + compatible = "qcom,sa8775p-pcie-anoc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + system_noc: interconnect-system-noc {
> + compatible = "qcom,sa8775p-system-noc";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x17a00000 0x10000>, /* GICD */
> + <0x17a60000 0x100000>; /* GICR * 8 */

Compatible goes first, then reg, then ranges.

> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + apps_rsc: rsc@18200000 {
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x18200000 0x10000>,
> + <0x18210000 0x10000>,
> + <0x18220000 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 0>;
> + label = "apps_rsc";
> +
> + apps_bcm_voter: bcm_voter {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sa8775p-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board_clk>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sa8775p-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {

opp-0
(so numbering from 0 and hyphen)

> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {

opp-1

> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> + arch_timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };
> +
> + memtimer: timer@17c20000 {

Why this one is outside of soc node? Or are we inside soc? But then
ARMv8 timer cannot be here... dtbs W=1 would warn you, wouldn't it?

> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";

Weird order of properties.

> + reg = <0x17c20000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@17c21000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c21000 0x1000>,
> + <0x17c22000 0x1000>;
> + };
> +
> + frame@17c23000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c23000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c25000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c25000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c27000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c27000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c29000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c29000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2d000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x1f40000 0x20000>;
> + #hwlock-cells = <1>;
> + };
> +
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,sa8775p-pinctrl";
> + reg = <0xf000000 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 149>;
> + };
> +
> + qcom-wdt@17c10000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> + compatible = "qcom,kpss-wdt";
> + reg = <0x17c10000 0x1000>;
> + clocks = <&sleep_clk>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0xac0000 0x6000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x443 0x0>;
> + status = "disabled";
> +
> + uart10: serial@a8c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0xa8c000 0x4000>;
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + power-domains = <&rpmhpd SA8775P_CX>;
> + operating-points-v2 = <&qup_opp_table_100mhz>;
> + status = "disabled";
> + };
> + };
> +
> + apps_smmu: apps-smmu@15000000 {

iommu, node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

and probably also fails dtbs_check...

> + compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500";
> + reg = <0x15000000 0x100000>, <0x15182000 0x28>;
> + reg-names = "base", "tcu-base";
> + #iommu-cells = <2>;
> + qcom,skip-init;
> + qcom,use-3-lvl-tables;
> + #global-interrupts = <2>;
> + #size-cells = <1>;

Best regards,
Krzysztof

2023-01-09 18:49:58

[permalink] [raw]

Subject: Re: [PATCH 07/18] interconnect: qcom: add a driver for sa8775p

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Shazad Hussain <[email protected]>
>
> Introduce QTI SA8775P-specific interconnect driver.
>

> +
> +static struct qcom_icc_desc sa8775p_pcie_anoc = {
> + .nodes = pcie_anoc_nodes,
> + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
> + .bcms = pcie_anoc_bcms,
> + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
> +};
> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {
> + &bcm_sn0,
> + &bcm_sn1,
> + &bcm_sn3,
> + &bcm_sn4,
> + &bcm_sn9,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {
> + [MASTER_GIC_AHB] = &qhm_gic,
> + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
> + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
> + [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
> + [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
> + [MASTER_PIMEM] = &qxm_pimem,
> + [MASTER_GIC] = &xm_gic,
> + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
> + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
> + [SLAVE_SERVICE_SNOC] = &srvc_snoc,
> +};
> +
> +static struct qcom_icc_desc sa8775p_system_noc = {

This and several others are const, which means you started entire work
on some old code. It's quite a waste of your effort as now you have to
get all the patches we did for cleanups. Much better to start off from a
newest file. If you based work on downstream code, then this definitely
needs many fixes...

Best regards,
Krzysztof

2023-01-09 18:50:25

[permalink] [raw]

Subject: Re: [PATCH 11/18] arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P platforms

On 9.01.2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Enable the Qualcomm SA8775P TLMM pinctrl and GPIO driver. It needs to be
> built-in for UART to provide a console.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index d5c938adbd2d..6c752b9a4565 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -555,6 +555,7 @@ CONFIG_PINCTRL_QCM2290=y
> CONFIG_PINCTRL_QCS404=y
> CONFIG_PINCTRL_QDF2XXX=y
> CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
> +CONFIG_PINCTRL_SA8775P=y
> CONFIG_PINCTRL_SC7180=y
> CONFIG_PINCTRL_SC7280=y
> CONFIG_PINCTRL_SC8180X=y

2023-01-09 18:50:53

[permalink] [raw]

Subject: Re: [PATCH 01/18] dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p

On 09/01/2023 18:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add DT bindings for the GCC clock on SA8775P platforms. Add relevant
> DT include definitions as well.
>

Ah, and same comments as for all other patches:

Subject: drop second/last, redundant "bindings". The "dt-bindings"
prefix is already stating that these are bindings.

Best regards,
Krzysztof

2023-01-09 18:51:13

[permalink] [raw]

Subject: Re: [PATCH 13/18] dt-bindings: power: qcom,rpmpd: document sa8775p

On 09/01/2023 18:45, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add a compatible for sa8775p platforms and relevant defines to the include
> file.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2023-01-09 19:11:52

[permalink] [raw]

Subject: Re: [PATCH 01/18] dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p

On 09/01/2023 18:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add DT bindings for the GCC clock on SA8775P platforms. Add relevant
> DT include definitions as well.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> .../bindings/clock/qcom,gcc-sa8775p.yaml | 77 +++++

Use name style like SM8550.

> include/dt-bindings/clock/qcom,gcc-sa8775p.h | 320 ++++++++++++++++++
> 2 files changed, 397 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
> new file mode 100644
> index 000000000000..35d92d94495a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sa8775p.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on sa8775p
> +
> +maintainers:
> + - Bartosz Golaszewski <[email protected]>
> +
> +description: |
> + Qualcomm global clock control module provides the clocks, resets and
> + power domains on sa8775p.
> +
> + See also:: include/dt-bindings/clock/qcom,gcc-sa8775p.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-sa8775p

Here as well.

> +
> + clocks:
> + items:
> + - description: XO reference clock
> + - description: Sleep clock
> + - description: UFS memory first RX symbol clock
> + - description: UFS memory second RX symbol clock
> + - description: UFS memory first TX symbol clock
> + - description: UFS card first RX symbol clock
> + - description: UFS card second RX symbol clock
> + - description: UFS card first TX symbol clock
> + - description: Primary USB3 PHY wrapper pipe clock
> + - description: Secondary USB3 PHY wrapper pipe clock
> + - description: PCIe 0 pipe clock
> + - description: PCIe 1 pipe clock
> + - description: PCIe PHY clock
> + - description: First EMAC controller reference clock
> + - description: Second EMAC controller reference clock
> +
> + protected-clocks:
> + maxItems: 240
> +
> +required:
> + - compatible
> + - clocks
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sa8775p";
> + reg = <0x100000 0xc7018>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&usb_0_ssphy>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;

All these should be real in example.

> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gcc-sa8775p.h b/include/dt-bindings/clock/qcom,gcc-sa8775p.h
> new file mode 100644
> index 000000000000..badc253379c9
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sa8775p.h

Filename needs adjustments.

> @@ -0,0 +1,320 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

Dual license.

> +/*
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
Best regards,
Krzysztof

2023-01-09 20:33:46

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH 01/18] dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p

On Mon, 09 Jan 2023 18:44:54 +0100, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add DT bindings for the GCC clock on SA8775P platforms. Add relevant
> DT include definitions as well.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> .../bindings/clock/qcom,gcc-sa8775p.yaml | 77 +++++
> include/dt-bindings/clock/qcom,gcc-sa8775p.h | 320 ++++++++++++++++++
> 2 files changed, 397 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295, 0, 0, 0, 0, 0, 0, 0, 0], [4294967295, 0, 0, 0, 0]] is too short
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

2023-01-09 20:34:27

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 00/18] arm64: qcom: add support for sa8775p-ride

On 09/01/2023 19:44, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> This adds basic support for the Qualcomm sa8775p platform and its reference
> board: sa8775p-ride. The dtsi contains basic SoC description required for
> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
> sa8775p-ride board. There are three new drivers required to boot the board:
> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
> to existing code. More support is coming up.
>
> Bartosz Golaszewski (15):
> dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
> arm64: defconfig: enable the clock driver for Qualcomm SA8775P
> platforms
> dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
> clk: qcom: rpmh: add clocks for sa8775p
> dt-bindings: interconnect: qcom: document the interconnects for
> sa8775p
> arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
> dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
> arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
> platforms
> dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
> dt-bindings: power: qcom,rpmpd: document sa8775p
> soc: qcom: rmphpd: add power domains for sa8775p
> dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
> iommu: arm-smmu: qcom: add support for sa8775p
> dt-bindings: arm: qcom: document the sa8775p reference board
> arm64: dts: qcom: add initial support for qcom sa8775p-ride
>
> Shazad Hussain (2):
> clk: qcom: add the GCC driver for sa8775p

This patch didn't make it to the list. Please check if you can fix or
split it somehow?

--
With best wishes
Dmitry

2023-01-09 21:32:31

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 00/18] arm64: qcom: add support for sa8775p-ride

On 09/01/2023 22:59, Konrad Dybcio wrote:
>
>
> On 9.01.2023 21:13, Dmitry Baryshkov wrote:
>> On 09/01/2023 19:44, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <[email protected]>
>>>
>>> This adds basic support for the Qualcomm sa8775p platform and its reference
>>> board: sa8775p-ride. The dtsi contains basic SoC description required for
>>> a simple boot-to-shell. The dts enables boot-to-shell with UART on the
>>> sa8775p-ride board. There are three new drivers required to boot the board:
>>> pinctrl, interconnect and GCC clock. Other patches contain various tweaks
>>> to existing code. More support is coming up.
>>>
>>> Bartosz Golaszewski (15):
>>>    dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p
>>>    arm64: defconfig: enable the clock driver for Qualcomm SA8775P
>>>      platforms
>>>    dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p
>>>    clk: qcom: rpmh: add clocks for sa8775p
>>>    dt-bindings: interconnect: qcom: document the interconnects for
>>>      sa8775p
>>>    arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P
>>>    dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm
>>>    arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P
>>>      platforms
>>>    dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
>>>    dt-bindings: power: qcom,rpmpd: document sa8775p
>>>    soc: qcom: rmphpd: add power domains for sa8775p
>>>    dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P
>>>    iommu: arm-smmu: qcom: add support for sa8775p
>>>    dt-bindings: arm: qcom: document the sa8775p reference board
>>>    arm64: dts: qcom: add initial support for qcom sa8775p-ride
>>>
>>> Shazad Hussain (2):
>>>    clk: qcom: add the GCC driver for sa8775p
>>
>> This patch didn't make it to the list. Please check if you can fix or split it somehow?
> It's a known issue with lists clipping messages that are too long.
> I'll forward it to you.

Thank you!

--
With best wishes
Dmitry

2023-01-09 22:08:55