changes v2:
- remove "ARM: imx6q: use of_clk_get_by_name() instead of_clk_get() to
get ptp clock" patch
- fix build warnings
- add "Acked-by: Lee Jones <[email protected]>"
- reword some commits as suggested by Fabio
Most of i.MX SoC variants have configurable FEC/Ethernet reference clock
used by RMII specification. This functionality is located in the
general purpose registers (GRPx) and till now was not implemented as
part of SoC clock tree.
With this patch set, we move forward and add this missing functionality
to some of i.MX clk drivers. So, we will be able to configure clock topology
by using devicetree and be able to troubleshoot clock dependencies
by using clk_summary etc.
Currently implemented and tested i.MX6Q, i.MX6DL and i.MX6UL variants.
Oleksij Rempel (19):
clk: imx: add clk-gpr-mux driver
clk: imx6q: add ethernet refclock mux support
ARM: imx6q: skip ethernet refclock reconfiguration if enet_clk_ref is
present
ARM: dts: imx6qdl: use enet_clk_ref instead of enet_out for the FEC
node
ARM: dts: imx6dl-lanmcu: configure ethernet reference clock parent
ARM: dts: imx6dl-alti6p: configure ethernet reference clock parent
ARM: dts: imx6dl-plybas: configure ethernet reference clock parent
ARM: dts: imx6dl-plym2m: configure ethernet reference clock parent
ARM: dts: imx6dl-prtmvt: configure ethernet reference clock parent
ARM: dts: imx6dl-victgo: configure ethernet reference clock parent
ARM: dts: imx6q-prtwd2: configure ethernet reference clock parent
ARM: dts: imx6qdl-skov-cpu: configure ethernet reference clock parent
ARM: dts: imx6dl-eckelmann-ci4x10: configure ethernet reference clock
parent
clk: imx: add imx_obtain_fixed_of_clock()
clk: imx6ul: fix enet1 gate configuration
clk: imx6ul: add ethernet refclock mux support
ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL
ARM: mach-imx: imx6ul: remove not optional ethernet refclock overwrite
ARM: dts: imx6ul-prti6g: configure ethernet reference clock parent
arch/arm/boot/dts/imx6dl-alti6p.dts | 12 +-
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 13 +-
arch/arm/boot/dts/imx6dl-lanmcu.dts | 12 +-
arch/arm/boot/dts/imx6dl-plybas.dts | 12 +-
arch/arm/boot/dts/imx6dl-plym2m.dts | 12 +-
arch/arm/boot/dts/imx6dl-prtmvt.dts | 11 +-
arch/arm/boot/dts/imx6dl-victgo.dts | 12 +-
arch/arm/boot/dts/imx6q-prtwd2.dts | 17 ++-
arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi | 12 +-
arch/arm/boot/dts/imx6qdl.dtsi | 4 +-
arch/arm/boot/dts/imx6ul-prti6g.dts | 14 ++-
arch/arm/boot/dts/imx6ul.dtsi | 10 +-
arch/arm/mach-imx/mach-imx6q.c | 10 +-
arch/arm/mach-imx/mach-imx6ul.c | 20 ---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-gpr-mux.c | 119 ++++++++++++++++++
drivers/clk/imx/clk-imx6q.c | 13 ++
drivers/clk/imx/clk-imx6ul.c | 33 ++++-
drivers/clk/imx/clk.c | 14 +++
drivers/clk/imx/clk.h | 8 ++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +-
include/dt-bindings/clock/imx6ul-clock.h | 7 +-
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +-
23 files changed, 296 insertions(+), 80 deletions(-)
create mode 100644 drivers/clk/imx/clk-gpr-mux.c
--
2.30.2
IMX6UL_CLK_ENETx_REF is behind of CLK_ENETx_REF_SEL:
FEC MAC <---------- CLK_ENETx_REF_SEL <--------- CLK_ENETx_REF
\
^------<-> CLK_ENETx_REF_PAD
We should point to the clock selector instead. So, we will be able to
use external clock source from CLK_ENETx_REF_PAD as well.
At same time, remove enet_out clk. It is using always the same clock as
enet_clk_ref and do not help to solve any challenges of this HW.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6ul.dtsi | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2b5996395701..fa9afedb6549 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -532,10 +532,9 @@ fec2: ethernet@20b4000 {
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
- <&clks IMX6UL_CLK_ENET2_REF_125M>,
- <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ <&clks IMX6UL_CLK_ENET2_REF_SEL>;
clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
+ "enet_clk_ref";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
@@ -880,10 +879,9 @@ fec1: ethernet@2188000 {
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
- <&clks IMX6UL_CLK_ENET_REF>,
- <&clks IMX6UL_CLK_ENET_REF>;
+ <&clks IMX6UL_CLK_ENET1_REF_SEL>;
clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
+ "enet_clk_ref";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
--
2.30.2
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6dl-prtmvt.dts | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts
index 1f8cddd83ccb..5f4fa796ca18 100644
--- a/arch/arm/boot/dts/imx6dl-prtmvt.dts
+++ b/arch/arm/boot/dts/imx6dl-prtmvt.dts
@@ -193,6 +193,7 @@ clk50m_phy: phy-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_1v8: regulator-1v8 {
@@ -293,8 +294,10 @@ &can2 {
};
&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
};
&ecspi1 {
@@ -314,10 +317,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rmii_phy>;
status = "okay";
--
2.30.2
Add ethernet refclock mux support and set it to internal clock by
default. This configuration will not affect existing boards since
machine code currently overwrites this default.
The machine code will be fixed in a separate patch.
Signed-off-by: Oleksij Rempel <[email protected]>
---
drivers/clk/imx/clk-imx6q.c | 13 +++++++++++++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index de36f58d551c..22b464ca22c8 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -12,6 +12,7 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -115,6 +116,10 @@ static struct clk_div_table video_div_table[] = {
{ /* sentinel */ }
};
+static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", };
+static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD };
+static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
+
static unsigned int share_count_esai;
static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
@@ -908,6 +913,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
+ hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0);
+
+ hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr",
+ IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels),
+ enet_ref_sels_table, enet_ref_sels_table_mask);
+
imx_check_clk_hws(hws, IMX6QDL_CLK_END);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
@@ -974,6 +985,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
}
+ clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk);
+
imx_register_uart_clocks(2);
}
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index e20c43cc36f6..e5b2a1ba02bc 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -273,6 +273,8 @@
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_DCIC1 264
#define IMX6QDL_CLK_DCIC2 265
-#define IMX6QDL_CLK_END 266
+#define IMX6QDL_CLK_ENET_REF_SEL 266
+#define IMX6QDL_CLK_ENET_REF_PAD 267
+#define IMX6QDL_CLK_END 268
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.30.2
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
index 3def1b621c8e..2731faede1cb 100644
--- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
@@ -105,6 +105,7 @@ clk50m_phy: phy-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_3v3: regulator-3v3 {
@@ -232,13 +233,16 @@ adc: adc@0 {
};
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-mode = "rmii";
phy-supply = <®_3v3>;
status = "okay";
--
2.30.2
According to the "i.MX 6UltraLite Applications Processor Reference Manual,
Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
of PLL6. It is controlling ENET1 separately.
So, instead of this picture (implementation before this patch):
fec1 <- enet_ref (divider) <---------------------------,
|- pll6_enet (gate)
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
we should have this one (after this patch):
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
|- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
With this fix, the RMII reference clock will be turned off, after
setting network interface down on each separate interface
(ip l s dev eth0 down). Which was not working before, on system with both
FECs enabled.
Signed-off-by: Oleksij Rempel <[email protected]>
---
drivers/clk/imx/clk-imx6ul.c | 7 ++++---
include/dt-bindings/clock/imx6ul-clock.h | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 67a7a77ca540..c3c465c1b0e7 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
- hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
+ hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1);
hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
/*
@@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
- hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+ hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0,
base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
- hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
+ hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13);
+ hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 79094338e6f1..b44920f1edb0 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -256,7 +256,8 @@
#define IMX6UL_CLK_GPIO4 247
#define IMX6UL_CLK_GPIO5 248
#define IMX6UL_CLK_MMDC_P1_IPG 249
+#define IMX6UL_CLK_ENET1_REF_125M 250
-#define IMX6UL_CLK_END 250
+#define IMX6UL_CLK_END 251
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
--
2.30.2
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6dl-alti6p.dts | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts
index e8325fd680d9..e6a4e2770640 100644
--- a/arch/arm/boot/dts/imx6dl-alti6p.dts
+++ b/arch/arm/boot/dts/imx6dl-alti6p.dts
@@ -22,6 +22,7 @@ clock_ksz8081: clock-ksz8081 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
i2c2-mux {
@@ -191,6 +192,13 @@ &can1 {
status = "okay";
};
+&clks {
+ clocks = <&clock_ksz8081>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clock_ksz8081>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -208,10 +216,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clock_ksz8081>;
- clock-names = "ipg", "ahb", "ptp";
status = "okay";
mdio {
--
2.30.2
On 23-01-17 07:14:49, Oleksij Rempel wrote:
> According to the "i.MX 6UltraLite Applications Processor Reference Manual,
> Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
> of PLL6. It is controlling ENET1 separately.
>
> So, instead of this picture (implementation before this patch):
> fec1 <- enet_ref (divider) <---------------------------,
> |- pll6_enet (gate)
> fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-?
>
> we should have this one (after this patch):
> fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
> |- pll6_enet
> fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-?
>
> With this fix, the RMII reference clock will be turned off, after
> setting network interface down on each separate interface
> (ip l s dev eth0 down). Which was not working before, on system with both
> FECs enabled.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
I'm OK with this. Maybe a fixes tag ?
Reviewed-by: Abel Vesa <[email protected]>
> ---
> drivers/clk/imx/clk-imx6ul.c | 7 ++++---
> include/dt-bindings/clock/imx6ul-clock.h | 3 ++-
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index 67a7a77ca540..c3c465c1b0e7 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -176,7 +176,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
> hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
> hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
> - hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
> + hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor("pll6_enet", "pll6_bypass", 1, 1);
> hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
>
> /*
> @@ -205,12 +205,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
> hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
>
> - hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
> + hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0,
> base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
> hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
> base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
>
> - hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
> + hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m", "enet1_ref", base + 0xe0, 13);
> + hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
> hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
> hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
>
> diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
> index 79094338e6f1..b44920f1edb0 100644
> --- a/include/dt-bindings/clock/imx6ul-clock.h
> +++ b/include/dt-bindings/clock/imx6ul-clock.h
> @@ -256,7 +256,8 @@
> #define IMX6UL_CLK_GPIO4 247
> #define IMX6UL_CLK_GPIO5 248
> #define IMX6UL_CLK_MMDC_P1_IPG 249
> +#define IMX6UL_CLK_ENET1_REF_125M 250
>
> -#define IMX6UL_CLK_END 250
> +#define IMX6UL_CLK_END 251
>
> #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
> --
> 2.30.2
>
On 23-01-17 07:14:36, Oleksij Rempel wrote:
> Add ethernet refclock mux support and set it to internal clock by
> default. This configuration will not affect existing boards since
> machine code currently overwrites this default.
>
> The machine code will be fixed in a separate patch.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
> ---
> drivers/clk/imx/clk-imx6q.c | 13 +++++++++++++
> include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index de36f58d551c..22b464ca22c8 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -12,6 +12,7 @@
> #include <linux/clk-provider.h>
> #include <linux/err.h>
> #include <linux/io.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <linux/of_irq.h>
> @@ -115,6 +116,10 @@ static struct clk_div_table video_div_table[] = {
> { /* sentinel */ }
> };
>
> +static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", };
> +static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD };
> +static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
> +
> static unsigned int share_count_esai;
> static unsigned int share_count_asrc;
> static unsigned int share_count_ssi1;
> @@ -908,6 +913,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
> hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
>
> + hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0);
> +
> + hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr",
> + IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels),
> + enet_ref_sels_table, enet_ref_sels_table_mask);
> +
> imx_check_clk_hws(hws, IMX6QDL_CLK_END);
>
> of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> @@ -974,6 +985,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
> }
>
> + clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk);
> +
> imx_register_uart_clocks(2);
> }
> CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
> diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> index e20c43cc36f6..e5b2a1ba02bc 100644
> --- a/include/dt-bindings/clock/imx6qdl-clock.h
> +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> @@ -273,6 +273,8 @@
> #define IMX6QDL_CLK_MMDC_P0_IPG 263
> #define IMX6QDL_CLK_DCIC1 264
> #define IMX6QDL_CLK_DCIC2 265
> -#define IMX6QDL_CLK_END 266
> +#define IMX6QDL_CLK_ENET_REF_SEL 266
> +#define IMX6QDL_CLK_ENET_REF_PAD 267
> +#define IMX6QDL_CLK_END 268
>
> #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
> --
> 2.30.2
>
On Sun, Jan 29, 2023 at 07:32:31PM +0200, Abel Vesa wrote:
> On 23-01-17 07:14:49, Oleksij Rempel wrote:
> > According to the "i.MX 6UltraLite Applications Processor Reference Manual,
> > Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
> > of PLL6. It is controlling ENET1 separately.
> >
> > So, instead of this picture (implementation before this patch):
> > fec1 <- enet_ref (divider) <---------------------------,
> > |- pll6_enet (gate)
> > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
> >
> > we should have this one (after this patch):
> > fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
> > |- pll6_enet
> > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
> >
> > With this fix, the RMII reference clock will be turned off, after
> > setting network interface down on each separate interface
> > (ip l s dev eth0 down). Which was not working before, on system with both
> > FECs enabled.
> >
> > Signed-off-by: Oleksij Rempel <[email protected]>
>
> I'm OK with this. Maybe a fixes tag ?
Hm. Initial commit was:
Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support")
but this patch will not apply on top of it.
Next possible commit would be:
Fixes: 1487b60dc2d2 ("clk: imx6ul: Switch to clk_hw based API")
But this patch didn't introduce this issue, it was just refactoring.
What do you prefer?
Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 23-01-30 13:15:30, Oleksij Rempel wrote:
> On Sun, Jan 29, 2023 at 07:32:31PM +0200, Abel Vesa wrote:
> > On 23-01-17 07:14:49, Oleksij Rempel wrote:
> > > According to the "i.MX 6UltraLite Applications Processor Reference Manual,
> > > Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
> > > of PLL6. It is controlling ENET1 separately.
> > >
> > > So, instead of this picture (implementation before this patch):
> > > fec1 <- enet_ref (divider) <---------------------------,
> > > |- pll6_enet (gate)
> > > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-?
> > >
> > > we should have this one (after this patch):
> > > fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
> > > |- pll6_enet
> > > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-?
> > >
> > > With this fix, the RMII reference clock will be turned off, after
> > > setting network interface down on each separate interface
> > > (ip l s dev eth0 down). Which was not working before, on system with both
> > > FECs enabled.
> > >
> > > Signed-off-by: Oleksij Rempel <[email protected]>
> >
> > I'm OK with this. Maybe a fixes tag ?
>
> Hm. Initial commit was:
> Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support")
> but this patch will not apply on top of it.
> Next possible commit would be:
> Fixes: 1487b60dc2d2 ("clk: imx6ul: Switch to clk_hw based API")
> But this patch didn't introduce this issue, it was just refactoring.
Hm, in that case I don't think is qoing to be backported ever.
>
> What do you prefer?
I'll apply it as it is.
Thanks.
>
> Regards,
> Oleksij
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 23-01-17 07:14:34, Oleksij Rempel wrote:
> changes v2:
> - remove "ARM: imx6q: use of_clk_get_by_name() instead of_clk_get() to
> get ptp clock" patch
> - fix build warnings
> - add "Acked-by: Lee Jones <[email protected]>"
> - reword some commits as suggested by Fabio
Unfortunatley it doesn't apply on my tree. Can you please rebase and resend?
Thanks.
>
> Most of i.MX SoC variants have configurable FEC/Ethernet reference clock
> used by RMII specification. This functionality is located in the
> general purpose registers (GRPx) and till now was not implemented as
> part of SoC clock tree.
>
> With this patch set, we move forward and add this missing functionality
> to some of i.MX clk drivers. So, we will be able to configure clock topology
> by using devicetree and be able to troubleshoot clock dependencies
> by using clk_summary etc.
>
> Currently implemented and tested i.MX6Q, i.MX6DL and i.MX6UL variants.
>
> Oleksij Rempel (19):
> clk: imx: add clk-gpr-mux driver
> clk: imx6q: add ethernet refclock mux support
> ARM: imx6q: skip ethernet refclock reconfiguration if enet_clk_ref is
> present
> ARM: dts: imx6qdl: use enet_clk_ref instead of enet_out for the FEC
> node
> ARM: dts: imx6dl-lanmcu: configure ethernet reference clock parent
> ARM: dts: imx6dl-alti6p: configure ethernet reference clock parent
> ARM: dts: imx6dl-plybas: configure ethernet reference clock parent
> ARM: dts: imx6dl-plym2m: configure ethernet reference clock parent
> ARM: dts: imx6dl-prtmvt: configure ethernet reference clock parent
> ARM: dts: imx6dl-victgo: configure ethernet reference clock parent
> ARM: dts: imx6q-prtwd2: configure ethernet reference clock parent
> ARM: dts: imx6qdl-skov-cpu: configure ethernet reference clock parent
> ARM: dts: imx6dl-eckelmann-ci4x10: configure ethernet reference clock
> parent
> clk: imx: add imx_obtain_fixed_of_clock()
> clk: imx6ul: fix enet1 gate configuration
> clk: imx6ul: add ethernet refclock mux support
> ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL
> ARM: mach-imx: imx6ul: remove not optional ethernet refclock overwrite
> ARM: dts: imx6ul-prti6g: configure ethernet reference clock parent
>
> arch/arm/boot/dts/imx6dl-alti6p.dts | 12 +-
> arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 13 +-
> arch/arm/boot/dts/imx6dl-lanmcu.dts | 12 +-
> arch/arm/boot/dts/imx6dl-plybas.dts | 12 +-
> arch/arm/boot/dts/imx6dl-plym2m.dts | 12 +-
> arch/arm/boot/dts/imx6dl-prtmvt.dts | 11 +-
> arch/arm/boot/dts/imx6dl-victgo.dts | 12 +-
> arch/arm/boot/dts/imx6q-prtwd2.dts | 17 ++-
> arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi | 12 +-
> arch/arm/boot/dts/imx6qdl.dtsi | 4 +-
> arch/arm/boot/dts/imx6ul-prti6g.dts | 14 ++-
> arch/arm/boot/dts/imx6ul.dtsi | 10 +-
> arch/arm/mach-imx/mach-imx6q.c | 10 +-
> arch/arm/mach-imx/mach-imx6ul.c | 20 ---
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-gpr-mux.c | 119 ++++++++++++++++++
> drivers/clk/imx/clk-imx6q.c | 13 ++
> drivers/clk/imx/clk-imx6ul.c | 33 ++++-
> drivers/clk/imx/clk.c | 14 +++
> drivers/clk/imx/clk.h | 8 ++
> include/dt-bindings/clock/imx6qdl-clock.h | 4 +-
> include/dt-bindings/clock/imx6ul-clock.h | 7 +-
> include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +-
> 23 files changed, 296 insertions(+), 80 deletions(-)
> create mode 100644 drivers/clk/imx/clk-gpr-mux.c
>
> --
> 2.30.2
>