This commits are based on the Fabien Parent <[email protected]> work.
The purpose of this series is to add the following HWs / IPs support for
the mt8365-evk board:
- Watchdog
- Power Management Integrated Circuit "PMIC" wrapper
- MT6357 PMIC
- MultiMediaCard "MMC" & Secure Digital "SD" controller
- USB controller
- Ethernet MAC controller
Add CPU Freq & IDLE support for this board.
This series depends to another one which add support for MT8365 SoC and
EVK board [1].
Regards,
Alex
[1]: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Changes in v3:
- Add trailers and simply resend.
- Link to v2: https://lore.kernel.org/r/[email protected]
---
Alexandre Bailon (1):
arm64: dts: mediatek: Increase the size BL31 reserved memory
Alexandre Mergnat (12):
dt-bindings: watchdog: mediatek,mtk-wdt: add mt8365
dt-bindings: pinctrl: mediatek,mt8365-pinctrl: add drive strength property
arm64: dts: mediatek: add watchdog support for mt8365 SoC
arm64: dts: mediatek: add pwrap support to mt8365 SoC
arm64: dts: mediatek: add mt6357 PMIC support for mt8365-evk
arm64: dts: mediatek: add mmc support for mt8365 SoC
arm64: dts: mediatek: add mmc support for mt8365-evk
arm64: dts: mediatek: add usb controller support for mt8365-evk
arm64: dts: mediatek: add ethernet support for mt8365 SoC
arm64: dts: mediatek: add ethernet support for mt8365-evk
arm64: dts: mediatek: add OPP support for mt8365 SoC
arm64: dts: mediatek: add cpufreq support for mt8365-evk
Amjad Ouled-Ameur (2):
arm64: dts: mediatek: fix systimer properties
arm64: dts: mediatek: Add CPU Idle support
Fabien Parent (2):
arm64: dts: mediatek: add mt6357 device-tree
arm64: dts: mediatek: set vmc regulator as always on
.../bindings/pinctrl/mediatek,mt8365-pinctrl.yaml | 3 +
.../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt6357.dtsi | 282 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 254 ++++++++++++++++++-
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 196 +++++++++++++-
5 files changed, 731 insertions(+), 5 deletions(-)
---
base-commit: 555b3a55823ec063129de4403899203febb58788
change-id: 20230203-evk-board-support-d5b7a839ed7b
Best regards,
--
Alexandre Mergnat <[email protected]>
In order to use the PMIC, the pwrap support should be added
to allow communication between the SoC and the PMIC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index e018df6844f6..687011353f69 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -186,6 +186,18 @@ apmixedsys: syscon@1000c000 {
#clock-cells = <1>;
};
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
keypad: keypad@10010000 {
compatible = "mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
--
2.25.1
Add binding description for mediatek,mt8365-wdt
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
index 55b34461df1b..66cacea8e47f 100644
--- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
@@ -38,6 +38,7 @@ properties:
- mediatek,mt7623-wdt
- mediatek,mt7629-wdt
- mediatek,mt8173-wdt
+ - mediatek,mt8365-wdt
- mediatek,mt8516-wdt
- const: mediatek,mt6589-wdt
--
2.25.1
- Add EMMC support on mmc0 (internal memory)
- Add SD-UHS support on mmc1 (external memory)
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 2f88562c638a..b5d018686cbe 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -97,6 +97,42 @@ &i2c0 {
#size-cells = <0>;
};
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12012>;
+ vmmc-supply = <&mt6357_vemc_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&mt6357_vmch_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ status = "okay";
+};
+
&mt6357_pmic {
interrupt-parent = <&pio>;
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
@@ -123,6 +159,108 @@ pins {
};
};
+ mmc0_default_pins: mmc0-default-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ ds-pins {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ cd-pins {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
uart0_pins: uart0-pins {
pins {
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
--
2.25.1
There are three ports of MSDC (MMC and SD Controller), which are:
- MSDC0: EMMC5.1
- MSDC1: SD3.0/SDIO3.0
- MSDC2: SDIO3.0+
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 687011353f69..a67eeca28da5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -399,6 +399,45 @@ usb_host: usb@11200000 {
};
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11c60000 0 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
+ <&infracfg CLK_IFR_MSDC2_HCLK>,
+ <&infracfg CLK_IFR_MSDC2_SRC>,
+ <&infracfg CLK_IFR_MSDC2_BK>,
+ <&infracfg CLK_IFR_AP_MSDC0>;
+ clock-names = "source", "hclk", "source_cg",
+ "bus_clk", "sys_cg";
+ status = "disabled";
+ };
+
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
--
2.25.1
This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards.
It supports power management with Energy Efficient Ethernet and Wake-on-LAN
specification. Flow control is provided for half-duplex and full-duplex
mode. For packet transmission and reception, the controller supports
IPv4/UDP/TCP checksum offload and VLAN tag insertion.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index a67eeca28da5..394a5a61be59 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -438,6 +438,18 @@ mmc2: mmc@11250000 {
status = "disabled";
};
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
--
2.25.1
From: Amjad Ouled-Ameur <[email protected]>
MT8365 has a SYST timer (System Timer), therefore the compatible node
should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer"
(which corresponds to ARM/ARM64 System Timer).
Plus, register range should be 0x100 instead of 0x10.
Finally, interrupt polarity of systimer is LEVEL_HIGH.
Fix the above properties accordingly.
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index c3ea3cc97a47..959d8533c24c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -575,9 +575,9 @@ system_clk: dummy13m {
};
systimer: timer@10017000 {
- compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer";
- reg = <0 0x10017000 0 0x10>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+ compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x100>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clock-names = "clk13m";
};
--
2.25.1
From: Amjad Ouled-Ameur <[email protected]>
MT8365 has 3 CPU Idle states:
- MCDI_CPU. (Multi-Core-Deep-Idle)
- MCDI_CLUSTER.
- DPIDLE. (Deep-Idle)
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 35 ++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 959d8533c24c..b5f5c77f7f84 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -112,6 +112,7 @@ cpu0: cpu@0 {
reg = <0x0>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -131,6 +132,7 @@ cpu1: cpu@1 {
reg = <0x1>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -150,6 +152,7 @@ cpu2: cpu@2 {
reg = <0x2>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -169,6 +172,7 @@ cpu3: cpu@3 {
reg = <0x3>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -182,6 +186,37 @@ cpu3: cpu@3 {
operating-points-v2 = <&cluster0_opp>;
};
+ idle-states {
+ entry-method = "psci";
+
+ CPU_MCDI: cpu-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010001>;
+ entry-latency-us = <300>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_MCDI: cluster-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010001>;
+ entry-latency-us = <350>;
+ exit-latency-us = <250>;
+ min-residency-us = <1200>;
+ };
+
+ CLUSTER_DPIDLE: cluster-dpidle {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010004>;
+ entry-latency-us = <300>;
+ exit-latency-us = <800>;
+ min-residency-us = <3300>;
+ };
+ };
+
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
--
2.25.1
In order to have cpufreq support, this patch adds proc-supply and sram-supply
for each CPU.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 1820daad6da3..edf3a4b6a76e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -88,6 +88,26 @@ optee_reserved: optee@43200000 {
};
};
+&cpu0 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
ðernet {
pinctrl-names = "default";
pinctrl-0 = <ðernet_pins>;
--
2.25.1
- Enable "vibr" and "vsim2" regulators to power the ethernet chip.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 57 +++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 868ee0d160e4..1820daad6da3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -88,6 +88,28 @@ optee_reserved: optee@43200000 {
};
};
+ðernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_pins>;
+ phy-handle = <ð_phy>;
+ phy-mode = "rmii";
+ /*
+ * Ethernet and HDMI (DSI0) are sharing pins.
+ * Only one can be enabled at a time and require the physical switch
+ * SW2101 to be set on LAN position
+ */
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -140,12 +162,47 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+/* Needed by analog switch (multiplexer), HDMI and ethernet */
+&mt6357_vibr_reg {
+ regulator-always-on;
+};
+
/* Needed by MSDC1 */
&mt6357_vmc_reg {
regulator-always-on;
};
+/* Needed by ethernet */
+&mt6357_vsim2_reg {
+ regulator-always-on;
+};
+
&pio {
+ ethernet_pins: ethernet-pins {
+ phy_reset_pins {
+ pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
+ };
+
+ rmii_pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
+ <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
+ <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
+ <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
+ <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
+ <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
+ <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
+ <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
+ <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
+ <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
+ <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
+ <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
+ <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
+ <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
+ <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
+ <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
+ };
+ };
+
gpio_keys: gpio-keys-pins {
pins {
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
--
2.25.1
In order to have cpufreq support, this patch adds generic Operating
Performance Points support.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 85 ++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 394a5a61be59..c3ea3cc97a47 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -20,6 +20,75 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <650000>;
+ };
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-microvolt = <668750>;
+ };
+ opp-987000000 {
+ opp-hz = /bits/ 64 <987000000>;
+ opp-microvolt = <687500>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <706250>;
+ };
+ opp-1125000000 {
+ opp-hz = /bits/ 64 <1125000000>;
+ opp-microvolt = <725000>;
+ };
+ opp-1216000000 {
+ opp-hz = /bits/ 64 <1216000000>;
+ opp-microvolt = <750000>;
+ };
+ opp-1308000000 {
+ opp-hz = /bits/ 64 <1308000000>;
+ opp-microvolt = <775000>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1466000000 {
+ opp-hz = /bits/ 64 <1466000000>;
+ opp-microvolt = <825000>;
+ };
+ opp-1533000000 {
+ opp-hz = /bits/ 64 <1533000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1633000000 {
+ opp-hz = /bits/ 64 <1633000000>;
+ opp-microvolt = <887500>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <912500>;
+ };
+ opp-1767000000 {
+ opp-hz = /bits/ 64 <1767000000>;
+ opp-microvolt = <937500>;
+ };
+ opp-1834000000 {
+ opp-hz = /bits/ 64 <1834000000>;
+ opp-microvolt = <962500>;
+ };
+ opp-1917000000 {
+ opp-hz = /bits/ 64 <1917000000>;
+ opp-microvolt = <993750>;
+ };
+ opp-2001000000 {
+ opp-hz = /bits/ 64 <2001000000>;
+ opp-microvolt = <1025000>;
+ };
+ };
+
cpu-map {
cluster0 {
core0 {
@@ -50,6 +119,10 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
@@ -65,6 +138,10 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
@@ -80,6 +157,10 @@ cpu2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
@@ -95,6 +176,10 @@ cpu3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
l2: l2-cache {
--
2.25.1
This power management system chip integration helps to manage regulators
and keys.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index fc7f6d8ae173..2f88562c638a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
#include "mt8365.dtsi"
+#include "mt6357.dtsi"
/ {
model = "MediaTek MT8365 Open Platform EVK";
@@ -96,6 +97,13 @@ &i2c0 {
#size-cells = <0>;
};
+&mt6357_pmic {
+ interrupt-parent = <&pio>;
+ interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
&pio {
gpio_keys: gpio-keys-pins {
pins {
--
2.25.1
From: Fabien Parent <[email protected]>
MSDC1 IP block is powered by VMC. Make sure it is always on.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index b5d018686cbe..22ec332fe9c9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -140,6 +140,11 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+/* Needed by MSDC1 */
+&mt6357_vmc_reg {
+ regulator-always-on;
+};
+
&pio {
gpio_keys: gpio-keys-pins {
pins {
--
2.25.1
This patch add support for SuperSpeed USB, in OTG mode, on micro connector.
It also add support for the Extensible Host Controller Interface USB.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 22ec332fe9c9..868ee0d160e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -319,6 +319,28 @@ &pwm {
status = "okay";
};
+&ssusb {
+ pinctrl-0 = <&usb_pins>;
+ pinctrl-names = "default";
+ maximum-speed = "high-speed";
+ usb-role-switch;
+ dr_mode = "otg";
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb_otg_vbus>;
+ };
+};
+
+&usb_host {
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
--
2.25.1
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> Add binding description for mediatek,mt8365-wdt
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> In order to use the PMIC, the pwrap support should be added
> to allow communication between the SoC and the PMIC.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index e018df6844f6..687011353f69 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -186,6 +186,18 @@ apmixedsys: syscon@1000c000 {
> #clock-cells = <1>;
> };
>
> + pwrap: pwrap@1000d000 {
> + compatible = "mediatek,mt8365-pwrap";
> + reg = <0 0x1000d000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
> + <&infracfg CLK_IFR_PMIC_AP>,
> + <&infracfg CLK_IFR_PWRAP_SYS>,
> + <&infracfg CLK_IFR_PWRAP_TMR>;
I would prefer:
clocks = <&infracfg CLK_IFR_PWRAP_SPI>, <&infracfg CLK_IFR_PMIC_AP>,
<&infracfg CLK_IFR_PWRAP_SYS>, <&infracfg CLK_IFR_PWRAP_TMR>;
....but I'll leave this choice to you, as I don't have really strong opinions on
this one, so, with or without the proposed change, you still get my:
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> This power management system chip integration helps to manage regulators
> and keys.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index fc7f6d8ae173..2f88562c638a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -12,6 +12,7 @@
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> #include "mt8365.dtsi"
> +#include "mt6357.dtsi"
>
> / {
> model = "MediaTek MT8365 Open Platform EVK";
> @@ -96,6 +97,13 @@ &i2c0 {
> #size-cells = <0>;
> };
>
> +&mt6357_pmic {
> + interrupt-parent = <&pio>;
> + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
Please... use:
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
Cheers,
Angelo
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> There are three ports of MSDC (MMC and SD Controller), which are:
> - MSDC0: EMMC5.1
> - MSDC1: SD3.0/SDIO3.0
> - MSDC2: SDIO3.0+
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index 687011353f69..a67eeca28da5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -399,6 +399,45 @@ usb_host: usb@11200000 {
> };
> };
>
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg CLK_IFR_MSDC0_HCLK>,
> + <&infracfg CLK_IFR_MSDC0_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&infracfg CLK_IFR_MSDC1_HCLK>,
> + <&infracfg CLK_IFR_MSDC1_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + mmc2: mmc@11250000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11250000 0 0x1000>,
> + <0 0x11c60000 0 0x1000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
> + <&infracfg CLK_IFR_MSDC2_HCLK>,
> + <&infracfg CLK_IFR_MSDC2_SRC>,
> + <&infracfg CLK_IFR_MSDC2_BK>,
> + <&infracfg CLK_IFR_AP_MSDC0>;
> + clock-names = "source", "hclk", "source_cg",
> + "bus_clk", "sys_cg";
clock-names for this do fit in one 90 columns line.
After compressing it,
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> - Add EMMC support on mmc0 (internal memory)
> - Add SD-UHS support on mmc1 (external memory)
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++++++
> 1 file changed, 138 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index 2f88562c638a..b5d018686cbe 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -97,6 +97,42 @@ &i2c0 {
> #size-cells = <0>;
> };
>
> +&mmc0 {
> + pinctrl-names = "default", "state_uhs";
> + pinctrl-0 = <&mmc0_default_pins>;
> + pinctrl-1 = <&mmc0_uhs_pins>;
> + bus-width = <8>;
> + max-frequency = <200000000>;
> + cap-mmc-highspeed;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + cap-mmc-hw-reset;
> + no-sdio;
> + no-sd;
> + hs400-ds-delay = <0x12012>;
> + vmmc-supply = <&mt6357_vemc_reg>;
> + vqmmc-supply = <&mt6357_vio18_reg>;
> + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
> + non-removable;
That's a bit messy :-)
Can we please reorder this by name?
assigned-clocks....
bus-width
cap....
hs400-ds-delay
max...
mmc-hs...
no...
non-rem...
pinctrl...
vxxxx-supply
status ....
...Actually the same comment also applies to mmc1.
Cheers,
Angelo
Il 29/03/23 10:54, [email protected] ha scritto:
> From: Fabien Parent <[email protected]>
>
> MSDC1 IP block is powered by VMC. Make sure it is always on.
Why always on?
Can't you just set mt6357_vmc_reg as VIN of mt6357_vmch_reg? :-)
Regards,
Angelo
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index b5d018686cbe..22ec332fe9c9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -140,6 +140,11 @@ &mt6357_pmic {
> #interrupt-cells = <2>;
> };
>
> +/* Needed by MSDC1 */
> +&mt6357_vmc_reg {
> + regulator-always-on;
> +};
> +
> &pio {
> gpio_keys: gpio-keys-pins {
> pins {
>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> In order to have cpufreq support, this patch adds proc-supply and sram-supply
> for each CPU.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, [email protected] ha scritto:
> From: Amjad Ouled-Ameur <[email protected]>
>
> MT8365 has 3 CPU Idle states:
> - MCDI_CPU. (Multi-Core-Deep-Idle)
> - MCDI_CLUSTER.
> - DPIDLE. (Deep-Idle)
>
> Signed-off-by: Amjad Ouled-Ameur <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> In order to have cpufreq support, this patch adds generic Operating
> Performance Points support.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 85 ++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index 394a5a61be59..c3ea3cc97a47 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -20,6 +20,75 @@ cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + cluster0_opp: opp-table-0 {
> + compatible = "operating-points-v2";
> + opp-shared;
One blank line here please, makes it slightly more readable.
> + opp-850000000 {
> + opp-hz = /bits/ 64 <850000000>;
> + opp-microvolt = <650000>;
> + };
Also, my personal preference is to also leave a blank line between
each opp-xxxx subnode, but that's your choice.
Everything else looks good.
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards.
> It supports power management with Energy Efficient Ethernet and Wake-on-LAN
> specification. Flow control is provided for half-duplex and full-duplex
> mode. For packet transmission and reception, the controller supports
> IPv4/UDP/TCP checksum offload and VLAN tag insertion.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
> This patch add support for SuperSpeed USB, in OTG mode, on micro connector.
> It also add support for the Extensible Host Controller Interface USB.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index 22ec332fe9c9..868ee0d160e4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -319,6 +319,28 @@ &pwm {
> status = "okay";
> };
>
> +&ssusb {
> + pinctrl-0 = <&usb_pins>;
> + pinctrl-names = "default";
> + maximum-speed = "high-speed";
> + usb-role-switch;
> + dr_mode = "otg";
> + vusb33-supply = <&mt6357_vusb33_reg>;
> + status = "okay";
Order by name please.
P.S.: status can go at the bottom, even if v < s :-)
Thanks,
Angelo
Il 29/03/23 10:54, [email protected] ha scritto:
> From: Amjad Ouled-Ameur <[email protected]>
>
> MT8365 has a SYST timer (System Timer), therefore the compatible node
> should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer"
> (which corresponds to ARM/ARM64 System Timer).
>
> Plus, register range should be 0x100 instead of 0x10.
>
> Finally, interrupt polarity of systimer is LEVEL_HIGH.
>
> Fix the above properties accordingly.
>
> Signed-off-by: Amjad Ouled-Ameur <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Alexandre Mergnat <[email protected]> writes:
> This commits are based on the Fabien Parent <[email protected]> work.
>
> The purpose of this series is to add the following HWs / IPs support for
> the mt8365-evk board:
> - Watchdog
> - Power Management Integrated Circuit "PMIC" wrapper
> - MT6357 PMIC
> - MultiMediaCard "MMC" & Secure Digital "SD" controller
> - USB controller
> - Ethernet MAC controller
>
> Add CPU Freq & IDLE support for this board.
>
> This series depends to another one which add support for MT8365 SoC and
> EVK board [1].
It seems to depend on more than that series. In order to test this, I
tried applying this series on top of Bero's minimal support (now in
linux-next), and it does not apply cleanly.
Could you please list all the dependencies that are not yet upstream.
Thanks,
Kevin
Le jeu. 30 mars 2023 à 02:09, Kevin Hilman <[email protected]> a écrit :
>
> Alexandre Mergnat <[email protected]> writes:
>
> > This commits are based on the Fabien Parent <[email protected]> work.
> >
> > The purpose of this series is to add the following HWs / IPs support for
> > the mt8365-evk board:
> > - Watchdog
> > - Power Management Integrated Circuit "PMIC" wrapper
> > - MT6357 PMIC
> > - MultiMediaCard "MMC" & Secure Digital "SD" controller
> > - USB controller
> > - Ethernet MAC controller
> >
> > Add CPU Freq & IDLE support for this board.
> >
> > This series depends to another one which add support for MT8365 SoC and
> > EVK board [1].
>
> It seems to depend on more than that series. In order to test this, I
> tried applying this series on top of Bero's minimal support (now in
> linux-next), and it does not apply cleanly.
>
> Could you please list all the dependencies that are not yet upstream.
Hi Kevin,
You're right, it also depend to
https://lore.kernel.org/all/[email protected]/
Regards,
Alex
On 29/03/2023 10:54, Alexandre Mergnat wrote:
> Add binding description for mediatek,mt8365-wdt
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> index 55b34461df1b..66cacea8e47f 100644
> --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> @@ -38,6 +38,7 @@ properties:
> - mediatek,mt7623-wdt
> - mediatek,mt7629-wdt
> - mediatek,mt8173-wdt
> + - mediatek,mt8365-wdt
> - mediatek,mt8516-wdt
> - const: mediatek,mt6589-wdt
>
>
On 29/03/2023 10:54, Alexandre Mergnat wrote:
> In order to use the PMIC, the pwrap support should be added
> to allow communication between the SoC and the PMIC.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Applied, thanks.
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index e018df6844f6..687011353f69 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -186,6 +186,18 @@ apmixedsys: syscon@1000c000 {
> #clock-cells = <1>;
> };
>
> + pwrap: pwrap@1000d000 {
> + compatible = "mediatek,mt8365-pwrap";
> + reg = <0 0x1000d000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
> + <&infracfg CLK_IFR_PMIC_AP>,
> + <&infracfg CLK_IFR_PWRAP_SYS>,
> + <&infracfg CLK_IFR_PWRAP_TMR>;
> + clock-names = "spi", "wrap", "sys", "tmr";
> + };
> +
> keypad: keypad@10010000 {
> compatible = "mediatek,mt6779-keypad";
> reg = <0 0x10010000 0 0x1000>;
>
On 29/03/2023 15:21, AngeloGioacchino Del Regno wrote:
> Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
>> There are three ports of MSDC (MMC and SD Controller), which are:
>> - MSDC0: EMMC5.1
>> - MSDC1: SD3.0/SDIO3.0
>> - MSDC2: SDIO3.0+
>>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> index 687011353f69..a67eeca28da5 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> @@ -399,6 +399,45 @@ usb_host: usb@11200000 {
>> };
>> };
>> + mmc0: mmc@11230000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11230000 0 0x1000>,
>> + <0 0x11cd0000 0 0x1000>;
>> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
>> + <&infracfg CLK_IFR_MSDC0_HCLK>,
>> + <&infracfg CLK_IFR_MSDC0_SRC>;
>> + clock-names = "source", "hclk", "source_cg";
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@11240000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11240000 0 0x1000>,
>> + <0 0x11c90000 0 0x1000>;
>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
>> + <&infracfg CLK_IFR_MSDC1_HCLK>,
>> + <&infracfg CLK_IFR_MSDC1_SRC>;
>> + clock-names = "source", "hclk", "source_cg";
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc@11250000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11250000 0 0x1000>,
>> + <0 0x11c60000 0 0x1000>;
>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
>> + <&infracfg CLK_IFR_MSDC2_HCLK>,
>> + <&infracfg CLK_IFR_MSDC2_SRC>,
>> + <&infracfg CLK_IFR_MSDC2_BK>,
>> + <&infracfg CLK_IFR_AP_MSDC0>;
>> + clock-names = "source", "hclk", "source_cg",
>> + "bus_clk", "sys_cg";
>
> clock-names for this do fit in one 90 columns line.
>
> After compressing it,
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>
I applied the patch and dropped you Reviewed-by tag. I think it depends on the
taste of everybody how you prefer to structure this. I've also seen that on
boards you care (mt8183 in that case) there a clocks that don't adhere to the
criteria you mention here ;-)
Anyway many thanks for reviewing this and all the great work in general.
Honestly I feel I didn't made justice by dropping your tag, but as you stated so
explicitly... :)
Regards,
Matthias
On 29/03/2023 15:26, AngeloGioacchino Del Regno wrote:
> Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
>> This patch add support for SuperSpeed USB, in OTG mode, on micro connector.
>> It also add support for the Extensible Host Controller Interface USB.
>>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> index 22ec332fe9c9..868ee0d160e4 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> @@ -319,6 +319,28 @@ &pwm {
>> status = "okay";
>> };
>> +&ssusb {
>> + pinctrl-0 = <&usb_pins>;
>> + pinctrl-names = "default";
>> + maximum-speed = "high-speed";
>> + usb-role-switch;
>> + dr_mode = "otg";
>> + vusb33-supply = <&mt6357_vusb33_reg>;
>> + status = "okay";
>
> Order by name please.
>
> P.S.: status can go at the bottom, even if v < s :-)
You mean v > s ;-)
Yes please reorder keep the status to the bottom that's somehow identical
throughout the kernel.
Regards,
Matthias
>
> Thanks,
> Angelo
On 29/03/2023 10:54, Alexandre Mergnat wrote:
> This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards.
> It supports power management with Energy Efficient Ethernet and Wake-on-LAN
> specification. Flow control is provided for half-duplex and full-duplex
> mode. For packet transmission and reception, the controller supports
> IPv4/UDP/TCP checksum offload and VLAN tag insertion.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Applied thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index a67eeca28da5..394a5a61be59 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -438,6 +438,18 @@ mmc2: mmc@11250000 {
> status = "disabled";
> };
>
> + ethernet: ethernet@112a0000 {
> + compatible = "mediatek,mt8365-eth";
> + reg = <0 0x112a0000 0 0x1000>;
> + mediatek,pericfg = <&infracfg>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topckgen CLK_TOP_ETH_SEL>,
> + <&infracfg CLK_IFR_NIC_AXI>,
> + <&infracfg CLK_IFR_NIC_SLV_AXI>;
> + clock-names = "core", "reg", "trans";
> + status = "disabled";
> + };
> +
> u3phy: t-phy@11cc0000 {
> compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
> #address-cells = <1>;
>
On 29/03/2023 10:54, [email protected] wrote:
> From: Amjad Ouled-Ameur <[email protected]>
>
> MT8365 has a SYST timer (System Timer), therefore the compatible node
> should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer"
> (which corresponds to ARM/ARM64 System Timer).
>
> Plus, register range should be 0x100 instead of 0x10.
>
> Finally, interrupt polarity of systimer is LEVEL_HIGH.
>
> Fix the above properties accordingly.
>
> Signed-off-by: Amjad Ouled-Ameur <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Patch looks good but does not apply cleanly because of previous patches that I
didn't take and need rework. Please resend the patches I didn't queue with the
comments addressed.
Regards,
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index c3ea3cc97a47..959d8533c24c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -575,9 +575,9 @@ system_clk: dummy13m {
> };
>
> systimer: timer@10017000 {
> - compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer";
> - reg = <0 0x10017000 0 0x10>;
> - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
> + compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x100>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&system_clk>;
> clock-names = "clk13m";
> };
>
Alexandre Mergnat <[email protected]> writes:
> Le jeu. 30 mars 2023 à 02:09, Kevin Hilman <[email protected]> a écrit :
>>
>> Alexandre Mergnat <[email protected]> writes:
>>
>> > This commits are based on the Fabien Parent <[email protected]> work.
>> >
>> > The purpose of this series is to add the following HWs / IPs support for
>> > the mt8365-evk board:
>> > - Watchdog
>> > - Power Management Integrated Circuit "PMIC" wrapper
>> > - MT6357 PMIC
>> > - MultiMediaCard "MMC" & Secure Digital "SD" controller
>> > - USB controller
>> > - Ethernet MAC controller
>> >
>> > Add CPU Freq & IDLE support for this board.
>> >
>> > This series depends to another one which add support for MT8365 SoC and
>> > EVK board [1].
>>
>> It seems to depend on more than that series. In order to test this, I
>> tried applying this series on top of Bero's minimal support (now in
>> linux-next), and it does not apply cleanly.
>>
>> Could you please list all the dependencies that are not yet upstream.
>
> Hi Kevin,
> You're right, it also depend to
> https://lore.kernel.org/all/[email protected]/
Nope. Something else is missing too. I tried this series on top of
Bero's series + i2c series and still doesn't apply cleanly. Look like
some pinctrl stuff is also missing[1].
Kevin
[1]
Link: https://lore.kernel.org/r/[email protected]
Base: base-commit 555b3a55823ec063129de4403899203febb58788 not known, ignoring
Base: not specified
git am /ssd/work/tmp/b4.mbx
Applying: dt-bindings: watchdog: mediatek,mtk-wdt: add mt8365
Applying: dt-bindings: pinctrl: mediatek,mt8365-pinctrl: add drive strength property
error: Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml: does not exist in index
Patch failed at 0002 dt-bindings: pinctrl: mediatek,mt8365-pinctrl: add drive strength property
Le mer. 29 mars 2023 à 15:25, AngeloGioacchino Del Regno
<[email protected]> a écrit :
>
> Il 29/03/23 10:54, [email protected] ha scritto:
> > From: Fabien Parent <[email protected]>
> >
> > MSDC1 IP block is powered by VMC. Make sure it is always on.
>
> Why always on?
> Can't you just set mt6357_vmc_reg as VIN of mt6357_vmch_reg? :-)
I'm not sure to get it. mt6357_vmc_reg & mt6357_vmch_reg come from
PMIC and are supposed to be independent.
You suggest to link them in the mt8365-evk dts file using something like:
&mt6357_vmch_reg {
vin-supply = <&mt6357_vmc_reg>;
};
Also, regulator binding probably needs change to support that.
Regards,
Alex
Le ven. 31 mars 2023 à 13:08, Alexandre Mergnat
<[email protected]> a écrit :
>
> Le mer. 29 mars 2023 à 15:25, AngeloGioacchino Del Regno
> <[email protected]> a écrit :
> >
> > Il 29/03/23 10:54, [email protected] ha scritto:
> > > From: Fabien Parent <[email protected]>
> > >
> > > MSDC1 IP block is powered by VMC. Make sure it is always on.
> >
> > Why always on?
> > Can't you just set mt6357_vmc_reg as VIN of mt6357_vmch_reg? :-)
>
> I'm not sure to get it. mt6357_vmc_reg & mt6357_vmch_reg come from
> PMIC and are supposed to be independent.
> You suggest to link them in the mt8365-evk dts file using something like:
> &mt6357_vmch_reg {
> vin-supply = <&mt6357_vmc_reg>;
> };
Additionally, vin-supply is supported by fixed-regulator and
gpio-regulator, which is not the case here.
I think it isn't doable.
Regards,
Alex
Hi Matthias
Le jeu. 30 mars 2023 à 19:34, Matthias Brugger
<[email protected]> a écrit :
>
>
>
> On 29/03/2023 10:54, [email protected] wrote:
> > From: Amjad Ouled-Ameur <[email protected]>
> >
> > MT8365 has a SYST timer (System Timer), therefore the compatible node
> > should be "mediatek,mt6765-timer" instead of "mediatek,mt6795-systimer"
> > (which corresponds to ARM/ARM64 System Timer).
> >
> > Plus, register range should be 0x100 instead of 0x10.
> >
> > Finally, interrupt polarity of systimer is LEVEL_HIGH.
> >
> > Fix the above properties accordingly.
> >
> > Signed-off-by: Amjad Ouled-Ameur <[email protected]>
> > Signed-off-by: Alexandre Mergnat <[email protected]>
>
> Patch looks good but does not apply cleanly because of previous patches that I
> didn't take and need rework. Please resend the patches I didn't queue with the
> comments addressed.
Sorry for that, I forgot to drop this patch since it has been already
fixed in the Bero's series [1]
I will drop it for the next version
[1]: https://lore.kernel.org/all/[email protected]/
Regards,
Alex
On Wed, Mar 29, 2023 at 10:54:22AM +0200, Alexandre Mergnat wrote:
> Add binding description for mediatek,mt8365-wdt
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> index 55b34461df1b..66cacea8e47f 100644
> --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
> @@ -38,6 +38,7 @@ properties:
> - mediatek,mt7623-wdt
> - mediatek,mt7629-wdt
> - mediatek,mt8173-wdt
> + - mediatek,mt8365-wdt
> - mediatek,mt8516-wdt
> - const: mediatek,mt6589-wdt
>