This patch series adds dma support for the StarFive JH7110 RISC-V SoC.
The first patch adds device tree binding. The second patch includes dma
driver. The last patch adds device node of dma to JH7110 dts.
The series has been tested on the VisionFive 2 board which equip with
JH7110 SoC and works normally.
The last patch should be applied after the following patchset:
https://lore.kernel.org/all/[email protected]/
Walker Chen (3):
dt-bindings: dma: snps,dw-axi-dmac: Update resets and add
snps,num-hs-if
dma: dw-axi-dmac: Add support for StarFive DMA
riscv: dts: starfive: add dma controller node
.../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++-
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +++++++++++++++
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
4 files changed, 60 insertions(+), 5 deletions(-)
base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476
prerequisite-patch-id: 54ce870d6ea747466474b5d4105cfbc05e1b01ab
prerequisite-patch-id: e8dd8258a4c4062eee2cf07c4607d52baea71f3a
prerequisite-patch-id: 057fa35870d8d7d22a57c13362588ffb9e9df316
prerequisite-patch-id: 102368a6ff799c4cb639aed513deff09c1839161
prerequisite-patch-id: 7c1a50a37919fedbbd336ca5dec295ac63c2a89d
prerequisite-patch-id: a5d9e0f7d4f8163f566678894cf693015119f2d9
prerequisite-patch-id: 87cb528acd9a7f1ffe7475d7261553f6a4de5753
prerequisite-patch-id: 417736eb958e1158c60a5ed74bc2350394321a80
prerequisite-patch-id: a137312ca162b5712e28719f77d0da78e9fdd778
prerequisite-patch-id: f7c548b4619f491ce27f319242c4e3685c76173b
prerequisite-patch-id: 4d90febab2fb7928f50a73104e7454312b9ce6c8
prerequisite-patch-id: 645a807d50e0e56593ffdc6c3b50ea54a230827a
prerequisite-patch-id: 165f8cd740ae60585d22c95b99a0689084d468e3
prerequisite-patch-id: 480d910deccadc2947b3318c3c13dfa0882c8e0d
prerequisite-patch-id: 1d1cb90ec12dfc9312e448759c7cab89f2bc6394
prerequisite-patch-id: 5f539ac7c96023b36489c6da7c70c31eaf64a25b
prerequisite-patch-id: 6bb9a780c62af3bcc2368dfd20303c7b1bc91e23
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: e3b986b9c60b2b93b7812ec174c9e1b4cfb14c97
prerequisite-patch-id: 2e03eeb766aefd5d38f132d091618e9fa19a37b6
prerequisite-patch-id: e0ba7af0f8d3d41844da9fbcba14b548cbc18f55
prerequisite-patch-id: c1f8603e58c64828d0f36deac9b93c24289d8e05
prerequisite-patch-id: d73b2371a15f99416566904dedd45be30109aa84
prerequisite-patch-id: fbbd7f621c50a0762b188f52585e3418f9896a28
prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40
prerequisite-patch-id: dd10a6d021de43aef31a1df70fc1a7f8a710d137
prerequisite-patch-id: 7acbc9c924e802712d3574dd74a6b3576089f78c
prerequisite-patch-id: e0ac2cb2de37dcd8c6a3f27d6cba1164a6967145
prerequisite-patch-id: ce8a6557564ba04bd90bb41d34f520347f399887
prerequisite-patch-id: 9f71c539a241baf1e73c7e7dfde5b0b04c66a502
prerequisite-patch-id: 0813e1684f69e106bc7a84e5f5a1f40a28e8a38d
prerequisite-patch-id: bb8e071ed43998874b9d98292c0dcdeedc0760ca
prerequisite-patch-id: 0c04762f1d20f09cd2a1356334a86e520907d111
prerequisite-patch-id: 23db1e84f5de4e117427509c466ae1c106e367bf
prerequisite-patch-id: 56577b43ff594598eaa3c1dc9f7caa462d7f94cd
prerequisite-patch-id: 2bc43b375b470f7e8bbe937b78678ba3856e3b8f
--
2.17.1
Add two reset items and properties 'snps,num-hs-if'.
The DMA controller needs to be reset before being used in JH7110 SoC.
Another difference from the original version is that the hardware
handshake number of DMA can be up to 56 while the number in original
version is less than 16, and different registers are selected according
to this.
Signed-off-by: Walker Chen <[email protected]>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 67aa7bb6d36a..1a8d8c20e254 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
maintainers:
- Eugeniy Paltsev <[email protected]>
- Jee Heng Sia <[email protected]>
+ - Walker Chen <[email protected]>
description:
Synopsys DesignWare AXI DMA Controller DT Binding
@@ -21,6 +22,7 @@ properties:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
+ - starfive,axi-dma
reg:
minItems: 1
@@ -59,7 +61,12 @@ properties:
maximum: 8
resets:
- maxItems: 1
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: axi-rst
+ - const: ahb-rst
snps,dma-masters:
description: |
@@ -74,6 +81,14 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6]
+ snps,num-hs-if:
+ description: |
+ The number of hardware handshake. If it is more than 16,
+ CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 256
+
snps,priority:
description: |
Channel priority specifier associated with the DMA channels.
--
2.17.1
Adding DMA reset operation in device probe, and using different
registers according to the hardware handshake number.
Signed-off-by: Walker Chen <[email protected]>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a183d93bd7e2..3581810033d2 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -25,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
- if (chan->chip->dw->hdata->reg_map_8_channels) {
+ if (chan->chip->dw->hdata->reg_map_8_channels &&
+ !chan->chip->dw->hdata->use_cfg2) {
cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
@@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
(chan->id * DMA_APB_HS_SEL_BIT_SIZE));
reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
-
- return;
}
/*
@@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
axi_chan_disable(chan);
ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
- !(val & chan_active), 1000, 10000);
+ !(val & chan_active), 1000, DMAC_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
@@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
chip->dw->hdata->m_data_width = tmp;
+ ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp);
+ if (!ret) {
+ if (tmp > 16)
+ chip->dw->hdata->use_cfg2 = true;
+ }
+
ret = device_property_read_u32_array(dev, "snps,block-size", carr,
chip->dw->hdata->nr_channels);
if (ret)
@@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->cfgr_clk))
return PTR_ERR(chip->cfgr_clk);
+ if (of_device_is_compatible(node, "starfive,axi-dma")) {
+ chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
+ if (IS_ERR(chip->resets))
+ return PTR_ERR(chip->resets);
+
+ ret = reset_control_deassert(chip->resets);
+ if (ret)
+ return ret;
+ }
+
ret = parse_device_properties(chip);
if (ret)
return ret;
@@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
{ .compatible = "intel,kmb-axi-dma" },
+ { .compatible = "starfive,axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index e9d5eb0fd594..761d95691c02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -21,6 +21,7 @@
#define DMAC_MAX_CHANNELS 16
#define DMAC_MAX_MASTERS 2
#define DMAC_MAX_BLK_SIZE 0x200000
+#define DMAC_TIMEOUT_US 200000
struct dw_axi_dma_hcfg {
u32 nr_channels;
@@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg {
/* Register map for DMAX_NUM_CHANNELS <= 8 */
bool reg_map_8_channels;
bool restrict_axi_burst_len;
+ bool use_cfg2;
};
struct axi_dma_chan {
@@ -70,6 +72,7 @@ struct axi_dma_chip {
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
+ struct reset_control *resets;
};
/* LLI == Linked List Item */
--
2.17.1
Adding the dma controller node for the Starfive JH7110 SoC.
Signed-off-by: Walker Chen <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index cfbaff4ea64b..1628c0f33fab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -412,6 +412,26 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@16050000 {
+ compatible = "starfive,axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ reset-names = "axi-rst", "ahb-rst";
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,num-hs-if = <56>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
On Mon, Feb 06, 2023 at 07:38:09PM +0800, Walker Chen wrote:
> Add two reset items and properties 'snps,num-hs-if'.
> The DMA controller needs to be reset before being used in JH7110 SoC.
> Another difference from the original version is that the hardware
> handshake number of DMA can be up to 56 while the number in original
> version is less than 16, and different registers are selected according
> to this.
>
> Signed-off-by: Walker Chen <[email protected]>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 67aa7bb6d36a..1a8d8c20e254 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
> maintainers:
> - Eugeniy Paltsev <[email protected]>
> - Jee Heng Sia <[email protected]>
> + - Walker Chen <[email protected]>
>
> description:
> Synopsys DesignWare AXI DMA Controller DT Binding
> @@ -21,6 +22,7 @@ properties:
> enum:
> - snps,axi-dma-1.01a
> - intel,kmb-axi-dma
> + - starfive,axi-dma
This should be SoC specific.
>
> reg:
> minItems: 1
> @@ -59,7 +61,12 @@ properties:
> maximum: 8
>
> resets:
> - maxItems: 1
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: axi-rst
> + - const: ahb-rst
'-rst' is redundant.
>
> snps,dma-masters:
> description: |
> @@ -74,6 +81,14 @@ properties:
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [0, 1, 2, 3, 4, 5, 6]
>
> + snps,num-hs-if:
> + description: |
> + The number of hardware handshake. If it is more than 16,
> + CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
Can't you infer this from the compatible string?
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 256
> +
> snps,priority:
> description: |
> Channel priority specifier associated with the DMA channels.
> --
> 2.17.1
>
On 06-02-23, 19:38, Walker Chen wrote:
> Adding DMA reset operation in device probe, and using different
> registers according to the hardware handshake number.
subsystem tag is dmaengine: xxx
>
> Signed-off-by: Walker Chen <[email protected]>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
> 2 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index a183d93bd7e2..3581810033d2 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -25,6 +25,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
what about older/other platforms that dont have use_cfg2?
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
> (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
> -
> - return;
> }
>
> /*
> @@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
> axi_chan_disable(chan);
>
> ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
> - !(val & chan_active), 1000, 10000);
> + !(val & chan_active), 1000, DMAC_TIMEOUT_US);
> if (ret == -ETIMEDOUT)
> dev_warn(dchan2dev(dchan),
> "%s failed to stop\n", axi_chan_name(chan));
> @@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> chip->dw->hdata->m_data_width = tmp;
>
> + ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp);
> + if (!ret) {
> + if (tmp > 16)
> + chip->dw->hdata->use_cfg2 = true;
> + }
> +
> ret = device_property_read_u32_array(dev, "snps,block-size", carr,
> chip->dw->hdata->nr_channels);
> if (ret)
> @@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->cfgr_clk))
> return PTR_ERR(chip->cfgr_clk);
>
> + if (of_device_is_compatible(node, "starfive,axi-dma")) {
> + chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(chip->resets))
> + return PTR_ERR(chip->resets);
> +
> + ret = reset_control_deassert(chip->resets);
> + if (ret)
> + return ret;
> + }
> +
> ret = parse_device_properties(chip);
> if (ret)
> return ret;
> @@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> static const struct of_device_id dw_dma_of_id_table[] = {
> { .compatible = "snps,axi-dma-1.01a" },
> { .compatible = "intel,kmb-axi-dma" },
> + { .compatible = "starfive,axi-dma" },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..761d95691c02 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -21,6 +21,7 @@
> #define DMAC_MAX_CHANNELS 16
> #define DMAC_MAX_MASTERS 2
> #define DMAC_MAX_BLK_SIZE 0x200000
> +#define DMAC_TIMEOUT_US 200000
>
> struct dw_axi_dma_hcfg {
> u32 nr_channels;
> @@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> @@ -70,6 +72,7 @@ struct axi_dma_chip {
> struct clk *core_clk;
> struct clk *cfgr_clk;
> struct dw_axi_dma *dw;
> + struct reset_control *resets;
> };
>
> /* LLI == Linked List Item */
> --
> 2.17.1
--
~Vinod
On 2023/2/8 4:58, Rob Herring wrote:
> On Mon, Feb 06, 2023 at 07:38:09PM +0800, Walker Chen wrote:
>> Add two reset items and properties 'snps,num-hs-if'.
>> The DMA controller needs to be reset before being used in JH7110 SoC.
>> Another difference from the original version is that the hardware
>> handshake number of DMA can be up to 56 while the number in original
>> version is less than 16, and different registers are selected according
>> to this.
>>
>> Signed-off-by: Walker Chen <[email protected]>
>> ---
>> .../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> index 67aa7bb6d36a..1a8d8c20e254 100644
>> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> @@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
>> maintainers:
>> - Eugeniy Paltsev <[email protected]>
>> - Jee Heng Sia <[email protected]>
>> + - Walker Chen <[email protected]>
>>
>> description:
>> Synopsys DesignWare AXI DMA Controller DT Binding
>> @@ -21,6 +22,7 @@ properties:
>> enum:
>> - snps,axi-dma-1.01a
>> - intel,kmb-axi-dma
>> + - starfive,axi-dma
>
> This should be SoC specific.
Well, so this should be 'starfive,jh7110-axi-dma'.
>
>>
>> reg:
>> minItems: 1
>> @@ -59,7 +61,12 @@ properties:
>> maximum: 8
>>
>> resets:
>> - maxItems: 1
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: axi-rst
>> + - const: ahb-rst
>
> '-rst' is redundant.
Okay, will be drop '-rst' in next version.
>
>>
>> snps,dma-masters:
>> description: |
>> @@ -74,6 +81,14 @@ properties:
>> $ref: /schemas/types.yaml#/definitions/uint32
>> enum: [0, 1, 2, 3, 4, 5, 6]
>>
>> + snps,num-hs-if:
>> + description: |
>> + The number of hardware handshake. If it is more than 16,
>> + CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
>
> Can't you infer this from the compatible string?
Yeah, maybe this is also feasible from the compatible string.
Thanks.
Best regards,
Walker
On 2023/2/10 16:59, Vinod Koul wrote:
> On 06-02-23, 19:38, Walker Chen wrote:
>> Adding DMA reset operation in device probe, and using different
>> registers according to the hardware handshake number.
>
> subsystem tag is dmaengine: xxx
OK, the tag will be changed to dmaengine.
>
>>
>> Signed-off-by: Walker Chen <[email protected]>
>> ---
>> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
>> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
>> 2 files changed, 24 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> index a183d93bd7e2..3581810033d2 100644
>> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> @@ -25,6 +25,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <linux/reset.h>
>> #include <linux/slab.h>
>> #include <linux/types.h>
>>
>> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>>
>> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
>> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
>> - if (chan->chip->dw->hdata->reg_map_8_channels) {
>> + if (chan->chip->dw->hdata->reg_map_8_channels &&
>> + !chan->chip->dw->hdata->use_cfg2) {
>
> what about older/other platforms that dont have use_cfg2?
The use_cfg2 variable's default value is false, the original logic will not be affected.
Rob herring gave a suggestion that it is assigned according to compatible string, like that:
if (of_device_is_compatible(node, "starfive,jh7110-axi-dma")) {
...
chip->dw->hdata->use_cfg2 = true;
}
>
>> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
>> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
>> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
>> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
>> (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
>> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
>> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
>> -
>> - return;
>> }
>>
Thanks
Best regards,
Walker
On 2023/2/6 19:38, Walker Chen wrote:
> Adding DMA reset operation in device probe, and using different
> registers according to the hardware handshake number.
>
> Signed-off-by: Walker Chen <[email protected]>
Hi Eugeniy Paltsev / Emil,
Could you please help to review and provide comments on this patch series?
Any comments will be appreciated!
Best regards,
Walker Chen