Hi,
This series fixes the issue with PCI I/O ranges defined in devicetree of
Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
identical mapping for the PCI I/O range. But the PCI device I/O ports
are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
mostly bogus. The lack of bug report on this issue indicates that no one really
tested legacy PCI devices with these SoCs.
This series also contains a couple of cleanup patches that aligns the entries of
ranges property.
Thanks,
Mani
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
Manivannan Sadhasivam (16):
arm64: dts: qcom: sdm845: Fix the PCI I/O port range
arm64: dts: qcom: msm8998: Fix the PCI I/O port range
arm64: dts: qcom: sc7280: Fix the PCI I/O port range
arm64: dts: qcom: sm8550: Fix the PCI I/O port range
arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
arm64: dts: qcom: ipq6018: Fix the PCI I/O port range
arm64: dts: qcom: msm8996: Fix the PCI I/O port range
arm64: dts: qcom: sm8250: Fix the PCI I/O port range
arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges
arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range
arm64: dts: qcom: sm8150: Fix the PCI I/O port range
arm64: dts: qcom: sm8450: Fix the PCI I/O port range
arm64: dts: qcom: sm8350: Fix the PCI I/O port range
ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++-----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
16 files changed, 53 insertions(+), 57 deletions(-)
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller")
Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 479859bd8ab3..1c060ea960ff 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2292,8 +2292,8 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -2397,7 +2397,7 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address
(0x1b200000) specified in the ranges property for I/O region.
Fixes: b84dfd175c09 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 8bc1c59127e5..5863332962e4 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -922,7 +922,7 @@ pcie0: pci@1c00000 {
phy-names = "pciephy";
status = "disabled";
- ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
#interrupt-cells = <1>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address
(0x40200000) specified in the ranges property for I/O region.
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index bdcb74925313..99845c79a8c4 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2077,7 +2077,7 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ff4d342c0725..f8d7b4dde878 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1653,8 +1653,8 @@ pcie0: pci@1c00000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
bus-range = <0x00 0xff>;
dma-coherent;
@@ -1752,8 +1752,8 @@ pcie1: pci@1c08000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
- <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
bus-range = <0x00 0xff>;
dma-coherent;
--
2.25.1
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses
(0x10200000, 0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses and align
them in a single line.
Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 62d05d740646..e8dad3ff4fcc 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -780,10 +780,8 @@ pcie1: pci@10000000 {
phys = <&pcie_phy1>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x10200000 0x10200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x10220000 0x10220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -844,10 +842,8 @@ pcie0: pci@20000000 {
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0x20200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x20220000 0x20220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address
(0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 095bbdd9a5c3 ("arm64: dts: qcom: ipq6018: Add pcie support")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index bbd94025ff5d..9ff4e9d45065 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -738,8 +738,8 @@ pcie0: pci@20000000 {
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
- <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
+ <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for
I/O region.
While at it, let's also align the entries.
Fixes: ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 905678e7175d..66af9526c98b 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1851,8 +1851,8 @@ pcie0: pcie@600000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
- <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
device_type = "pci";
@@ -1905,8 +1905,8 @@ pcie1: pcie@608000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
- <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
device_type = "pci";
@@ -1956,8 +1956,8 @@ pcie2: pcie@610000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
- <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
device_type = "pci";
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000, 0x64200000) specified in the ranges property for
I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 2f0e460acccd..e592ddcc0f07 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1834,8 +1834,8 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
@@ -1943,7 +1943,7 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
@@ -2051,7 +2051,7 @@ pcie2: pci@1c10000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
--
2.25.1
To maintain the uniformity, let's use the 0x prefix for the values of
ranges property.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index bc2ed73afb74..42fc33ab8b2e 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1469,8 +1469,8 @@ pcie: pci@10000000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
- <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
+ ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
+ <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in
the ranges property for I/O region.
Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0d02599d8867..a0065656442c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1657,7 +1657,7 @@ pcie4: pcie@1c00000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
<0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@@ -1756,7 +1756,7 @@ pcie3b: pcie@1c08000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
<0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@@ -1853,7 +1853,7 @@ pcie3a: pcie@1c10000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
<0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@@ -1953,7 +1953,7 @@ pcie2b: pcie@1c18000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
<0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@@ -2050,7 +2050,7 @@ pcie2a: pcie@1c20000 {
reg-names = "parf", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index fd20096cfc6e..1fabfa05708c 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1799,8 +1799,8 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -1895,7 +1895,7 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device")
Fixes: 7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1a744a33bcf4..3c9b9425da12 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1746,8 +1746,8 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
/*
* MSIs for BDF (1:0.0) only works with Device ID 0x5980.
@@ -1862,8 +1862,8 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
- <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
/*
* MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 1c97e28da6ad..1ca16bfc8988 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1487,8 +1487,8 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
@@ -1581,8 +1581,8 @@ pcie1: pci@1c08000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
- <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
To maintain the uniformity, let's use the 0x prefix for the values of
ranges property.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92aa2b081901..210b24e510c5 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1494,8 +1494,8 @@ pcie: pci@1b500000 {
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
- <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
+ <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
--
2.25.1
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address
(0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 187519403273 ("ARM: dts: ipq4019: Add a few peripheral nodes")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 02e9ea78405d..1159268f06d7 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -426,8 +426,8 @@ pcie0: pci@40000000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
- <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
+ ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
+ <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses
(0x0fe00000, 0x31e00000, 0x35e00000) specified in the ranges property for
I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 93241840b664 ("ARM: dts: qcom: Add pcie nodes for ipq8064")
Reported-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 52d77e105957..59fc18c448c4 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1081,8 +1081,8 @@ pcie0: pci@1b500000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -1132,8 +1132,8 @@ pcie1: pci@1b700000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -1183,8 +1183,8 @@ pcie2: pci@1b900000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
--
2.25.1
On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
> located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
> (0x60200000, 0x40200000) specified in the ranges property for I/O region.
> - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
>
This fixes the offset, but I wonder if the size of the I/O
window should be changed as well. The normal size is 64KB
(0x10000) per bus or less, while this one has 1MB.
It's probably harmless since each device would only use
a few bytes, and most devices don't need any I/O ports
at all.
Arnd
On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> Hi,
>
> This series fixes the issue with PCI I/O ranges defined in devicetree of
> Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> identical mapping for the PCI I/O range. But the PCI device I/O ports
> are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> mostly bogus. The lack of bug report on this issue indicates that no one really
> tested legacy PCI devices with these SoCs.
>
> This series also contains a couple of cleanup patches that aligns the entries of
> ranges property.
Looks good to me. I already commented that we may also want to use
64KB everywhere instead of 1MB for the per-host window size. Regardless
of that, please add
Reviewed-by: Arnd Bergmann <[email protected]>
I would also prefer to do this in fewer patches, maybe one to
change all the prefixes, and another one to change the location,
or whichever way Bjorn prefers.
Arnd
On Tue, Feb 28, 2023 at 10:17:36PM +0530, Manivannan Sadhasivam wrote:
> Hi,
>
> This series fixes the issue with PCI I/O ranges defined in devicetree of
> Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> identical mapping for the PCI I/O range. But the PCI device I/O ports
> are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> mostly bogus. The lack of bug report on this issue indicates that no one really
> tested legacy PCI devices with these SoCs.
>
> This series also contains a couple of cleanup patches that aligns the entries of
> ranges property.
>
> Thanks,
> Mani
>
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Manivannan Sadhasivam (16):
> arm64: dts: qcom: sdm845: Fix the PCI I/O port range
> arm64: dts: qcom: msm8998: Fix the PCI I/O port range
> arm64: dts: qcom: sc7280: Fix the PCI I/O port range
> arm64: dts: qcom: sm8550: Fix the PCI I/O port range
> arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
> arm64: dts: qcom: ipq6018: Fix the PCI I/O port range
> arm64: dts: qcom: msm8996: Fix the PCI I/O port range
> arm64: dts: qcom: sm8250: Fix the PCI I/O port range
> arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges
> arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range
> arm64: dts: qcom: sm8150: Fix the PCI I/O port range
> arm64: dts: qcom: sm8450: Fix the PCI I/O port range
> arm64: dts: qcom: sm8350: Fix the PCI I/O port range
> ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
> ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
> ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
>
> arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++--
Would you mind giving sa8540p.dtsi to similiar treatment? I will admit
I know next to nothing about PCI techically, so I can't even comment
with confidence that this is needed there, but it looks similar to other
descriptions modified in this patch series.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sa8540p.dtsi#n197
Thanks,
Andrew
On Tue, Feb 28, 2023 at 05:58:37PM +0100, Arnd Bergmann wrote:
> On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series fixes the issue with PCI I/O ranges defined in devicetree of
> > Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> > identical mapping for the PCI I/O range. But the PCI device I/O ports
> > are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> > mostly bogus. The lack of bug report on this issue indicates that no one really
> > tested legacy PCI devices with these SoCs.
> >
> > This series also contains a couple of cleanup patches that aligns the entries of
> > ranges property.
>
> Looks good to me. I already commented that we may also want to use
> 64KB everywhere instead of 1MB for the per-host window size.
I also spotted this discrepancy while working on this series, but the size
seems to be not universal across SoCs from many vendors. So I settled with
whatever range that was used before.
> Regardless of that, please add
>
> Reviewed-by: Arnd Bergmann <[email protected]>
>
> I would also prefer to do this in fewer patches, maybe one to
> change all the prefixes, and another one to change the location,
> or whichever way Bjorn prefers.
>
Well, the only intention of doing a per-patch change is to backport them if
needed. But I'll defer it to Bjorn.
Thanks,
Mani
> Arnd
--
மணிவண்ணன் சதாசிவம்
On Tue, Feb 28, 2023 at 11:29:52AM -0600, Andrew Halaney wrote:
> On Tue, Feb 28, 2023 at 10:17:36PM +0530, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series fixes the issue with PCI I/O ranges defined in devicetree of
> > Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> > identical mapping for the PCI I/O range. But the PCI device I/O ports
> > are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> > mostly bogus. The lack of bug report on this issue indicates that no one really
> > tested legacy PCI devices with these SoCs.
> >
> > This series also contains a couple of cleanup patches that aligns the entries of
> > ranges property.
> >
> > Thanks,
> > Mani
> >
> > [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
> >
> > Manivannan Sadhasivam (16):
> > arm64: dts: qcom: sdm845: Fix the PCI I/O port range
> > arm64: dts: qcom: msm8998: Fix the PCI I/O port range
> > arm64: dts: qcom: sc7280: Fix the PCI I/O port range
> > arm64: dts: qcom: sm8550: Fix the PCI I/O port range
> > arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
> > arm64: dts: qcom: ipq6018: Fix the PCI I/O port range
> > arm64: dts: qcom: msm8996: Fix the PCI I/O port range
> > arm64: dts: qcom: sm8250: Fix the PCI I/O port range
> > arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges
> > arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range
> > arm64: dts: qcom: sm8150: Fix the PCI I/O port range
> > arm64: dts: qcom: sm8450: Fix the PCI I/O port range
> > arm64: dts: qcom: sm8350: Fix the PCI I/O port range
> > ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
> > ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
> > ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
> >
> > arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
> > arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------
> > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
> > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
> > arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------
> > arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
> > arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++--
>
> Would you mind giving sa8540p.dtsi to similiar treatment? I will admit
> I know next to nothing about PCI techically, so I can't even comment
> with confidence that this is needed there, but it looks similar to other
> descriptions modified in this patch series.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sa8540p.dtsi#n197
Ah, I didn't spot the separate ranges used for this SoC. Will fix it in next
revision.
Thanks,
Mani
>
> Thanks,
> Andrew
>
--
மணிவண்ணன் சதாசிவம்
On Wed, Mar 1, 2023, at 12:29, Manivannan Sadhasivam wrote:
> On Tue, Feb 28, 2023 at 05:58:37PM +0100, Arnd Bergmann wrote:
>> On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
>> > Hi,
>> >
>> > This series fixes the issue with PCI I/O ranges defined in devicetree of
>> > Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
>> > identical mapping for the PCI I/O range. But the PCI device I/O ports
>> > are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
>> > mostly bogus. The lack of bug report on this issue indicates that no one really
>> > tested legacy PCI devices with these SoCs.
>> >
>> > This series also contains a couple of cleanup patches that aligns the entries of
>> > ranges property.
>>
>> Looks good to me. I already commented that we may also want to use
>> 64KB everywhere instead of 1MB for the per-host window size.
>
> I also spotted this discrepancy while working on this series, but the size
> seems to be not universal across SoCs from many vendors. So I settled with
> whatever range that was used before.
Makes sense. We could add another patch if necessary of course, and
it probably doesn't matter much. OTOH I don't think there is anything
SoC specific in this and we used to just truncate this to 64KB per
domain. It's only really a problem if the total size of the I/O ports
for all domains in a system exceeds the 16MB of virtual memory area.
Arnd
On Tue, 28 Feb 2023 22:17:36 +0530, Manivannan Sadhasivam wrote:
> This series fixes the issue with PCI I/O ranges defined in devicetree of
> Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> identical mapping for the PCI I/O range. But the PCI device I/O ports
> are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> mostly bogus. The lack of bug report on this issue indicates that no one really
> tested legacy PCI devices with these SoCs.
>
> [...]
Applied, thanks!
[14/16] ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
commit: 84160da56dd0ce48dd8eed56237cc8be45bd55dc
[15/16] ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
commit: 2540279e9a9e74fc880d1e4c83754ecfcbe290a0
[16/16] ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
commit: 0b16b34e491629016109e56747ad64588074194b
Best regards,
--
Bjorn Andersson <[email protected]>