From: Sinthu Raja <[email protected]>
Hi All,
This patch series fix the incorrect IO PADCONFIG offset size of the
wakeup domain for J721S2 SoC and add RPi expansion header support for
AM68 SK.
Changes in V3:
- Add Fixes tag.
Changes in V2:
- Update commit description.
- Update the offset value to 0x194 as 0x190 is the last register of the
IO PADCONFIG register set.
V1: https://lore.kernel.org/all/[email protected]/
V2: https://lore.kernel.org/lkml/[email protected]/T/
Sinthu Raja (2):
arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix IO PADCONFIG size for wakeup
domain
arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header
.../boot/dts/ti/k3-am68-sk-base-board.dts | 70 ++++++++++++++++++-
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +-
2 files changed, 70 insertions(+), 2 deletions(-)
--
2.36.1
From: Sinthu Raja <[email protected]>
The size of wkup domain I/O PADCONFIG register set is incorrect for J721S2.
Therefore, update the PADCONFIG total offset size to the correct value for
J721S22 SoC.
Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Signed-off-by: Sinthu Raja <[email protected]>
---
Changes in V3:
- Added Fix tag
Changes in V2:
- Update commit description.
- Update the offset value to 0x194 because 0x190 is the last register of the
IO PADCONFIG register set.
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 0af242aa9816..b10f1e8b98e6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -50,7 +50,7 @@ mcu_ram: sram@41c00000 {
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
+ reg = <0x00 0x4301c000 0x00 0x194>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
--
2.36.1
From: Sinthu Raja <[email protected]>
Add pinmux required to bring out the i2c and gpios on 40-pin RPi
expansion header on the AM68 SK board.
Signed-off-by: Sinthu Raja <[email protected]>
---
No Changes in V3.
.../boot/dts/ti/k3-am68-sk-base-board.dts | 70 ++++++++++++++++++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 27a43a8ecffd..118308cfdd75 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -173,6 +173,32 @@ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
>;
};
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 7) /* (AF28) MCAN13_RX.I2C4_SDA */
+ J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 7) /* (AD25) MCAN14_TX.I2C4_SCL */
+ >;
+ };
+
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
+ J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
+ J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
+ J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
+ J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
+ J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
+ J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
+ J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
+ J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
+ J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
+ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
+ >;
+ };
};
&wkup_pmx0 {
@@ -214,12 +240,39 @@ J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
>;
};
+ mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /*(H24) WKUP_GPIO0_63.MCU_I2C0_SCL*/
+ J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /*(H27) WKUP_GPIO0_64.MCU_I2C0_SDA*/
+ >;
+ };
+
mcu_i2c1_pins_default: mcu-i2c1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
>;
};
+
+ mcu_rpi_header_gpio0_pins_default: mcu-rpi-header-gpio0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
+ J721S2_WKUP_IOPAD(0x190, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
+ J721S2_WKUP_IOPAD(0x0c4, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
+ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
+ J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
+ J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
+ J721S2_WKUP_IOPAD(0x120, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
+ J721S2_WKUP_IOPAD(0x17c, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
+ J721S2_WKUP_IOPAD(0x184, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
+ J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
+ >;
+ };
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&main_gpio2 {
@@ -235,7 +288,8 @@ &main_gpio6 {
};
&wkup_gpio0 {
- status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_rpi_header_gpio0_pins_default>;
};
&wkup_gpio1 {
@@ -271,6 +325,20 @@ exp1: gpio@21 {
};
};
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
&main_sdhci0 {
/* Unused */
status = "disabled";
--
2.36.1
Hi Sinthu,
On 16/03/23 17:11, Sinthu Raja wrote:
> From: Sinthu Raja <[email protected]>
>
> Add pinmux required to bring out the i2c and gpios on 40-pin RPi
> expansion header on the AM68 SK board.
>
> Signed-off-by: Sinthu Raja <[email protected]>
> ---
>
> No Changes in V3.
>
It looks like you missed to carry the tested tag from Rahul on V2,
was that intentional?
https://lore.kernel.org/all/20230125200427.2bqlpym5tzz43yqq@uda0490373/
Thanks and Regards,
Vaishnav
> .../boot/dts/ti/k3-am68-sk-base-board.dts | 70 ++++++++++++++++++-
> 1 file changed, 69 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> index 27a43a8ecffd..118308cfdd75 100644
> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> @@ -173,6 +173,32 @@ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
> J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
> >;
> };
> +
> + main_i2c4_pins_default: main-i2c4-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 7) /* (AF28) MCAN13_RX.I2C4_SDA */
> + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 7) /* (AD25) MCAN14_TX.I2C4_SCL */
> + >;
> + };
> +
> + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
> + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
> + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
> + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
> + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
> + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
> + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
> + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
> + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
> + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
> + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
> + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
> + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
> + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
> + >;
> + };
> };
>
> &wkup_pmx0 {
> @@ -214,12 +240,39 @@ J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
> >;
> };
>
> + mcu_i2c0_pins_default: mcu-i2c0-pins-default {
> + pinctrl-single,pins = <
> + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /*(H24) WKUP_GPIO0_63.MCU_I2C0_SCL*/
> + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /*(H27) WKUP_GPIO0_64.MCU_I2C0_SDA*/
> + >;
> + };
> +
> mcu_i2c1_pins_default: mcu-i2c1-pins-default {
> pinctrl-single,pins = <
> J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
> J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
> >;
> };
> +
> + mcu_rpi_header_gpio0_pins_default: mcu-rpi-header-gpio0-pins-default {
> + pinctrl-single,pins = <
> + J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
> + J721S2_WKUP_IOPAD(0x190, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
> + J721S2_WKUP_IOPAD(0x0c4, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
> + J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
> + J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
> + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
> + J721S2_WKUP_IOPAD(0x120, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
> + J721S2_WKUP_IOPAD(0x17c, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
> + J721S2_WKUP_IOPAD(0x184, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
> + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
> + >;
> + };
> +};
> +
> +&main_gpio0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&rpi_header_gpio0_pins_default>;
> };
>
> &main_gpio2 {
> @@ -235,7 +288,8 @@ &main_gpio6 {
> };
>
> &wkup_gpio0 {
> - status = "disabled";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_rpi_header_gpio0_pins_default>;
> };
>
> &wkup_gpio1 {
> @@ -271,6 +325,20 @@ exp1: gpio@21 {
> };
> };
>
> +&main_i2c4 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c4_pins_default>;
> + clock-frequency = <400000>;
> +};
> +
> +&mcu_i2c0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_i2c0_pins_default>;
> + clock-frequency = <400000>;
> +};
> +
> &main_sdhci0 {
> /* Unused */
> status = "disabled";
--
Regards,
Vaishnav
Hi Sinthu,
On 16/03/23 17:11, Sinthu Raja wrote:
> From: Sinthu Raja <[email protected]>
>
> The size of wkup domain I/O PADCONFIG register set is incorrect for J721S2.
> Therefore, update the PADCONFIG total offset size to the correct value for
> J721S22 SoC.
>
> Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
> Signed-off-by: Sinthu Raja <[email protected]>
> ---
>
> Changes in V3:
> - Added Fix tag
>
> Changes in V2:
> - Update commit description.
> - Update the offset value to 0x194 because 0x190 is the last register of the
> IO PADCONFIG register set.
>
The existing PADCONFIG register region descriptions in the pinctrl nodes seems
to be incorrect for j721s2-main and j721s2-mcu-wakeup due to non-addressable
holes in the region which causes bus aborts when the registers are read and
causes system crash if we read something like,
/sys/kernel/debug/pinctrl/4301c000.pinctrl-pinctrl-single/pins
This is what I saw from inspection of the datasheet:
* WKUP_PADCONFIG13, WKUP_PADCONFIG25 missing in WKUP_PADCONFIG region
* MAIN_PADCONFIG 64-68 missing in MAIN_PADCONFIG region
I have verified that your patch does not introduce new issues, but since it is a
Fix patch, I will defer the decision to the maintainers on whether we should
split the nodes to avoid non-addressable regions and fix it completely here or
later do a fix for the split.
Thanks and Regards,
Vaishnav
> arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 0af242aa9816..b10f1e8b98e6 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -50,7 +50,7 @@ mcu_ram: sram@41c00000 {
> wkup_pmx0: pinctrl@4301c000 {
> compatible = "pinctrl-single";
> /* Proxy 0 addressing */
> - reg = <0x00 0x4301c000 0x00 0x178>;
> + reg = <0x00 0x4301c000 0x00 0x194>;
> #pinctrl-cells = <1>;
> pinctrl-single,register-width = <32>;
> pinctrl-single,function-mask = <0xffffffff>;
--
Regards,
Vaishnav
On 16:48-20230328, Vaishnav Achath wrote:
> Hi Sinthu,
>
> On 16/03/23 17:11, Sinthu Raja wrote:
> > From: Sinthu Raja <[email protected]>
> >
> > The size of wkup domain I/O PADCONFIG register set is incorrect for J721S2.
> > Therefore, update the PADCONFIG total offset size to the correct value for
> > J721S22 SoC.
> >
> > Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
> > Signed-off-by: Sinthu Raja <[email protected]>
> > ---
> >
> > Changes in V3:
> > - Added Fix tag
> >
> > Changes in V2:
> > - Update commit description.
> > - Update the offset value to 0x194 because 0x190 is the last register of the
> > IO PADCONFIG register set.
> >
>
> The existing PADCONFIG register region descriptions in the pinctrl nodes seems
> to be incorrect for j721s2-main and j721s2-mcu-wakeup due to non-addressable
> holes in the region which causes bus aborts when the registers are read and
> causes system crash if we read something like,
> /sys/kernel/debug/pinctrl/4301c000.pinctrl-pinctrl-single/pins
>
> This is what I saw from inspection of the datasheet:
>
> * WKUP_PADCONFIG13, WKUP_PADCONFIG25 missing in WKUP_PADCONFIG region
> * MAIN_PADCONFIG 64-68 missing in MAIN_PADCONFIG region
>
> I have verified that your patch does not introduce new issues, but since it is a
> Fix patch, I will defer the decision to the maintainers on whether we should
> split the nodes to avoid non-addressable regions and fix it completely here or
> later do a fix for the split.
Do a single fix-up please.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Hi Sinthu,
On 28/03/23 16:30, Vaishnav Achath wrote:
> Hi Sinthu,
>
> On 16/03/23 17:11, Sinthu Raja wrote:
>> From: Sinthu Raja <[email protected]>
>>
>> Add pinmux required to bring out the i2c and gpios on 40-pin RPi
>> expansion header on the AM68 SK board.
>>
>> Signed-off-by: Sinthu Raja <[email protected]>
>> ---
>>
>> No Changes in V3.
>>
>
> It looks like you missed to carry the tested tag from Rahul on V2,
> was that intentional?
>
> https://lore.kernel.org/all/20230125200427.2bqlpym5tzz43yqq@uda0490373/
>
> Thanks and Regards,
> Vaishnav
>
>> .../boot/dts/ti/k3-am68-sk-base-board.dts | 70 ++++++++++++++++++-
>> 1 file changed, 69 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
>> index 27a43a8ecffd..118308cfdd75 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
>> @@ -173,6 +173,32 @@ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
>> J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
>> >;
>> };
>> +
>> + main_i2c4_pins_default: main-i2c4-pins-default {
>> + pinctrl-single,pins = <
>> + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 7) /* (AF28) MCAN13_RX.I2C4_SDA */
>> + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 7) /* (AD25) MCAN14_TX.I2C4_SCL */
While reviewing these changes with Udit, we found that these settings for I2C is
wrong as per the datasheet(or sysconfig), for these PADs the mux mode 7 is GPIO
and mode 8 is I2C, can you please check and correct this.
Thanks and Regards,
Vaishnav
>> + >;
>> + };
>> +
>> + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
>> + pinctrl-single,pins = <
>> + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
>> + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
>> + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
>> + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
>> + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
>> + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
>> + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
>> + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
>> + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
>> + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
>> + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
>> + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
>> + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
>> + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
>> + >;
>> + };
>> };
>>
>> &wkup_pmx0 {
>> @@ -214,12 +240,39 @@ J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
>> >;
>> };
>>
>> + mcu_i2c0_pins_default: mcu-i2c0-pins-default {
>> + pinctrl-single,pins = <
>> + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /*(H24) WKUP_GPIO0_63.MCU_I2C0_SCL*/
>> + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /*(H27) WKUP_GPIO0_64.MCU_I2C0_SDA*/
>> + >;
>> + };
>> +
>> mcu_i2c1_pins_default: mcu-i2c1-pins-default {
>> pinctrl-single,pins = <
>> J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
>> J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
>> >;
>> };
>> +
>> + mcu_rpi_header_gpio0_pins_default: mcu-rpi-header-gpio0-pins-default {
>> + pinctrl-single,pins = <
>> + J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
>> + J721S2_WKUP_IOPAD(0x190, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
>> + J721S2_WKUP_IOPAD(0x0c4, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
>> + J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
>> + J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
>> + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
>> + J721S2_WKUP_IOPAD(0x120, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
>> + J721S2_WKUP_IOPAD(0x17c, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
>> + J721S2_WKUP_IOPAD(0x184, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
>> + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
>> + >;
>> + };
>> +};
>> +
>> +&main_gpio0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&rpi_header_gpio0_pins_default>;
>> };
>>
>> &main_gpio2 {
>> @@ -235,7 +288,8 @@ &main_gpio6 {
>> };
>>
>> &wkup_gpio0 {
>> - status = "disabled";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcu_rpi_header_gpio0_pins_default>;
>> };
>>
>> &wkup_gpio1 {
>> @@ -271,6 +325,20 @@ exp1: gpio@21 {
>> };
>> };
>>
>> +&main_i2c4 {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&main_i2c4_pins_default>;
>> + clock-frequency = <400000>;
>> +};
>> +
>> +&mcu_i2c0 {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcu_i2c0_pins_default>;
>> + clock-frequency = <400000>;
>> +};
>> +
>> &main_sdhci0 {
>> /* Unused */
>> status = "disabled";
>
--
Regards,
Vaishnav