2023-04-11 06:51:20

by Changhuang Liang

[permalink] [raw]
Subject: [PATCH v1 0/7] Add JH7110 DPHY PMU support

This patchset adds mipi dphy power domain driver for the StarFive JH7110
SoC. It is used to turn on dphy power switch. The series has been tested
on the VisionFive 2 board.

This patchset should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/[email protected]/

Changhuang Liang (7):
dt-bindings: power: Constrain properties for JH7110 PMU
soc: starfive: Replace SOC_STARFIVE with ARCH_SATRFIVE
soc: starfive: Modify ioremap to regmap
soc: starfive: Add pmu type operation
soc: starfive: Use call back to parse device tree resources
soc: starfive: Add dphy pmu support
riscv: dts: starfive: Add dphy rx pmu node

.../bindings/power/starfive,jh7110-pmu.yaml | 14 +-
MAINTAINERS | 1 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +
drivers/soc/starfive/Kconfig | 4 +-
drivers/soc/starfive/jh71xx_pmu.c | 213 ++++++++++++++----
.../dt-bindings/power/starfive,jh7110-pmu.h | 3 +
6 files changed, 187 insertions(+), 53 deletions(-)


base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
prerequisite-patch-id: 7ff6864ac74df5392c8646fe756cadd584fcc813
prerequisite-patch-id: 284b5d1b95c6d68bca08db1e82ed14930c98b777
--
2.25.1


2023-04-11 06:51:35

by Changhuang Liang

[permalink] [raw]
Subject: [PATCH v1 4/7] soc: starfive: Add pmu type operation

Add pmu type, make a distinction between different PMU.

Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/soc/starfive/jh71xx_pmu.c | 55 ++++++++++++++++++++++---------
1 file changed, 39 insertions(+), 16 deletions(-)

diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 306218c83691..98f6849d61de 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -45,6 +45,12 @@
*/
#define JH71XX_PMU_TIMEOUT_US 100

+/* pmu type */
+enum pmu_type {
+ JH71XX_PMU_GENERAL,
+ JH71XX_PMU_DPHY,
+};
+
struct jh71xx_domain_info {
const char * const name;
unsigned int flags;
@@ -54,6 +60,7 @@ struct jh71xx_domain_info {
struct jh71xx_pmu_match_data {
const struct jh71xx_domain_info *domain_info;
int num_domains;
+ u8 pmu_type;
};

struct jh71xx_pmu {
@@ -75,19 +82,23 @@ struct jh71xx_pmu_dev {
static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
+ unsigned int offset = 0;
unsigned int val;

if (!mask)
return -EINVAL;

- regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val);
+ if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL)
+ offset = JH71XX_PMU_CURR_POWER_MODE;
+
+ regmap_read(pmu->base, offset, &val);

*is_on = val & mask;

return 0;
}

-static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+static int jh71xx_pmu_general_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
unsigned long flags;
@@ -95,22 +106,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
u32 mode;
u32 encourage_lo;
u32 encourage_hi;
- bool is_on;
int ret;

- ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
- if (ret) {
- dev_dbg(pmu->dev, "unable to get current state for %s\n",
- pmd->genpd.name);
- return ret;
- }
-
- if (is_on == on) {
- dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
- pmd->genpd.name, on ? "en" : "dis");
- return 0;
- }
-
spin_lock_irqsave(&pmu->lock, flags);

/*
@@ -169,6 +166,31 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}

+static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ bool is_on;
+ int ret = 0;
+
+ ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
+ if (ret) {
+ dev_dbg(pmu->dev, "unable to get current state for %s\n",
+ pmd->genpd.name);
+ return ret;
+ }
+
+ if (is_on == on) {
+ dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
+ pmd->genpd.name, on ? "en" : "dis");
+ return 0;
+ }
+
+ if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL)
+ ret = jh71xx_pmu_general_set_state(pmd, mask, on);
+
+ return ret;
+}
+
static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
{
struct jh71xx_pmu_dev *pmd = container_of(genpd,
@@ -360,6 +382,7 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
static const struct jh71xx_pmu_match_data jh7110_pmu = {
.num_domains = ARRAY_SIZE(jh7110_power_domains),
.domain_info = jh7110_power_domains,
+ .pmu_type = JH71XX_PMU_GENERAL,
};

static const struct of_device_id jh71xx_pmu_of_match[] = {
--
2.25.1

2023-04-11 06:51:54

by Changhuang Liang

[permalink] [raw]
Subject: [PATCH v1 7/7] riscv: dts: starfive: Add dphy rx pmu node

Add dphy rx pmu node to configure dphy power.

Signed-off-by: Changhuang Liang <[email protected]>
Reviewed-by: Walker Chen <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index f271c3184d3a..a82374afcc91 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -499,6 +499,11 @@ aoncrg: clock-controller@17000000 {
aon_syscon: syscon@17010000 {
compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
reg = <0x0 0x17010000 0x0 0x1000>;
+
+ pwrc_dphy: power-controller {
+ compatible = "starfive,jh7110-pmu-dphy";
+ #power-domain-cells = <1>;
+ };
};

aongpio: pinctrl@17020000 {
--
2.25.1

2023-04-11 20:12:02

by Conor Dooley

[permalink] [raw]
Subject: Re: [PATCH v1 0/7] Add JH7110 DPHY PMU support

Hey Walker,

On Mon, Apr 10, 2023 at 11:47:36PM -0700, Changhuang Liang wrote:
> This patchset adds mipi dphy power domain driver for the StarFive JH7110
> SoC. It is used to turn on dphy power switch. The series has been tested
> on the VisionFive 2 board.

Could you review the driver changes here please.

Thanks,
Conor.

>
> This patchset should be applied after the patchset [1]:
> [1] https://lore.kernel.org/all/[email protected]/
>
> Changhuang Liang (7):
> dt-bindings: power: Constrain properties for JH7110 PMU
> soc: starfive: Replace SOC_STARFIVE with ARCH_SATRFIVE
> soc: starfive: Modify ioremap to regmap
> soc: starfive: Add pmu type operation
> soc: starfive: Use call back to parse device tree resources
> soc: starfive: Add dphy pmu support
> riscv: dts: starfive: Add dphy rx pmu node
>
> .../bindings/power/starfive,jh7110-pmu.yaml | 14 +-
> MAINTAINERS | 1 +
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +
> drivers/soc/starfive/Kconfig | 4 +-
> drivers/soc/starfive/jh71xx_pmu.c | 213 ++++++++++++++----
> .../dt-bindings/power/starfive,jh7110-pmu.h | 3 +
> 6 files changed, 187 insertions(+), 53 deletions(-)
>
>
> base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
> prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
> prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
> prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
> prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
> prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
> prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
> prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
> prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
> prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
> prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
> prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
> prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
> prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
> prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
> prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
> prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
> prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
> prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
> prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
> prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
> prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
> prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
> prerequisite-patch-id: 7ff6864ac74df5392c8646fe756cadd584fcc813
> prerequisite-patch-id: 284b5d1b95c6d68bca08db1e82ed14930c98b777
> --
> 2.25.1


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2023-04-11 20:53:34

by Conor Dooley

[permalink] [raw]
Subject: Re: [PATCH v1 4/7] soc: starfive: Add pmu type operation

Hey Changhuang Liang,

On Mon, Apr 10, 2023 at 11:47:40PM -0700, Changhuang Liang wrote:
> Add pmu type, make a distinction between different PMU.

Please write more detailed commit messages, thanks.

>
> Signed-off-by: Changhuang Liang <[email protected]>
> ---
> drivers/soc/starfive/jh71xx_pmu.c | 55 ++++++++++++++++++++++---------
> 1 file changed, 39 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
> index 306218c83691..98f6849d61de 100644
> --- a/drivers/soc/starfive/jh71xx_pmu.c
> +++ b/drivers/soc/starfive/jh71xx_pmu.c
> @@ -45,6 +45,12 @@
> */
> #define JH71XX_PMU_TIMEOUT_US 100
>
> +/* pmu type */

Delete this comment, it's obvious.

> +enum pmu_type {
> + JH71XX_PMU_GENERAL,

I'm really not sold on GENERAL as a name.
Why not name these after the compatibles?

> + JH71XX_PMU_DPHY,
> +};
> +
> struct jh71xx_domain_info {
> const char * const name;
> unsigned int flags;
> @@ -54,6 +60,7 @@ struct jh71xx_domain_info {
> struct jh71xx_pmu_match_data {
> const struct jh71xx_domain_info *domain_info;
> int num_domains;
> + u8 pmu_type;

This is an enum, not a u8?

Thanks,
Conor.


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2023-04-12 06:52:48

by Changhuang Liang

[permalink] [raw]
Subject: Re: [PATCH v1 4/7] soc: starfive: Add pmu type operation



On 2023/4/12 4:52, Conor Dooley wrote:
> Hey Changhuang Liang,
>
> On Mon, Apr 10, 2023 at 11:47:40PM -0700, Changhuang Liang wrote:
>> Add pmu type, make a distinction between different PMU.
>
> Please write more detailed commit messages, thanks.
>

OK, will write more detail for it.

>>
>> Signed-off-by: Changhuang Liang <[email protected]>
>> ---
>> drivers/soc/starfive/jh71xx_pmu.c | 55 ++++++++++++++++++++++---------
>> 1 file changed, 39 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
>> index 306218c83691..98f6849d61de 100644
>> --- a/drivers/soc/starfive/jh71xx_pmu.c
>> +++ b/drivers/soc/starfive/jh71xx_pmu.c
>> @@ -45,6 +45,12 @@
>> */
>> #define JH71XX_PMU_TIMEOUT_US 100
>>
>> +/* pmu type */
>
> Delete this comment, it's obvious.
>

OK, will delete this line.

>> +enum pmu_type {
>> + JH71XX_PMU_GENERAL,
>
> I'm really not sold on GENERAL as a name.
> Why not name these after the compatibles?
>

OK, will change to "JH71XX_PMU".

>> + JH71XX_PMU_DPHY,
>> +};
>> +
>> struct jh71xx_domain_info {
>> const char * const name;
>> unsigned int flags;
>> @@ -54,6 +60,7 @@ struct jh71xx_domain_info {
>> struct jh71xx_pmu_match_data {
>> const struct jh71xx_domain_info *domain_info;
>> int num_domains;
>> + u8 pmu_type;
>
> This is an enum, not a u8?
>

OK, will fix it.

> Thanks,
> Conor.
>