This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
The patch has been tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1] and [2]:
[1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
[2] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
This patchset is base on v6.3-rc4
patch 1 is usb phy dt-binding document.
patch 2 is Pcie PHY dt-binding document.
patch 3 is USB 2.0 PHY driver.
patch 4 is PCIe PHY driver.
patch 5 is usb dt-binding document.
patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
patch 7 is USB device tree configuration.
previous version
---
version 1 patchset are split to different kernel organization. It is
incorrect. But they were sent, and Emil sent comments. I think I should
reserve them in cover-letter. To read the change records and previous version,
please start with version 2.
v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v4: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
changes
v5:
1. (patch 1) set correct model name and commit title.
2. (patch 2) change to '-item' in syscon property. change commit title.
3. (patch 5)
- change to '-item' in syscon configure.
- change commit title and doc title.
4. (patch 6)
- add clk and phy deinit function
- add clk deinit function if phy init failed.
- coding style changes and other format changes.
v4:
1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
3. (patch 3)
- split PCIe PHY driver to patch 4.
- replace dr_mode to phy mode in jh7110_usb2_phy.
4. (patch 4)
- Makefile and Kconfig sorted by alphabet sequence.
- Add PCIe PHY stg and syscon PHY connection configuration
for USB 3.0.
5. (patch 5)
- commit message changed.
- merge wrapper dts node and cdns3 node in example.
- Add interrupts, reg, phy and dr_mode in property.
- Add reset-name in property example.
6. (patch 6)
- For dts node is merged, Using platform_device_alloc and
platform_device_add to generate cadence sub device.
- IOMEM and IRQ resource are passed to Cadence sub device.
- Add PHY ops process for PHY dts setting can not be passed to
Cadence USB driver.
- remove the stg and sys USB 3.0 PHY configuration.
- Change the suspend clock reset and clock enable sequence.
- Get all reset and clock resources before enable them in
cdns_clk_rst_init.
- commit message changed.
7. (patch 7)
- merge wrapper dts node and cdns3 node in usb dts.
- move the stg and sys USB 3.0 PHY confiuration to
PCIe PHY dts node.
- commit message changed.
- Add reset-names dts.
v3:
1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
USB PHY codes are moved to patch 3 and patch 4.
2. (patch 5)
- USB wrapper module dts document is moved to usb directory.
- Remove the 'dr_mode' and 'starfive,usb2-only' setting.
- Some dts format changes. dts binding check pass.
3. (patch 6)
- Remove the PHY codes.
- Search 'dr_mode' and phy setting from Cadence subnode.
4. (patch 7)
- Add USB PHY dts configurion.
- 'dr_mode' is moved to Cadence controller submode.
v2:
1. (patch 5) dt-binding changes. The document example is the same as dts config.
2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
3. (patch 7) dts nodes sorted by the address after @
Minda Chen (7):
dt-bindings: phy: Add StarFive JH7110 USB PHY
dt-bindings: phy: Add StarFive JH7110 PCIe PHY
phy: starfive: Add JH7110 USB 2.0 PHY driver
phy: starfive: Add JH7110 PCIE 2.0 PHY driver
dt-bindings: usb: Add StarFive JH7110 USB controller
usb: cdns3: Add StarFive JH7110 USB driver
riscv: dts: starfive: Add USB dts configuration for JH7110
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
.../bindings/usb/starfive,jh7110-usb.yaml | 131 ++++++
MAINTAINERS | 14 +
.../jh7110-starfive-visionfive-2.dtsi | 7 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
drivers/phy/starfive/Kconfig | 22 +
drivers/phy/starfive/Makefile | 2 +
drivers/phy/starfive/phy-jh7110-pcie.c | 202 +++++++++
drivers/phy/starfive/phy-jh7110-usb.c | 162 ++++++++
drivers/usb/cdns3/Kconfig | 11 +
drivers/usb/cdns3/Makefile | 1 +
drivers/usb/cdns3/cdns3-starfive.c | 390 ++++++++++++++++++
drivers/usb/cdns3/core.h | 3 +
14 files changed, 1097 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
--
2.17.1
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
new file mode 100644
index 000000000000..2e83a6164cd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PCIe 2.0 PHY
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ starfive,sys-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
+ description:
+ The phandle to System Register Controller syscon node and the PHY connect offset
+ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
+ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10210000 0x10000>;
+ #phy-cells = <0>;
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
+ };
--
2.17.1
On Thu, 20 Apr 2023 19:00:47 +0800, Minda Chen wrote:
> Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
> PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
>
> Signed-off-by: Minda Chen <[email protected]>
> Reviewed-by: Hal Feng <[email protected]>
> ---
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>
Reviewed-by: Rob Herring <[email protected]>