Add memory-region property to the tegra186-bpmp binding to support
DRAM MRQ GSCs.
Co-developed-by: Stefan Kristiansson <[email protected]>
Signed-off-by: Stefan Kristiansson <[email protected]>
Signed-off-by: Peter De Schrijver <[email protected]>
---
.../firmware/nvidia,tegra186-bpmp.yaml | 37 +++++++++++++++++--
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
index 833c07f1685c..f3e02c9d090d 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -57,8 +57,11 @@ description: |
"#address-cells" or "#size-cells" property.
The shared memory area for the IPC TX and RX between CPU and BPMP are
- predefined and work on top of sysram, which is an SRAM inside the
- chip. See ".../sram/sram.yaml" for the bindings.
+ predefined and work on top of either sysram, which is an SRAM inside the
+ chip, or in normal SDRAM.
+ See ".../sram/sram.yaml" for the bindings for the SRAM case.
+ See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
+ the SDRAM case.
properties:
compatible:
@@ -81,6 +84,11 @@ properties:
minItems: 2
maxItems: 2
+ memory-region:
+ description: phandle to reserved memory region used for IPC between
+ CPU-NS and BPMP.
+ maxItems: 1
+
"#clock-cells":
const: 1
@@ -115,10 +123,15 @@ properties:
additionalProperties: false
+oneOf:
+ - required:
+ - memory-region
+ - required:
+ - shmem
+
required:
- compatible
- mboxes
- - shmem
- "#clock-cells"
- "#power-domain-cells"
- "#reset-cells"
@@ -184,3 +197,21 @@ examples:
#thermal-sensor-cells = <1>;
};
};
+
+ - |
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
+ mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ memory-region = <&dram_cpu_bpmp_mail>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.34.1
On Thu, May 11, 2023 at 04:20:50PM +0300, Peter De Schrijver wrote:
> + bpmp {
> + compatible = "nvidia,tegra186-bpmp";
> + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
> + interconnect-names = "read", "write", "dma-mem", "dma-write";
> + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
> + TEGRA_HSP_DB_MASTER_BPMP>;
FWIW, this fits on one line - although you've just copy-pasted what was
already there in the other example.
Reviewed-by: Conor Dooley <[email protected]>
On 11/05/2023 15:20, Peter De Schrijver wrote:
> Add memory-region property to the tegra186-bpmp binding to support
> DRAM MRQ GSCs.
Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).
>
> Co-developed-by: Stefan Kristiansson <[email protected]>
> Signed-off-by: Stefan Kristiansson <[email protected]>
> Signed-off-by: Peter De Schrijver <[email protected]>
> ---
> .../firmware/nvidia,tegra186-bpmp.yaml | 37 +++++++++++++++++--
> 1 file changed, 34 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> index 833c07f1685c..f3e02c9d090d 100644
> --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> @@ -57,8 +57,11 @@ description: |
> "#address-cells" or "#size-cells" property.
>
> The shared memory area for the IPC TX and RX between CPU and BPMP are
> - predefined and work on top of sysram, which is an SRAM inside the
> - chip. See ".../sram/sram.yaml" for the bindings.
> + predefined and work on top of either sysram, which is an SRAM inside the
> + chip, or in normal SDRAM.
> + See ".../sram/sram.yaml" for the bindings for the SRAM case.
> + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
> + the SDRAM case.
>
> properties:
> compatible:
> @@ -81,6 +84,11 @@ properties:
> minItems: 2
> maxItems: 2
>
> + memory-region:
> + description: phandle to reserved memory region used for IPC between
> + CPU-NS and BPMP.
> + maxItems: 1
> +
> "#clock-cells":
> const: 1
>
> @@ -115,10 +123,15 @@ properties:
>
> additionalProperties: false
>
> +oneOf:
> + - required:
> + - memory-region
> + - required:
> + - shmem
> +
> required:
> - compatible
> - mboxes
> - - shmem
> - "#clock-cells"
> - "#power-domain-cells"
> - "#reset-cells"
> @@ -184,3 +197,21 @@ examples:
> #thermal-sensor-cells = <1>;
> };
> };
> +
> + - |
> + #include <dt-bindings/mailbox/tegra186-hsp.h>
> +
> + bpmp {
> + compatible = "nvidia,tegra186-bpmp";
> + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
> + interconnect-names = "read", "write", "dma-mem", "dma-write";
> + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
> + TEGRA_HSP_DB_MASTER_BPMP>;
> + memory-region = <&dram_cpu_bpmp_mail>;
I am not sure if difference with one property justifies new example...
Best regards,
Krzysztof
On Fri, May 12, 2023 at 08:45:22AM +0200, Krzysztof Kozlowski wrote:
> On 11/05/2023 15:20, Peter De Schrijver wrote:
> > Add memory-region property to the tegra186-bpmp binding to support
> > DRAM MRQ GSCs.
>
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
>
> >
> > Co-developed-by: Stefan Kristiansson <[email protected]>
> > Signed-off-by: Stefan Kristiansson <[email protected]>
> > Signed-off-by: Peter De Schrijver <[email protected]>
> > ---
> > .../firmware/nvidia,tegra186-bpmp.yaml | 37 +++++++++++++++++--
> > 1 file changed, 34 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> > index 833c07f1685c..f3e02c9d090d 100644
> > --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> > +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
> > @@ -57,8 +57,11 @@ description: |
> > "#address-cells" or "#size-cells" property.
> >
> > The shared memory area for the IPC TX and RX between CPU and BPMP are
> > - predefined and work on top of sysram, which is an SRAM inside the
> > - chip. See ".../sram/sram.yaml" for the bindings.
> > + predefined and work on top of either sysram, which is an SRAM inside the
> > + chip, or in normal SDRAM.
> > + See ".../sram/sram.yaml" for the bindings for the SRAM case.
> > + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
> > + the SDRAM case.
> >
> > properties:
> > compatible:
> > @@ -81,6 +84,11 @@ properties:
> > minItems: 2
> > maxItems: 2
> >
> > + memory-region:
> > + description: phandle to reserved memory region used for IPC between
> > + CPU-NS and BPMP.
> > + maxItems: 1
> > +
> > "#clock-cells":
> > const: 1
> >
> > @@ -115,10 +123,15 @@ properties:
> >
> > additionalProperties: false
> >
> > +oneOf:
> > + - required:
> > + - memory-region
> > + - required:
> > + - shmem
> > +
> > required:
> > - compatible
> > - mboxes
> > - - shmem
> > - "#clock-cells"
> > - "#power-domain-cells"
> > - "#reset-cells"
> > @@ -184,3 +197,21 @@ examples:
> > #thermal-sensor-cells = <1>;
> > };
> > };
> > +
> > + - |
> > + #include <dt-bindings/mailbox/tegra186-hsp.h>
> > +
> > + bpmp {
> > + compatible = "nvidia,tegra186-bpmp";
> > + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
> > + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
> > + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
> > + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
> > + interconnect-names = "read", "write", "dma-mem", "dma-write";
> > + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
> > + TEGRA_HSP_DB_MASTER_BPMP>;
> > + memory-region = <&dram_cpu_bpmp_mail>;
>
> I am not sure if difference with one property justifies new example...
It makes sense in this case, in my opinion, because both memory-region
and shmem properties are mutually exclusive, so this is a good way to
make sure both validation paths are tested.
Thierry