Add the tdm controller node and pins configuration of tdm for the
StarFive JH7110 SoC.
Signed-off-by: Walker Chen <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++
2 files changed, 61 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 1155b97b593d..19b5954ee72d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -214,6 +214,40 @@
slew-rate = <0>;
};
};
+
+ tdm0_pins: tdm0-pins {
+ tdm0-pins-tx {
+ pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ tdm0-pins-rx {
+ pinmux = <GPIOMUX(61, GPOUT_HIGH,
+ GPOEN_DISABLE,
+ GPI_SYS_TDM_RXD)>;
+ input-enable;
+ };
+
+ tdm0-pins-sync {
+ pinmux = <GPIOMUX(63, GPOUT_HIGH,
+ GPOEN_DISABLE,
+ GPI_SYS_TDM_SYNC)>;
+ input-enable;
+ };
+
+ tdm0-pins-pcmclk {
+ pinmux = <GPIOMUX(38, GPOUT_HIGH,
+ GPOEN_DISABLE,
+ GPI_SYS_TDM_CLK)>;
+ input-enable;
+ };
+ };
};
&uart0 {
@@ -221,3 +255,9 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&tdm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&tdm0_pins>;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 866313570a7e..cfda6fb0d91b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -366,6 +366,27 @@
status = "disabled";
};
+ tdm: tdm@10090000 {
+ compatible = "starfive,jh7110-tdm";
+ reg = <0x0 0x10090000 0x0 0x1000>;
+ clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
+ <&syscrg JH7110_SYSCLK_TDM_APB>,
+ <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
+ <&syscrg JH7110_SYSCLK_TDM_TDM>,
+ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
+ <&tdm_ext>;
+ clock-names = "tdm_ahb", "tdm_apb",
+ "tdm_internal", "tdm",
+ "mclk_inner", "tdm_ext";
+ resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
+ <&syscrg JH7110_SYSRST_TDM_APB>,
+ <&syscrg JH7110_SYSRST_TDM_CORE>;
+ dmas = <&dma 20>, <&dma 21>;
+ dma-names = "rx","tx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.17.1
On 2023/5/11 17:15, Walker Chen wrote:
> Add the tdm controller node and pins configuration of tdm for the
> StarFive JH7110 SoC.
>
> Signed-off-by: Walker Chen <[email protected]>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 1155b97b593d..19b5954ee72d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -214,6 +214,40 @@
> slew-rate = <0>;
> };
> };
> +
> + tdm0_pins: tdm0-pins {
> + tdm0-pins-tx {
> + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + tdm0-pins-rx {
> + pinmux = <GPIOMUX(61, GPOUT_HIGH,
> + GPOEN_DISABLE,
> + GPI_SYS_TDM_RXD)>;
> + input-enable;
> + };
> +
> + tdm0-pins-sync {
> + pinmux = <GPIOMUX(63, GPOUT_HIGH,
> + GPOEN_DISABLE,
> + GPI_SYS_TDM_SYNC)>;
> + input-enable;
> + };
> +
> + tdm0-pins-pcmclk {
> + pinmux = <GPIOMUX(38, GPOUT_HIGH,
> + GPOEN_DISABLE,
> + GPI_SYS_TDM_CLK)>;
> + input-enable;
> + };
> + };
> };
>
> &uart0 {
> @@ -221,3 +255,9 @@
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&tdm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&tdm0_pins>;
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 866313570a7e..cfda6fb0d91b 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -366,6 +366,27 @@
> status = "disabled";
> };
>
> + tdm: tdm@10090000 {
> + compatible = "starfive,jh7110-tdm";
> + reg = <0x0 0x10090000 0x0 0x1000>;
> + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
> + <&syscrg JH7110_SYSCLK_TDM_APB>,
> + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
> + <&syscrg JH7110_SYSCLK_TDM_TDM>,
> + <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> + <&tdm_ext>;
> + clock-names = "tdm_ahb", "tdm_apb",
> + "tdm_internal", "tdm",
> + "mclk_inner", "tdm_ext";
> + resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
> + <&syscrg JH7110_SYSRST_TDM_APB>,
> + <&syscrg JH7110_SYSRST_TDM_CORE>;
> + dmas = <&dma 20>, <&dma 21>;
> + dma-names = "rx","tx";
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
Hi Conor / Emil,
Based on our discussion a few days ago, the new version of patch for dts looks like this,
Please help to review and provide your comments if you feel free.
Thank you very much!
Best regards,
Walker
On Mon, May 15, 2023 at 04:44:54PM +0800, Walker Chen wrote:
> Hi Conor / Emil,
>
> Based on our discussion a few days ago, the new version of patch for dts looks like this,
> Please help to review and provide your comments if you feel free.
> On 2023/5/11 17:15, Walker Chen wrote:
It's only been 4 days chief, of which 2 were the weekend, you don't need
to bump it yet! You'd be better off asking one of your co-workers to
review the content, instead of me. I'll happily apply the patch, with
appropriate review, once the dt-binding has been applied by Mark. I do
not have the capacity to review the detail of individual patches adding
peripherals unfortunately.
Getting your co-workers to look at your patches, and doing the same for
theirs, is almost always a good idea for speeding up the process
Thanks for dropping the overlay though,
Conor.
On Mon, May 15, 2023 at 09:58:12AM +0100, Conor Dooley wrote:
> It's only been 4 days chief, of which 2 were the weekend, you don't need
> to bump it yet! You'd be better off asking one of your co-workers to
4 days, 2 of which were the weekend and 4 of which I was on holiday...
On 2023/5/15 16:58, Conor Dooley wrote:
> On Mon, May 15, 2023 at 04:44:54PM +0800, Walker Chen wrote:
>
>> Hi Conor / Emil,
>>
>> Based on our discussion a few days ago, the new version of patch for dts looks like this,
>> Please help to review and provide your comments if you feel free.
>
>> On 2023/5/11 17:15, Walker Chen wrote:
>
> It's only been 4 days chief, of which 2 were the weekend, you don't need
> to bump it yet! You'd be better off asking one of your co-workers to
> review the content, instead of me. I'll happily apply the patch, with
> appropriate review, once the dt-binding has been applied by Mark. I do
> not have the capacity to review the detail of individual patches adding
> peripherals unfortunately.
> Getting your co-workers to look at your patches, and doing the same for
> theirs, is almost always a good idea for speeding up the process
Oh, Conor, perhaps I was too eager to finish the work quickly. Sorry for that!
Maybe I need to ask my co-worker to review firstly as you said.
Best regards,
Walker