2023-06-02 08:55:42

by William Qiu

[permalink] [raw]
Subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Add QSPI clock operation in device probe.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..21788472c7fb 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -63,6 +63,8 @@ struct cqspi_st {
struct platform_device *pdev;
struct spi_master *master;
struct clk *clk;
+ struct clk_bulk_data *clks;
+ unsigned int num_clks;
unsigned int sclk;

void __iomem *iobase;
@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev)
}

if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+ cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
+ if (cqspi->num_clks < 0) {
+ dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks);
+ return -EINVAL;
+ }
+
+ ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
+ if (ret)
+ dev_err(dev, "Cannot enable clock clks\n");
+
rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
if (IS_ERR(rstc_ref)) {
ret = PTR_ERR(rstc_ref);
@@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev)

clk_disable_unprepare(cqspi->clk);

+ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
@@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev)

clk_disable_unprepare(cqspi->clk);

+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks);
+
return ret;
}

@@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev)
struct spi_master *master = dev_get_drvdata(dev);

clk_prepare_enable(cqspi->clk);
+ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
+ clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
cqspi_wait_idle(cqspi);
cqspi_controller_init(cqspi);

--
2.34.1



2023-06-02 12:38:57

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI

Hi William,

kernel test robot noticed the following build warnings:

[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.4-rc4 next-20230602]
[cannot apply to robh/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/[email protected]/config)
compiler: powerpc-linux-gcc (GCC) 12.3.0
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +1873 drivers/spi/spi-cadence-quadspi.c

1865
1866 static int cqspi_resume(struct device *dev)
1867 {
1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1869 struct spi_master *master = dev_get_drvdata(dev);
1870
1871 clk_prepare_enable(cqspi->clk);
1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
1874 cqspi_wait_idle(cqspi);
1875 cqspi_controller_init(cqspi);
1876
1877 cqspi->current_cs = -1;
1878 cqspi->sclk = 0;
1879
1880 return spi_master_resume(master);
1881 }
1882

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

2023-06-06 03:56:57

by William Qiu

[permalink] [raw]
Subject: Re: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI



On 2023/6/2 20:33, kernel test robot wrote:
> Hi William,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on broonie-spi/for-next]
> [also build test WARNING on linus/master v6.4-rc4 next-20230602]
> [cannot apply to robh/for-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
> patch link: https://lore.kernel.org/r/20230602084925.215411-3-william.qiu%40starfivetech.com
> patch subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
> config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20230602/[email protected]/config)
> compiler: powerpc-linux-gcc (GCC) 12.3.0
> reproduce (this is a W=1 build):
> mkdir -p ~/bin
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/intel-lab-lkp/linux/commit/6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review William-Qiu/dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFive-JH7110-SoC/20230602-165251
> git checkout 6bbd49e32d407d210b6ea322696cef2e49bf3fa1
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.3.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/spi/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <[email protected]>
> | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
>
> All warnings (new ones prefixed by >>):
>
> drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_resume':
>>> drivers/spi/spi-cadence-quadspi.c:1873:17: warning: ignoring return value of 'clk_bulk_prepare_enable' declared with attribute 'warn_unused_result' [-Wunused-result]
> 1873 | clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
> vim +1873 drivers/spi/spi-cadence-quadspi.c
>
> 1865
> 1866 static int cqspi_resume(struct device *dev)
> 1867 {
> 1868 struct cqspi_st *cqspi = dev_get_drvdata(dev);
> 1869 struct spi_master *master = dev_get_drvdata(dev);
> 1870
> 1871 clk_prepare_enable(cqspi->clk);
> 1872 if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi"))
>> 1873 clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks);
> 1874 cqspi_wait_idle(cqspi);
> 1875 cqspi_controller_init(cqspi);
> 1876
> 1877 cqspi->current_cs = -1;
> 1878 cqspi->sclk = 0;
> 1879
> 1880 return spi_master_resume(master);
> 1881 }
> 1882
>

Thanks about that. I'll fix it in next version.

Best Regards,
William