This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
The patch has been tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1], [2] and [3]:
[1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
[2] https://patchwork.kernel.org/project/linux-clk/cover/[email protected]
[3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
This patchset is base on v6.4-rc1
patch 1 is usb phy dt-binding document.
patch 2 is Pcie PHY dt-binding document.
patch 3 is USB 2.0 PHY driver.
patch 4 is PCIe PHY driver.
patch 5 is usb dt-binding document.
patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
patch 7 is USB device tree configuration.
previous version
---
version 1 patchset are split to different kernel organization. It is
incorrect. But they were sent, and Emil sent comments. I think I should
reserve them in cover-letter. To read the change records and previous version,
please start with version 2.
v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v4: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
v5: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
changes
v6:
1. (patch 3) remove the platform remove function.
2. (patch 4)
- add switch to pcie mode function.
- remove the redundant init/exit function.
3. (patch 5)
- dts split to wrapper layer and cdns node. The codes are
like v3.
- add cdns3 sub node dts-binding references.
4. (patch 6)
For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
to usb, so USB contain its own registers. So do not merge the dts node.
The codes are like v3.
- remove the cdns3_platform_add function.
- remove phy ops because cdns3 contain all the phy ops.
- runtime suspend function just shutdown the clocks.
5. (patch 7)
- add cdns3 subnode again.
v5:
1. (patch 1) set correct model name and commit title.
2. (patch 2) change to '-item' in syscon property. change commit title.
3. (patch 5)
- change to '-item' in syscon configure.
- change commit title and doc title.
4. (patch 6)
- add clk and phy deinit function
- add clk deinit function if phy init failed.
- coding style changes and other format changes.
v4:
1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
3. (patch 3)
- split PCIe PHY driver to patch 4.
- replace dr_mode to phy mode in jh7110_usb2_phy.
4. (patch 4)
- Makefile and Kconfig sorted by alphabet sequence.
- Add PCIe PHY stg and syscon PHY connection configuration
for USB 3.0.
5. (patch 5)
- commit message changed.
- merge wrapper dts node and cdns3 node in example.
- Add interrupts, reg, phy and dr_mode in property.
- Add reset-name in property example.
6. (patch 6)
- For dts node is merged, Using platform_device_alloc and
platform_device_add to generate cadence sub device.
- IOMEM and IRQ resource are passed to Cadence sub device.
- Add PHY ops process for PHY dts setting can not be passed to
Cadence USB driver.
- remove the stg and sys USB 3.0 PHY configuration.
- Change the suspend clock reset and clock enable sequence.
- Get all reset and clock resources before enable them in
cdns_clk_rst_init.
- commit message changed.
7. (patch 7)
- merge wrapper dts node and cdns3 node in usb dts.
- move the stg and sys USB 3.0 PHY confiuration to
PCIe PHY dts node.
- commit message changed.
- Add reset-names dts.
v3:
1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
USB PHY codes are moved to patch 3 and patch 4.
2. (patch 5)
- USB wrapper module dts document is moved to usb directory.
- Remove the 'dr_mode' and 'starfive,usb2-only' setting.
- Some dts format changes. dts binding check pass.
3. (patch 6)
- Remove the PHY codes.
- Search 'dr_mode' and phy setting from Cadence subnode.
4. (patch 7)
- Add USB PHY dts configurion.
- 'dr_mode' is moved to Cadence controller submode.
v2:
1. (patch 5) dt-binding changes. The document example is the same as dts config.
2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
3. (patch 7) dts nodes sorted by the address after @
Minda Chen (7):
dt-bindings: phy: Add StarFive JH7110 USB PHY
dt-bindings: phy: Add StarFive JH7110 PCIe PHY
phy: starfive: Add JH7110 USB 2.0 PHY driver
phy: starfive: Add JH7110 PCIE 2.0 PHY driver
dt-bindings: usb: Add StarFive JH7110 USB controller
usb: cdns3: Add StarFive JH7110 USB driver
riscv: dts: starfive: Add USB dts configuration for JH7110
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 ++++
.../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++
MAINTAINERS | 14 +
.../jh7110-starfive-visionfive-2.dtsi | 5 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 ++++
drivers/phy/starfive/Kconfig | 21 ++
drivers/phy/starfive/Makefile | 2 +
drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++
drivers/phy/starfive/phy-jh7110-usb.c | 150 +++++++++++
drivers/usb/cdns3/Kconfig | 11 +
drivers/usb/cdns3/Makefile | 1 +
drivers/usb/cdns3/cdns3-starfive.c | 246 ++++++++++++++++++
13 files changed, 930 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
base-commit: ac9a78681b921877518763ba0e89202254349d1b
--
2.17.1
StarFive JH7110 platforms USB have a wrapper module around
the Cadence USBSS-DRD controller. Add binding information doc
for that.
Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Peter Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
new file mode 100644
index 000000000000..24aa9c10d6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-usb
+
+ ranges: true
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for USB.
+
+ dr_mode:
+ enum: [host, otg, peripheral]
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+ clocks:
+ items:
+ - description: link power management clock
+ - description: standby clock
+ - description: APB clock
+ - description: AXI clock
+ - description: UTMI APB clock
+
+ clock-names:
+ items:
+ - const: lpm
+ - const: stb
+ - const: apb
+ - const: axi
+ - const: utmi_apb
+
+ resets:
+ items:
+ - description: Power up reset
+ - description: APB clock reset
+ - description: AXI clock reset
+ - description: UTMI APB clock reset
+
+ reset-names:
+ items:
+ - const: pwrup
+ - const: apb
+ - const: axi
+ - const: utmi_apb
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: cdns,usb3.yaml#
+ description: Required child node
+
+required:
+ - compatible
+ - ranges
+ - starfive,stg-syscon
+ - '#address-cells'
+ - '#size-cells'
+ - dr_mode
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ ranges = <0x0 0x10100000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ clocks = <&syscrg 4>,
+ <&stgcrg 5>,
+ <&stgcrg 1>,
+ <&stgcrg 3>,
+ <&stgcrg 2>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg 10>,
+ <&stgcrg 8>,
+ <&stgcrg 7>,
+ <&stgcrg 9>;
+ reset-names = "pwrup", "apb", "axi", "utmi_apb";
+ dr_mode = "host";
+
+ usb@0 {
+ compatible = "cdns,usb3";
+ reg = <0x0 0x10000>,
+ <0x10000 0x10000>,
+ <0x20000 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ };
+ };
--
2.17.1
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
new file mode 100644
index 000000000000..2e83a6164cd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PCIe 2.0 PHY
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ starfive,sys-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
+ description:
+ The phandle to System Register Controller syscon node and the PHY connect offset
+ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
+ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10210000 0x10000>;
+ #phy-cells = <0>;
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
+ };
--
2.17.1
On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote:
> StarFive JH7110 platforms USB have a wrapper module around
> the Cadence USBSS-DRD controller. Add binding information doc
> for that.
>
> Signed-off-by: Minda Chen <[email protected]>
> Reviewed-by: Peter Chen <[email protected]>
> Reviewed-by: Hal Feng <[email protected]>
> ---
> .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> new file mode 100644
> index 000000000000..24aa9c10d6ab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
USBSS-DRD SoC controller"?
Otherwise, it looks like all the stuff from him and Rob have been sorted
out, so other than $title this is
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor..
On 18/05/2023 14:27, Minda Chen wrote:
> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
> The patch has been tested on the VisionFive 2 board.
>
> This patchset should be applied after the patchset [1], [2] and [3]:
> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
> [2] https://patchwork.kernel.org/project/linux-clk/cover/[email protected]
> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>
> This patchset is base on v6.4-rc1
>
> patch 1 is usb phy dt-binding document.
> patch 2 is Pcie PHY dt-binding document.
> patch 3 is USB 2.0 PHY driver.
> patch 4 is PCIe PHY driver.
> patch 5 is usb dt-binding document.
> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
> patch 7 is USB device tree configuration.
>
> previous version
> ---
> version 1 patchset are split to different kernel organization. It is
> incorrect. But they were sent, and Emil sent comments. I think I should
> reserve them in cover-letter. To read the change records and previous version,
> please start with version 2.
>
> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
> v4: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
> v5: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>
> changes
> v6:
> 1. (patch 3) remove the platform remove function.
> 2. (patch 4)
> - add switch to pcie mode function.
> - remove the redundant init/exit function.
> 3. (patch 5)
> - dts split to wrapper layer and cdns node. The codes are
> like v3.
> - add cdns3 sub node dts-binding references.
> 4. (patch 6)
> For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
> to usb, so USB contain its own registers. So do not merge the dts node.
> The codes are like v3.
> - remove the cdns3_platform_add function.
> - remove phy ops because cdns3 contain all the phy ops.
> - runtime suspend function just shutdown the clocks.
> 5. (patch 7)
> - add cdns3 subnode again.
>
> v5:
> 1. (patch 1) set correct model name and commit title.
> 2. (patch 2) change to '-item' in syscon property. change commit title.
> 3. (patch 5)
> - change to '-item' in syscon configure.
> - change commit title and doc title.
> 4. (patch 6)
> - add clk and phy deinit function
> - add clk deinit function if phy init failed.
> - coding style changes and other format changes.
>
> v4:
> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
> 3. (patch 3)
> - split PCIe PHY driver to patch 4.
> - replace dr_mode to phy mode in jh7110_usb2_phy.
> 4. (patch 4)
> - Makefile and Kconfig sorted by alphabet sequence.
> - Add PCIe PHY stg and syscon PHY connection configuration
> for USB 3.0.
> 5. (patch 5)
> - commit message changed.
> - merge wrapper dts node and cdns3 node in example.
> - Add interrupts, reg, phy and dr_mode in property.
> - Add reset-name in property example.
> 6. (patch 6)
> - For dts node is merged, Using platform_device_alloc and
> platform_device_add to generate cadence sub device.
> - IOMEM and IRQ resource are passed to Cadence sub device.
> - Add PHY ops process for PHY dts setting can not be passed to
> Cadence USB driver.
> - remove the stg and sys USB 3.0 PHY configuration.
> - Change the suspend clock reset and clock enable sequence.
> - Get all reset and clock resources before enable them in
> cdns_clk_rst_init.
> - commit message changed.
> 7. (patch 7)
> - merge wrapper dts node and cdns3 node in usb dts.
> - move the stg and sys USB 3.0 PHY confiuration to
> PCIe PHY dts node.
> - commit message changed.
> - Add reset-names dts.
>
> v3:
> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
> USB PHY codes are moved to patch 3 and patch 4.
> 2. (patch 5)
> - USB wrapper module dts document is moved to usb directory.
> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
> - Some dts format changes. dts binding check pass.
> 3. (patch 6)
> - Remove the PHY codes.
> - Search 'dr_mode' and phy setting from Cadence subnode.
> 4. (patch 7)
> - Add USB PHY dts configurion.
> - 'dr_mode' is moved to Cadence controller submode.
>
> v2:
> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
> 3. (patch 7) dts nodes sorted by the address after @
>
> Minda Chen (7):
> dt-bindings: phy: Add StarFive JH7110 USB PHY
> dt-bindings: phy: Add StarFive JH7110 PCIe PHY
> phy: starfive: Add JH7110 USB 2.0 PHY driver
> phy: starfive: Add JH7110 PCIE 2.0 PHY driver
> dt-bindings: usb: Add StarFive JH7110 USB controller
> usb: cdns3: Add StarFive JH7110 USB driver
> riscv: dts: starfive: Add USB dts configuration for JH7110
>
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++
> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 ++++
> .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++
> MAINTAINERS | 14 +
> .../jh7110-starfive-visionfive-2.dtsi | 5 +
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 ++++
> drivers/phy/starfive/Kconfig | 21 ++
> drivers/phy/starfive/Makefile | 2 +
> drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++
> drivers/phy/starfive/phy-jh7110-usb.c | 150 +++++++++++
> drivers/usb/cdns3/Kconfig | 11 +
> drivers/usb/cdns3/Makefile | 1 +
> drivers/usb/cdns3/cdns3-starfive.c | 246 ++++++++++++++++++
> 13 files changed, 930 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
For this series:
Reviewed-by: Roger Quadros <[email protected]>
On 2023/5/26 5:34, Conor Dooley wrote:
> On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote:
>> StarFive JH7110 platforms USB have a wrapper module around
>> the Cadence USBSS-DRD controller. Add binding information doc
>> for that.
>>
>> Signed-off-by: Minda Chen <[email protected]>
>> Reviewed-by: Peter Chen <[email protected]>
>> Reviewed-by: Hal Feng <[email protected]>
>> ---
>> .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
>> 1 file changed, 115 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> new file mode 100644
>> index 000000000000..24aa9c10d6ab
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> @@ -0,0 +1,115 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
>
> I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> USBSS-DRD SoC controller"?
>
The previous title describe whole USB controller for previous dts node is merged. Now the dts node is split.
"starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
> Otherwise, it looks like all the stuff from him and Rob have been sorted
> out, so other than $title this is
> Reviewed-by: Conor Dooley <[email protected]>
>
> Thanks,
> Conor..
Thanks
On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:
> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
> >
> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> > USBSS-DRD SoC controller"?
> >
> The previous title describe whole USB controller for previous dts node is
> merged. Now the dts node is split.
> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
Okay, I must have misunderstood the conversation on the previous
version. Sorry about that.
> > Otherwise, it looks like all the stuff from him and Rob have been sorted
> > out, so other than $title this is
> > Reviewed-by: Conor Dooley <[email protected]>
On 2023/5/26 17:03, Roger Quadros wrote:
>
>
> On 18/05/2023 14:27, Minda Chen wrote:
>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>> The patch has been tested on the VisionFive 2 board.
>>
>> This patchset should be applied after the patchset [1], [2] and [3]:
>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
>> [2] https://patchwork.kernel.org/project/linux-clk/cover/[email protected]
>> [3] https://patchwork.kernel.org/project/linux-phy/cover/[email protected]/
>>
>> This patchset is base on v6.4-rc1
>>
>> patch 1 is usb phy dt-binding document.
>> patch 2 is Pcie PHY dt-binding document.
>> patch 3 is USB 2.0 PHY driver.
>> patch 4 is PCIe PHY driver.
>> patch 5 is usb dt-binding document.
>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>> patch 7 is USB device tree configuration.
>>
>> previous version
>> ---
>> version 1 patchset are split to different kernel organization. It is
>> incorrect. But they were sent, and Emil sent comments. I think I should
>> reserve them in cover-letter. To read the change records and previous version,
>> please start with version 2.
>>
>> v1: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>> v2: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>> v3: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>> v4: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>> v5: https://patchwork.kernel.org/project/linux-usb/cover/[email protected]/
>>
>> changes
>> v6:
>> 1. (patch 3) remove the platform remove function.
>> 2. (patch 4)
>> - add switch to pcie mode function.
>> - remove the redundant init/exit function.
>> 3. (patch 5)
>> - dts split to wrapper layer and cdns node. The codes are
>> like v3.
>> - add cdns3 sub node dts-binding references.
>> 4. (patch 6)
>> For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
>> to usb, so USB contain its own registers. So do not merge the dts node.
>> The codes are like v3.
>> - remove the cdns3_platform_add function.
>> - remove phy ops because cdns3 contain all the phy ops.
>> - runtime suspend function just shutdown the clocks.
>> 5. (patch 7)
>> - add cdns3 subnode again.
>>
>> v5:
>> 1. (patch 1) set correct model name and commit title.
>> 2. (patch 2) change to '-item' in syscon property. change commit title.
>> 3. (patch 5)
>> - change to '-item' in syscon configure.
>> - change commit title and doc title.
>> 4. (patch 6)
>> - add clk and phy deinit function
>> - add clk deinit function if phy init failed.
>> - coding style changes and other format changes.
>>
>> v4:
>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>> 3. (patch 3)
>> - split PCIe PHY driver to patch 4.
>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>> 4. (patch 4)
>> - Makefile and Kconfig sorted by alphabet sequence.
>> - Add PCIe PHY stg and syscon PHY connection configuration
>> for USB 3.0.
>> 5. (patch 5)
>> - commit message changed.
>> - merge wrapper dts node and cdns3 node in example.
>> - Add interrupts, reg, phy and dr_mode in property.
>> - Add reset-name in property example.
>> 6. (patch 6)
>> - For dts node is merged, Using platform_device_alloc and
>> platform_device_add to generate cadence sub device.
>> - IOMEM and IRQ resource are passed to Cadence sub device.
>> - Add PHY ops process for PHY dts setting can not be passed to
>> Cadence USB driver.
>> - remove the stg and sys USB 3.0 PHY configuration.
>> - Change the suspend clock reset and clock enable sequence.
>> - Get all reset and clock resources before enable them in
>> cdns_clk_rst_init.
>> - commit message changed.
>> 7. (patch 7)
>> - merge wrapper dts node and cdns3 node in usb dts.
>> - move the stg and sys USB 3.0 PHY confiuration to
>> PCIe PHY dts node.
>> - commit message changed.
>> - Add reset-names dts.
>>
>> v3:
>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>> USB PHY codes are moved to patch 3 and patch 4.
>> 2. (patch 5)
>> - USB wrapper module dts document is moved to usb directory.
>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>> - Some dts format changes. dts binding check pass.
>> 3. (patch 6)
>> - Remove the PHY codes.
>> - Search 'dr_mode' and phy setting from Cadence subnode.
>> 4. (patch 7)
>> - Add USB PHY dts configurion.
>> - 'dr_mode' is moved to Cadence controller submode.
>>
>> v2:
>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>> 3. (patch 7) dts nodes sorted by the address after @
>>
>> Minda Chen (7):
>> dt-bindings: phy: Add StarFive JH7110 USB PHY
>> dt-bindings: phy: Add StarFive JH7110 PCIe PHY
>> phy: starfive: Add JH7110 USB 2.0 PHY driver
>> phy: starfive: Add JH7110 PCIE 2.0 PHY driver
>> dt-bindings: usb: Add StarFive JH7110 USB controller
>> usb: cdns3: Add StarFive JH7110 USB driver
>> riscv: dts: starfive: Add USB dts configuration for JH7110
>>
>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++
>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 ++++
>> .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++
>> MAINTAINERS | 14 +
>> .../jh7110-starfive-visionfive-2.dtsi | 5 +
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 ++++
>> drivers/phy/starfive/Kconfig | 21 ++
>> drivers/phy/starfive/Makefile | 2 +
>> drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++
>> drivers/phy/starfive/phy-jh7110-usb.c | 150 +++++++++++
>> drivers/usb/cdns3/Kconfig | 11 +
>> drivers/usb/cdns3/Makefile | 1 +
>> drivers/usb/cdns3/cdns3-starfive.c | 246 ++++++++++++++++++
>> 13 files changed, 930 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>
>
> For this series:
> Reviewed-by: Roger Quadros <[email protected]>
Thanks Roger， Coner and Greg.
Patch 6 (USB controller codes) are accepted.
Thanks Rob and Krzysztof.
Dts-binding doc are reviewed.
Hi Vinod , Kishon and Linux-PHY maintainer
Could you take time to review USB PHY codes (patch 3 and patch4) ? Thanks
On 2023/5/26 21:13, Conor Dooley wrote:
> On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:
>
>> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
>> >
>> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
>> > USBSS-DRD SoC controller"?
>> >
>> The previous title describe whole USB controller for previous dts node is
>> merged. Now the dts node is split.
>> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
>
> Okay, I must have misunderstood the conversation on the previous
> version. Sorry about that.
>
>> > Otherwise, it looks like all the stuff from him and Rob have been sorted
>> > out, so other than $title this is
>> > Reviewed-by: Conor Dooley <[email protected]>
>
Hi Greg
Can this patch can be applied to Linux-USB-next tree? Since this patch is reviewed by Conor.
List Below is Conor's previous E-mail.
I think I missed this mail somehow. 5/7 had the binding for the driver
so probably that should've gone via the USB tree too?
Should apply on its own (no deps on the phy patches) & has dt-binding
maintainer reviews.
`b4 am -P 5 [email protected]` if
that's your cup of tea.
On Sun, Jun 18, 2023 at 08:22:05PM +0800, Minda Chen wrote:
>
>
> On 2023/5/26 21:13, Conor Dooley wrote:
> > On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:
> >
> >> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
> >> >
> >> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> >> > USBSS-DRD SoC controller"?
> >> >
> >> The previous title describe whole USB controller for previous dts node is
> >> merged. Now the dts node is split.
> >> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
> >
> > Okay, I must have misunderstood the conversation on the previous
> > version. Sorry about that.
> >
> >> > Otherwise, it looks like all the stuff from him and Rob have been sorted
> >> > out, so other than $title this is
> >> > Reviewed-by: Conor Dooley <[email protected]>
> >
>
> Hi Greg
> Can this patch can be applied to Linux-USB-next tree? Since this patch is reviewed by Conor.
>
> List Below is Conor's previous E-mail.
>
> I think I missed this mail somehow. 5/7 had the binding for the driver
> so probably that should've gone via the USB tree too?
> Should apply on its own (no deps on the phy patches) & has dt-binding
> maintainer reviews.
>
> `b4 am -P 5 [email protected]` if
> that's your cup of tea.
Thanks, I missed that, now applied!
greg k-h