DMA detection will fail if axinet was started before (by boot loader,
boot ROM, etc). In this state axinet will not start properly.
XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to detect
64 DMA capability here. But datasheet says: When DMACR.RS is 1
(axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
is used to fetch the first descriptor. So iowrite32()/ioread32() trick
to this register to detect DMA will not work.
So move axinet reset before DMA detection.
Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO access")
Signed-off-by: Maxim Kochetkov <[email protected]>
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 3e310b55bce2..734822321e0a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device *pdev)
goto cleanup_clk;
}
+ /* Reset core now that clocks are enabled, prior to accessing MDIO */
+ ret = __axienet_device_reset(lp);
+ if (ret)
+ goto cleanup_clk;
+
/* Autodetect the need for 64-bit DMA pointers.
* When the IP is configured for a bus width bigger than 32 bits,
* writing the MSB registers is mandatory, even if they are all 0.
@@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device *pdev)
lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
- /* Reset core now that clocks are enabled, prior to accessing MDIO */
- ret = __axienet_device_reset(lp);
- if (ret)
- goto cleanup_clk;
-
ret = axienet_mdio_setup(lp);
if (ret)
dev_warn(&pdev->dev,
--
2.40.1
On Thu, 2023-06-22 at 20:52 +0300, Maxim Kochetkov wrote:
> DMA detection will fail if axinet was started before (by boot loader,
> boot ROM, etc). In this state axinet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32()
> trick
> to this register to detect DMA will not work.
> So move axinet reset before DMA detection.
>
> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization
> prior to MDIO access")
> Signed-off-by: Maxim Kochetkov <[email protected]>
>
Reviewed-by: Robert Hancock <[email protected]>
> ---
> drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct
> platform_device *pdev)
> goto cleanup_clk;
> }
>
> + /* Reset core now that clocks are enabled, prior to accessing
> MDIO */
> + ret = __axienet_device_reset(lp);
> + if (ret)
> + goto cleanup_clk;
> +
> /* Autodetect the need for 64-bit DMA pointers.
> * When the IP is configured for a bus width bigger than 32
> bits,
> * writing the MSB registers is mandatory, even if they are
> all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct
> platform_device *pdev)
> lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
> lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
>
> - /* Reset core now that clocks are enabled, prior to accessing
> MDIO */
> - ret = __axienet_device_reset(lp);
> - if (ret)
> - goto cleanup_clk;
> -
> ret = axienet_mdio_setup(lp);
> if (ret)
> dev_warn(&pdev->dev,
> --
> 2.40.1
>
On 22.06.2023 21:43, Pandey, Radhey Shyam wrote:
>> DMA detection will fail if axinet was started before (by boot loader,
>
> :%s/axinet/axienet/g
Sorry about that. I will fix it in v3.
>
>> boot ROM, etc). In this state axinet will not start properly.
>> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
>> detect
>> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
>> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
>> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
>> to this register to detect DMA will not work.
>> So move axinet reset before DMA detection.
>>
>> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO
>
> Is this fixes tag correct ? I think the failure is introduced after
> f735c40ed93c net: axienet: Autodetect 64-bit DMA capability?
Yes of course. I will fix it in v3.
> -----Original Message-----
> From: Maxim Kochetkov <[email protected]>
> Sent: Thursday, June 22, 2023 11:22 PM
> To: [email protected]
> Cc: Maxim Kochetkov <[email protected]>; Pandey, Radhey Shyam
> <[email protected]>; David S. Miller
> <[email protected]>; Eric Dumazet <[email protected]>; Jakub
> Kicinski <[email protected]>; Paolo Abeni <[email protected]>; Simek,
> Michal <[email protected]>; Andrew Lunn <[email protected]>; Robert
> Hancock <[email protected]>; linux-arm-
> [email protected]; [email protected]
> Subject: [PATCH v2 1/1] net: axienet: Move reset before DMA detection
>
> DMA detection will fail if axinet was started before (by boot loader,
:%s/axinet/axienet/g
> boot ROM, etc). In this state axinet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
> to this register to detect DMA will not work.
> So move axinet reset before DMA detection.
>
> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to MDIO
Is this fixes tag correct ? I think the failure is introduced after
f735c40ed93c net: axienet: Autodetect 64-bit DMA capability?
> access")
> Signed-off-by: Maxim Kochetkov <[email protected]>
> ---
> drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device
> *pdev)
> goto cleanup_clk;
> }
>
> + /* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> + ret = __axienet_device_reset(lp);
> + if (ret)
> + goto cleanup_clk;
> +
> /* Autodetect the need for 64-bit DMA pointers.
> * When the IP is configured for a bus width bigger than 32 bits,
> * writing the MSB registers is mandatory, even if they are all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device
> *pdev)
> lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
> lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
>
> - /* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> - ret = __axienet_device_reset(lp);
> - if (ret)
> - goto cleanup_clk;
> -
> ret = axienet_mdio_setup(lp);
> if (ret)
> dev_warn(&pdev->dev,
> --
> 2.40.1
> + /* Reset core now that clocks are enabled, prior to accessing MDIO */
> + ret = __axienet_device_reset(lp);
> + if (ret)
> + goto cleanup_clk;
> +
> /* Autodetect the need for 64-bit DMA pointers.
I would say the comment is now not fully correct. It probably should
be extended to include 64 bit DMA.
Andrew
On 22.06.2023 22:18, Andrew Lunn wrote:
>> + /* Reset core now that clocks are enabled, prior to accessing MDIO */
>> + ret = __axienet_device_reset(lp);
>> + if (ret)
>> + goto cleanup_clk;
>> +
>> /* Autodetect the need for 64-bit DMA pointers.
>
> I would say the comment is now not fully correct. It probably should
> be extended to include 64 bit DMA.
Fixed in v4