From: Heiko Stuebner <[email protected]>
There is at least one core implementing the wrong vector specification,
which cannot claim to implement the v extension but still is able to
do vectors similar to v.
To not hack around this by claiming to do v, move the has_vector() return
to act similar to riscv_noncoherent_supported() and move to a separate
variable that can be set for example from errata code.
Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/include/asm/vector.h | 5 ++++-
arch/riscv/kernel/setup.c | 6 ++++++
arch/riscv/kernel/vector.c | 8 ++++++++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 04c0b07bf6cd..315c96d2b4d0 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -19,13 +19,16 @@
#include <asm/csr.h>
#include <asm/asm.h>
+extern bool riscv_v_supported;
+void riscv_vector_supported(void);
+
extern unsigned long riscv_v_vsize;
int riscv_v_setup_vsize(void);
bool riscv_v_first_use_handler(struct pt_regs *regs);
static __always_inline bool has_vector(void)
{
- return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
+ return riscv_v_supported;
}
static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 971fe776e2f8..952dfb90525e 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -36,6 +36,7 @@
#include <asm/thread_info.h>
#include <asm/kasan.h>
#include <asm/efi.h>
+#include <asm/vector.h>
#include "head.h"
@@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p)
riscv_fill_hwcap();
init_rt_signal_env();
apply_boot_alternatives();
+
+ if (IS_ENABLED(CONFIG_RISCV_ISA_V) &&
+ riscv_isa_extension_available(NULL, v))
+ riscv_vector_supported();
+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
riscv_isa_extension_available(NULL, ZICBOM))
riscv_noncoherent_supported();
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index f9c8e19ab301..74178fb71805 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -22,6 +22,9 @@
static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE);
+bool riscv_v_supported;
+EXPORT_SYMBOL_GPL(riscv_v_supported);
+
unsigned long riscv_v_vsize __read_mostly;
EXPORT_SYMBOL_GPL(riscv_v_vsize);
@@ -274,3 +277,8 @@ static int riscv_v_init(void)
return riscv_v_sysctl_init();
}
core_initcall(riscv_v_init);
+
+void riscv_vector_supported(void)
+{
+ riscv_v_supported = true;
+}
--
2.39.2
Hey Heiko,
On Fri, Jun 23, 2023 at 01:13:04AM +0200, Heiko Stuebner wrote:
> From: Heiko Stuebner <[email protected]>
>
> There is at least one core implementing the wrong vector specification,
> which cannot claim to implement the v extension but still is able to
> do vectors similar to v.
>
> To not hack around this by claiming to do v, move the has_vector() return
> to act similar to riscv_noncoherent_supported() and move to a separate
> variable that can be set for example from errata code.
>
> Signed-off-by: Heiko Stuebner <[email protected]>
> ---
> arch/riscv/include/asm/vector.h | 5 ++++-
> arch/riscv/kernel/setup.c | 6 ++++++
> arch/riscv/kernel/vector.c | 8 ++++++++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 04c0b07bf6cd..315c96d2b4d0 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -19,13 +19,16 @@
> #include <asm/csr.h>
> #include <asm/asm.h>
>
> +extern bool riscv_v_supported;
> +void riscv_vector_supported(void);
> +
> extern unsigned long riscv_v_vsize;
> int riscv_v_setup_vsize(void);
> bool riscv_v_first_use_handler(struct pt_regs *regs);
>
> static __always_inline bool has_vector(void)
> {
> - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
> + return riscv_v_supported;
Since you're moving this thing away from being backed by an alternative,
should this variable then be marked with something like __ro_after_init?
Cheers,
Conor.
> }
>
> static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 971fe776e2f8..952dfb90525e 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -36,6 +36,7 @@
> #include <asm/thread_info.h>
> #include <asm/kasan.h>
> #include <asm/efi.h>
> +#include <asm/vector.h>
>
> #include "head.h"
>
> @@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p)
> riscv_fill_hwcap();
> init_rt_signal_env();
> apply_boot_alternatives();
> +
> + if (IS_ENABLED(CONFIG_RISCV_ISA_V) &&
> + riscv_isa_extension_available(NULL, v))
> + riscv_vector_supported();
> +
> if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> riscv_isa_extension_available(NULL, ZICBOM))
> riscv_noncoherent_supported();
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index f9c8e19ab301..74178fb71805 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -22,6 +22,9 @@
>
> static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE);
>
> +bool riscv_v_supported;
> +EXPORT_SYMBOL_GPL(riscv_v_supported);
> +
> unsigned long riscv_v_vsize __read_mostly;
> EXPORT_SYMBOL_GPL(riscv_v_vsize);
>
> @@ -274,3 +277,8 @@ static int riscv_v_init(void)
> return riscv_v_sysctl_init();
> }
> core_initcall(riscv_v_init);
> +
> +void riscv_vector_supported(void)
> +{
> + riscv_v_supported = true;
> +}
> --
> 2.39.2
>
Hi Heiko,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20230622]
[cannot apply to linus/master v6.4-rc7 v6.4-rc6 v6.4-rc5 v6.4-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Heiko-Stuebner/RISC-V-move-vector-available-status-into-a-dedicated-variable/20230623-081314
base: next-20230622
patch link: https://lore.kernel.org/r/20230622231305.631331-3-heiko%40sntech.de
patch subject: [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20230623/[email protected]/config)
compiler: riscv64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230623/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
arch/riscv/kernel/setup.c: In function 'setup_arch':
>> arch/riscv/kernel/setup.c:315:17: error: implicit declaration of function 'riscv_vector_supported'; did you mean 'riscv_noncoherent_supported'? [-Werror=implicit-function-declaration]
315 | riscv_vector_supported();
| ^~~~~~~~~~~~~~~~~~~~~~
| riscv_noncoherent_supported
cc1: some warnings being treated as errors
vim +315 arch/riscv/kernel/setup.c
304
305 if (!acpi_disabled)
306 acpi_init_rintc_map();
307
308 riscv_init_cbo_blocksizes();
309 riscv_fill_hwcap();
310 init_rt_signal_env();
311 apply_boot_alternatives();
312
313 if (IS_ENABLED(CONFIG_RISCV_ISA_V) &&
314 riscv_isa_extension_available(NULL, v))
> 315 riscv_vector_supported();
316
317 if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
318 riscv_isa_extension_available(NULL, ZICBOM))
319 riscv_noncoherent_supported();
320 }
321
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki