From: Lad Prabhakar <[email protected]>
Hi Geert,
This patch series intends to incorporate the absent port pins P19 to P28,
which are exclusively available on the RZ/Five SoC.
I am submitting this series as an RFC (Request for Comments) as the port
pins P19 to P28 cannot be utilized as GPIO but can be utilized as
multiplexed pins. Additionally, certain attributes such as setting the
ISEL would necessitate a device tree property to indicate ISEL. Therefore,
before proceeding with the addition of comprehensive support, I would
appreciate some input on whether an alternative approach could be considered.
Cheers,
Prabhakar
Lad Prabhakar (4):
pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK()
macro
pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in
rzg2l_gpio_request()
pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 +++++++++++++-------
2 files changed, 176 insertions(+), 91 deletions(-)
--
2.34.1
From: Lad Prabhakar <[email protected]>
Validate the GPIO pin request in rzg2l_gpio_request() callback using
rzg2l_validate_gpio_pin() function.
Signed-off-by: Lad Prabhakar <[email protected]>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index a0c2e585e765..2fc1b880db0c 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -780,12 +780,18 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = {
static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
+ const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[offset];
+ u64 *pin_data = pin->drv_data;
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
unsigned long flags;
u8 reg8;
int ret;
+ ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
+ if (ret)
+ return ret;
+
ret = pinctrl_gpio_request(chip->base + offset);
if (ret)
return ret;
--
2.34.1
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:04 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> This patch series intends to incorporate the absent port pins P19 to P28,
> which are exclusively available on the RZ/Five SoC.
Are you sure these are not available on RZ/G2UL?
I thought RZ/Five and RZ/G2UL were identical, except for the ARM
vs. RISC-V CPU core (+ support)?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds