A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
This would result in the upper 32 bits being unintentionally zeroed and
MSIs getting mapped to incorrect PCI addresses if the address had any
of the upper bits set.
Replace 32-bit mask by appropriate 64-bit mask.
Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint")
Reported-by: Dan Carpenter <[email protected]>
Closes: https://lore.kernel.org/linux-pci/[email protected]/
Signed-off-by: Rick Wertenbroek <[email protected]>
Cc: [email protected]
---
drivers/pci/controller/pcie-rockchip.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index fe0333778fd9..627d08b34827 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -158,7 +158,9 @@
#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
-#define PCIE_ADDR_MASK 0xffffff00
+#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
+#define MIN_AXI_ADDR_BITS_PASSED 8
+#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
#define PCIE_CORE_AXI_CONF_BASE 0xc00000
#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
@@ -185,8 +187,6 @@
#define AXI_WRAPPER_TYPE1_CFG 0xb
#define AXI_WRAPPER_NOR_MSG 0xc
-#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
-#define MIN_AXI_ADDR_BITS_PASSED 8
#define PCIE_RC_SEND_PME_OFF 0x11960
#define ROCKCHIP_VENDOR_ID 0x1d87
#define PCIE_LINK_IS_L2(x) \
--
2.25.1
On 7/3/23 17:58, Rick Wertenbroek wrote:
> A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> This would result in the upper 32 bits being unintentionally zeroed and
> MSIs getting mapped to incorrect PCI addresses if the address had any
> of the upper bits set.
>
> Replace 32-bit mask by appropriate 64-bit mask.
>
> Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint")
> Reported-by: Dan Carpenter <[email protected]>
> Closes: https://lore.kernel.org/linux-pci/[email protected]/
> Signed-off-by: Rick Wertenbroek <[email protected]>
> Cc: [email protected]
Looks good to me.
Reviewed-by: Damien Le Moal <[email protected]>
> ---
> drivers/pci/controller/pcie-rockchip.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index fe0333778fd9..627d08b34827 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -158,7 +158,9 @@
> #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
> #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
>
> -#define PCIE_ADDR_MASK 0xffffff00
> +#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> +#define MIN_AXI_ADDR_BITS_PASSED 8
> +#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
> #define PCIE_CORE_AXI_CONF_BASE 0xc00000
> #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
> #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
> @@ -185,8 +187,6 @@
> #define AXI_WRAPPER_TYPE1_CFG 0xb
> #define AXI_WRAPPER_NOR_MSG 0xc
>
> -#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> -#define MIN_AXI_ADDR_BITS_PASSED 8
> #define PCIE_RC_SEND_PME_OFF 0x11960
> #define ROCKCHIP_VENDOR_ID 0x1d87
> #define PCIE_LINK_IS_L2(x) \
--
Damien Le Moal
Western Digital Research
On 2023-07-03 09:58, Rick Wertenbroek wrote:
> A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> This would result in the upper 32 bits being unintentionally zeroed and
> MSIs getting mapped to incorrect PCI addresses if the address had any
> of the upper bits set.
>
> Replace 32-bit mask by appropriate 64-bit mask.
>
> Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint")
> Reported-by: Dan Carpenter <[email protected]>
> Closes: https://lore.kernel.org/linux-pci/[email protected]/
> Signed-off-by: Rick Wertenbroek <[email protected]>
> Cc: [email protected]
> ---
> drivers/pci/controller/pcie-rockchip.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index fe0333778fd9..627d08b34827 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -158,7 +158,9 @@
> #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
> #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
>
> -#define PCIE_ADDR_MASK 0xffffff00
> +#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> +#define MIN_AXI_ADDR_BITS_PASSED 8
> +#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
Nit: this probably wants to be GENMASK_ULL(), otherwise it might throw a
warning if compile-tested for 32-bit.
Thanks,
Robin.
> #define PCIE_CORE_AXI_CONF_BASE 0xc00000
> #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
> #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
> @@ -185,8 +187,6 @@
> #define AXI_WRAPPER_TYPE1_CFG 0xb
> #define AXI_WRAPPER_NOR_MSG 0xc
>
> -#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
> -#define MIN_AXI_ADDR_BITS_PASSED 8
> #define PCIE_RC_SEND_PME_OFF 0x11960
> #define ROCKCHIP_VENDOR_ID 0x1d87
> #define PCIE_LINK_IS_L2(x) \
Hello,
> > A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> > This would result in the upper 32 bits being unintentionally zeroed and
> > MSIs getting mapped to incorrect PCI addresses if the address had any
> > of the upper bits set.
> >
> > Replace 32-bit mask by appropriate 64-bit mask.
[...]
> > +#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
>
> Nit: this probably wants to be GENMASK_ULL(), otherwise it might throw a
> warning if compile-tested for 32-bit.
I can change this to GENMASK_ULL() when I apply the patch. Unless Rick
wants to send v3 - either way would be fine. :)
Krzysztof
On Mon, Jul 3, 2023 at 2:08 PM Krzysztof Wilczyński <[email protected]> wrote:
>
> Hello,
>
> > > A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> > > This would result in the upper 32 bits being unintentionally zeroed and
> > > MSIs getting mapped to incorrect PCI addresses if the address had any
> > > of the upper bits set.
> > >
> > > Replace 32-bit mask by appropriate 64-bit mask.
>
> [...]
> > > +#define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
> >
> > Nit: this probably wants to be GENMASK_ULL(), otherwise it might throw a
> > warning if compile-tested for 32-bit.
>
> I can change this to GENMASK_ULL() when I apply the patch. Unless Rick
> wants to send v3 - either way would be fine. :)
>
> Krzysztof
Thank you, I'd appreciate that rather than sending a v3.
Regards,
Rick
Hi Rick,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on linus/master next-20230703]
[cannot apply to pci/for-linus v6.4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Rick-Wertenbroek/PCI-rockchip-Use-64-bit-mask-on-MSI-64-bit-PCI-address/20230703-165959
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20230703085845.2052008-1-rick.wertenbroek%40gmail.com
patch subject: [PATCH v2] PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20230703/[email protected]/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230703/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
In file included from include/linux/bitops.h:6,
from include/linux/log2.h:12,
from include/asm-generic/div64.h:55,
from arch/arm/include/asm/div64.h:107,
from include/linux/math.h:6,
from include/linux/math64.h:6,
from include/linux/time.h:6,
from include/linux/stat.h:19,
from include/linux/configfs.h:22,
from drivers/pci/controller/pcie-rockchip-ep.c:11:
drivers/pci/controller/pcie-rockchip-ep.c: In function 'rockchip_pcie_prog_ep_ob_atu':
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip.h:167:49: note: in expansion of macro 'PCIE_ADDR_MASK'
167 | #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR PCIE_ADDR_MASK
| ^~~~~~~~~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:77:44: note: in expansion of macro 'PCIE_CORE_OB_REGION_ADDR0_LO_ADDR'
77 | (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from include/asm-generic/div64.h:27:
drivers/pci/controller/pcie-rockchip-ep.c: In function 'rockchip_pcie_ep_send_msi_irq':
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler.h:78:45: note: in definition of macro 'unlikely'
78 | # define unlikely(x) __builtin_expect(!!(x), 0)
| ^
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:394:54: note: in expansion of macro 'PCIE_ADDR_MASK'
394 | if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) ||
| ^~~~~~~~~~~~~~
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:399:57: note: in expansion of macro 'PCIE_ADDR_MASK'
399 | pci_addr & PCIE_ADDR_MASK,
| ^~~~~~~~~~~~~~
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:400:47: note: in expansion of macro 'PCIE_ADDR_MASK'
400 | ~PCIE_ADDR_MASK + 1);
| ^~~~~~~~~~~~~~
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:401:48: note: in expansion of macro 'PCIE_ADDR_MASK'
401 | ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK);
| ^~~~~~~~~~~~~~
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:17,
from arch/arm/include/asm/hardirq.h:10,
from include/linux/hardirq.h:11,
from include/linux/interrupt.h:11,
from include/linux/pci.h:38,
from include/linux/pci-epf.h:15,
from include/linux/pci-epc.h:12,
from drivers/pci/controller/pcie-rockchip-ep.c:15:
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
arch/arm/include/asm/io.h:281:75: note: in definition of macro 'writew_relaxed'
281 | #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
| ^
drivers/pci/controller/pcie-rockchip-ep.c:405:9: note: in expansion of macro 'writew'
405 | writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));
| ^~~~~~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip-ep.c:405:54: note: in expansion of macro 'PCIE_ADDR_MASK'
405 | writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));
| ^~~~~~~~~~~~~~
--
In file included from include/linux/bitops.h:6,
from include/linux/kernel.h:22,
from include/linux/clk.h:13,
from drivers/pci/controller/pcie-rockchip-host.c:15:
drivers/pci/controller/pcie-rockchip-host.c: In function 'rockchip_pcie_prog_ob_atu':
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip.h:167:49: note: in expansion of macro 'PCIE_ADDR_MASK'
167 | #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR PCIE_ADDR_MASK
| ^~~~~~~~~~~~~~
drivers/pci/controller/pcie-rockchip-host.c:733:35: note: in expansion of macro 'PCIE_CORE_OB_REGION_ADDR0_LO_ADDR'
733 | ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/controller/pcie-rockchip-host.c: In function 'rockchip_pcie_prog_ib_atu':
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/pci/controller/pcie-rockchip.h:163:41: note: in expansion of macro 'GENMASK'
163 | #define PCIE_ADDR_MASK GENMASK(63, MIN_AXI_ADDR_BITS_PASSED)
| ^~~~~~~
drivers/pci/controller/pcie-rockchip.h:175:49: note: in expansion of macro 'PCIE_ADDR_MASK'
175 | #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR PCIE_ADDR_MASK
| ^~~~~~~~~~~~~~
drivers/pci/controller/pcie-rockchip-host.c:767:42: note: in expansion of macro 'PCIE_CORE_IB_REGION_ADDR0_LO_ADDR'
767 | ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +35 include/linux/bits.h
295bcca84916cb Rikard Falkeborn 2020-04-06 32
295bcca84916cb Rikard Falkeborn 2020-04-06 33 #define __GENMASK(h, l) \
95b980d62d52c4 Masahiro Yamada 2019-07-16 34 (((~UL(0)) - (UL(1) << (l)) + 1) & \
95b980d62d52c4 Masahiro Yamada 2019-07-16 @35 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
295bcca84916cb Rikard Falkeborn 2020-04-06 36 #define GENMASK(h, l) \
295bcca84916cb Rikard Falkeborn 2020-04-06 37 (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
8bd9cb51daac89 Will Deacon 2018-06-19 38
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hello,
> A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
> This would result in the upper 32 bits being unintentionally zeroed and
> MSIs getting mapped to incorrect PCI addresses if the address had any
> of the upper bits set.
>
> Replace 32-bit mask by appropriate 64-bit mask.
Applied to controller/rockchip, thank you!
[1/1] PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address
https://git.kernel.org/pci/pci/c/251c859f4b6f
Krzysztof