Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. The commit
3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
had fixed this issue. So, add the essential compatible to also use the
specific data on Stratix10 platform.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Meng Li <[email protected]>
---
v2:
- Add SoC specific compatible as per Krzysztof comment
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 41c9eb51d0ee..46691e72f46b 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -491,7 +491,7 @@ usbphy0: usbphy@0 {
};
usb0: usb@ffb00000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-stratix10-hsotg", "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
@@ -505,7 +505,7 @@ usb0: usb@ffb00000 {
};
usb1: usb@ffb40000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-stratix10-hsotg", "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
--
2.34.1
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Friday, July 21, 2023 4:54 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
> SoCFPGA Stratix10 platform
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
> > On 21/07/2023 10:38, Meng Li wrote:
> >> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> >> the Stratix platform also does not support clock-gating. The commit
> >> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
> >> Agilex") had fixed this issue. So, add the essential compatible to
> >> also use the specific data on Stratix10 platform.
> >>
> >> Acked-by: Krzysztof Kozlowski <[email protected]>
> >
> > From where did you get it?
> >
> > Did you just fake a tag to pass the review?
>
> I just double checked my replies and this for sure never happened.
>
> NAK, don't fake reviews. This very impolite and destroys entire trust.
> The model of upstream collaboration depends on the trust, which is now gone
> for Windriver.
>
No! I don't fake a tag.
In the v1 version, the subject is " usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform"
But it is not reasonable, because the patch is for dts file. So I changed the subject to "arm64: dts: stratix10: "
And add SoC special compatible.
Thanks,
Limeng
> Best regards,
> Krzysztof
On 21/07/2023 11:05, Li, Meng wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Friday, July 21, 2023 4:54 PM
>> To: Li, Meng <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]
>> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
>> SoCFPGA Stratix10 platform
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
>>> On 21/07/2023 10:38, Meng Li wrote:
>>>> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
>>>> the Stratix platform also does not support clock-gating. The commit
>>>> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
>>>> Agilex") had fixed this issue. So, add the essential compatible to
>>>> also use the specific data on Stratix10 platform.
>>>>
>>>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>>
>>> From where did you get it?
>>>
>>> Did you just fake a tag to pass the review?
>>
>> I just double checked my replies and this for sure never happened.
>>
>> NAK, don't fake reviews. This very impolite and destroys entire trust.
>> The model of upstream collaboration depends on the trust, which is now gone
>> for Windriver.
>>
>
> No! I don't fake a tag.
Really? Then I ask second time - from where did you get it? Provide a link.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Friday, July 21, 2023 5:19 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
> SoCFPGA Stratix10 platform
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 21/07/2023 11:05, Li, Meng wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <[email protected]>
> >> Sent: Friday, July 21, 2023 4:54 PM
> >> To: Li, Meng <[email protected]>; [email protected];
> >> [email protected]; [email protected];
> >> [email protected];
> >> [email protected]
> >> Cc: [email protected]
> >> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for
> >> Intel SoCFPGA Stratix10 platform
> >>
> >> CAUTION: This email comes from a non Wind River email account!
> >> Do not click links or open attachments unless you recognize the
> >> sender and know the content is safe.
> >>
> >> On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
> >>> On 21/07/2023 10:38, Meng Li wrote:
> >>>> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP
> >>>> on the Stratix platform also does not support clock-gating. The
> >>>> commit
> >>>> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
> >>>> Agilex") had fixed this issue. So, add the essential compatible to
> >>>> also use the specific data on Stratix10 platform.
> >>>>
> >>>> Acked-by: Krzysztof Kozlowski <[email protected]>
> >>>
> >>> From where did you get it?
> >>>
> >>> Did you just fake a tag to pass the review?
> >>
> >> I just double checked my replies and this for sure never happened.
> >>
> >> NAK, don't fake reviews. This very impolite and destroys entire trust.
> >> The model of upstream collaboration depends on the trust, which is
> >> now gone for Windriver.
> >>
> >
> > No! I don't fake a tag.
>
> Really? Then I ask second time - from where did you get it? Provide a link.
>
https://lore.kernel.org/lkml/[email protected]/T/
thanks,
Limeng
> Best regards,
> Krzysztof
On 21/07/2023 11:29, Li, Meng wrote:
>>>>>> NAK, don't fake reviews. This very impolite and destroys entire trust.
>>>>>> The model of upstream collaboration depends on the trust, which is
>>>>>> now gone for Windriver.
>>>>>>
>>>>>
>>>>> No! I don't fake a tag.
>>>>
>>>> Really? Then I ask second time - from where did you get it? Provide a link.
>>>>
>>>
>>> https://lore.kernel.org/lkml/20230718030851.2014306-1-Meng.Li@windrive
>>> r.com/T/
>>
>> So where is it? You pointed to your email. Where is the tag?
>>
>
> Sorry! Maybe I have wrong understanding about TAG.
> From my perspective, If reviewers ask question or give some advices to the patch, I need to add the tag to v2.
This is some crazy idea. So you want to sprinkle some tags, just because
someone disagrees with your patch and explicitly gives you a NAK, which
means NOT-Ack, Not-acknowledge, not accepted, not in good shape.
I actually wonder why adding an acknowledging tag for the patch, if I
disagreed and gave you NAK. Following your logic, this should be a NAK
tag. This I could understand. But giving acknowledge when I clearly said
patch is wrong?
Read all process documents before submitting new patches:
https://www.kernel.org/doc/html/latest/process/
> If it is not allowed, I apologize for that.
Best regards,
Krzysztof
On 21/07/2023 11:21, Li, Meng wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Friday, July 21, 2023 5:19 PM
>> To: Li, Meng <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]
>> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
>> SoCFPGA Stratix10 platform
>>
>> CAUTION: This email comes from a non Wind River email account!
>> Do not click links or open attachments unless you recognize the sender and
>> know the content is safe.
>>
>> On 21/07/2023 11:05, Li, Meng wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <[email protected]>
>>>> Sent: Friday, July 21, 2023 4:54 PM
>>>> To: Li, Meng <[email protected]>; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected];
>>>> [email protected]
>>>> Cc: [email protected]
>>>> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for
>>>> Intel SoCFPGA Stratix10 platform
>>>>
>>>> CAUTION: This email comes from a non Wind River email account!
>>>> Do not click links or open attachments unless you recognize the
>>>> sender and know the content is safe.
>>>>
>>>> On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
>>>>> On 21/07/2023 10:38, Meng Li wrote:
>>>>>> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP
>>>>>> on the Stratix platform also does not support clock-gating. The
>>>>>> commit
>>>>>> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
>>>>>> Agilex") had fixed this issue. So, add the essential compatible to
>>>>>> also use the specific data on Stratix10 platform.
>>>>>>
>>>>>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>>>>
>>>>> From where did you get it?
>>>>>
>>>>> Did you just fake a tag to pass the review?
>>>>
>>>> I just double checked my replies and this for sure never happened.
>>>>
>>>> NAK, don't fake reviews. This very impolite and destroys entire trust.
>>>> The model of upstream collaboration depends on the trust, which is
>>>> now gone for Windriver.
>>>>
>>>
>>> No! I don't fake a tag.
>>
>> Really? Then I ask second time - from where did you get it? Provide a link.
>>
>
> https://lore.kernel.org/lkml/[email protected]/T/
So where is it? You pointed to your email. Where is the tag?
Best regards,
Krzysztof
On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
> On 21/07/2023 10:38, Meng Li wrote:
>> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
>> the Stratix platform also does not support clock-gating. The commit
>> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
>> had fixed this issue. So, add the essential compatible to also use the
>> specific data on Stratix10 platform.
>>
>> Acked-by: Krzysztof Kozlowski <[email protected]>
>
> From where did you get it?
>
> Did you just fake a tag to pass the review?
I just double checked my replies and this for sure never happened.
NAK, don't fake reviews. This very impolite and destroys entire trust.
The model of upstream collaboration depends on the trust, which is now
gone for Windriver.
Best regards,
Krzysztof
On 21/07/2023 10:38, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. The commit
> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
> had fixed this issue. So, add the essential compatible to also use the
> specific data on Stratix10 platform.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
From where did you get it?
Did you just fake a tag to pass the review?
> Signed-off-by: Meng Li <[email protected]>
> ---
>
> v2:
> - Add SoC specific compatible as per Krzysztof comment
>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 41c9eb51d0ee..46691e72f46b 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -491,7 +491,7 @@ usbphy0: usbphy@0 {
> };
>
> usb0: usb@ffb00000 {
> - compatible = "snps,dwc2";
> + compatible = "intel,socfpga-stratix10-hsotg", "intel,socfpga-agilex-hsotg", "snps,dwc2";
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Friday, July 21, 2023 5:36 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
> SoCFPGA Stratix10 platform
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 21/07/2023 11:29, Li, Meng wrote:
> >>>>>> NAK, don't fake reviews. This very impolite and destroys entire trust.
> >>>>>> The model of upstream collaboration depends on the trust, which
> >>>>>> is now gone for Windriver.
> >>>>>>
> >>>>>
> >>>>> No! I don't fake a tag.
> >>>>
> >>>> Really? Then I ask second time - from where did you get it? Provide a link.
> >>>>
> >>>
> >>> https://lore.kernel.org/lkml/20230718030851.2014306-1-Meng.Li@windri
> >>> ve
> >>> r.com/T/
> >>
> >> So where is it? You pointed to your email. Where is the tag?
> >>
> >
> > Sorry! Maybe I have wrong understanding about TAG.
> > From my perspective, If reviewers ask question or give some advices to the
> patch, I need to add the tag to v2.
>
> This is some crazy idea. So you want to sprinkle some tags, just because
> someone disagrees with your patch and explicitly gives you a NAK, which means
> NOT-Ack, Not-acknowledge, not accepted, not in good shape.
>
> I actually wonder why adding an acknowledging tag for the patch, if I disagreed
> and gave you NAK. Following your logic, this should be a NAK tag. This I could
> understand. But giving acknowledge when I clearly said patch is wrong?
>
Very sorry for wasting your time because of lack of understanding about upstream rules.
And thanks for many explanations patiently, this will help me make progress.
> Read all process documents before submitting new patches:
> https://www.kernel.org/doc/html/latest/process/
>
Ok! I will check these docs.
Thanks,
Limeng
> > If it is not allowed, I apologize for that.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Friday, July 21, 2023 5:23 PM
> To: Li, Meng <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]
> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for Intel
> SoCFPGA Stratix10 platform
>
> CAUTION: This email comes from a non Wind River email account!
> Do not click links or open attachments unless you recognize the sender and
> know the content is safe.
>
> On 21/07/2023 11:21, Li, Meng wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <[email protected]>
> >> Sent: Friday, July 21, 2023 5:19 PM
> >> To: Li, Meng <[email protected]>; [email protected];
> >> [email protected]; [email protected];
> >> [email protected];
> >> [email protected]
> >> Cc: [email protected]
> >> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible for
> >> Intel SoCFPGA Stratix10 platform
> >>
> >> CAUTION: This email comes from a non Wind River email account!
> >> Do not click links or open attachments unless you recognize the
> >> sender and know the content is safe.
> >>
> >> On 21/07/2023 11:05, Li, Meng wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Krzysztof Kozlowski <[email protected]>
> >>>> Sent: Friday, July 21, 2023 4:54 PM
> >>>> To: Li, Meng <[email protected]>; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected];
> >>>> [email protected]
> >>>> Cc: [email protected]
> >>>> Subject: Re: [v2 PATCH] arm64: dts: stratix10: add new compatible
> >>>> for Intel SoCFPGA Stratix10 platform
> >>>>
> >>>> CAUTION: This email comes from a non Wind River email account!
> >>>> Do not click links or open attachments unless you recognize the
> >>>> sender and know the content is safe.
> >>>>
> >>>> On 21/07/2023 10:51, Krzysztof Kozlowski wrote:
> >>>>> On 21/07/2023 10:38, Meng Li wrote:
> >>>>>> Intel Stratix10 is very the same with Agilex platform, the DWC2
> >>>>>> IP on the Stratix platform also does not support clock-gating.
> >>>>>> The commit
> >>>>>> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's
> >>>>>> Agilex") had fixed this issue. So, add the essential compatible
> >>>>>> to also use the specific data on Stratix10 platform.
> >>>>>>
> >>>>>> Acked-by: Krzysztof Kozlowski <[email protected]>
> >>>>>
> >>>>> From where did you get it?
> >>>>>
> >>>>> Did you just fake a tag to pass the review?
> >>>>
> >>>> I just double checked my replies and this for sure never happened.
> >>>>
> >>>> NAK, don't fake reviews. This very impolite and destroys entire trust.
> >>>> The model of upstream collaboration depends on the trust, which is
> >>>> now gone for Windriver.
> >>>>
> >>>
> >>> No! I don't fake a tag.
> >>
> >> Really? Then I ask second time - from where did you get it? Provide a link.
> >>
> >
> > https://lore.kernel.org/lkml/20230718030851.2014306-1-Meng.Li@windrive
> > r.com/T/
>
> So where is it? You pointed to your email. Where is the tag?
>
Sorry! Maybe I have wrong understanding about TAG.
From my perspective, If reviewers ask question or give some advices to the patch, I need to add the tag to v2.
If it is not allowed, I apologize for that.
Thanks,
Limeng
> Best regards,
> Krzysztof