Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.
This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.
Changes have been tested on QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).
Changes in v10:
Refactored phy init/exit/power-on/off functions in dwc3 core
Refactored dwc3-qcom irq registration and handling
Implemented wakeup for multiport irq's
Moved few macros from xhci.h to xhci-ext-caps.h
Fixed nits pointed out in v9
Fixed Co-developed by and SOB tags in patches 5 and 11
Changes in v9:
Added IRQ support for DP/DM/SS MP Irq's of SC8280
Refactored code to read port count by accessing xhci registers
Changes in v8:
Reorganised code in patch-5
Fixed nitpicks in code according to comments received on v7
Fixed indentation in DT patches
Added drive strength for pinctrl nodes in SA8295 DT
Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next
Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.
Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.
Changes in RFC v4:
Added DT support for SA8295p.
Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.
Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
and num_usb3_phy.
Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.
In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.
Tests done on v10:
Enumeration:
/ # lsusb
Bus 003 Device 001: ID 1d6b:0002
Bus 001 Device 001: ID 1d6b:0002
Bus 001 Device 002: ID 045e:0040
Bus 004 Device 001: ID 1d6b:0003
Bus 002 Device 001: ID 1d6b:0003
Bus 001 Device 003: ID 17ef:60d1
Interrupt registration:
/ # cat /proc/interrupts | grep dwc
184: 0 0 0 0 0 0 0 0 PDC 127 Level qcom_dwc3 DP_HS1
185: 0 0 0 0 0 0 0 0 PDC 126 Level qcom_dwc3 DM_HS1
186: 0 0 0 0 0 0 0 0 PDC 16 Level qcom_dwc3 SS1
187: 0 0 0 0 0 0 0 0 PDC 129 Level qcom_dwc3 DP_HS2
188: 0 0 0 0 0 0 0 0 PDC 128 Level qcom_dwc3 DM_HS2
189: 0 0 0 0 0 0 0 0 PDC 17 Level qcom_dwc3 SS2
190: 0 0 0 0 0 0 0 0 PDC 131 Level qcom_dwc3 DP_HS3
191: 0 0 0 0 0 0 0 0 PDC 130 Level qcom_dwc3 DM_HS3
192: 0 0 0 0 0 0 0 0 PDC 133 Level qcom_dwc3 DP_HS4
193: 0 0 0 0 0 0 0 0 PDC 132 Level qcom_dwc3 DM_HS4
195: 0 0 0 0 0 0 0 0 PDC 14 Level qcom_dwc3 DP_HS
196: 0 0 0 0 0 0 0 0 PDC 15 Level qcom_dwc3 DM_HS
197: 0 0 0 0 0 0 0 0 PDC 138 Level qcom_dwc3 SS
198: 32 0 0 0 0 0 0 0 GICv3 835 Leel dwc3
199: 0 0 0 0 0 0 0 0 PDC 12 Level qcom_dwc3 DP_HS
200: 0 0 0 0 0 0 0 0 PDC 13 Level qcom_dwc3 DM_HS
201: 0 0 0 0 0 0 0 0 PDC 136 Level qcom_dwc3 SS
Interrupt connfiguration during suspend entry and suspend exit upon device
connect. Speed here in the following log indicates enum usb_device_speed
in dwc3-qcom.
[ 151.625326] K: dwc3_qcom_enable_interrupts index: 0 speed: 0
[ 151.680985] K: dwc3_qcom_enable_interrupts index: 0 speed: 2
[ 151.686841] K: dwc3_qcom_enable_interrupts index: 1 speed: 2
[ 151.692665] K: dwc3_qcom_enable_interrupts index: 2 speed: 0
[ 151.692678] K: dwc3_qcom_enable_interrupts index: 3 speed: 0
[ 151.724912] K: dwc3_qcom_disable_interrupts index: 0 speed: 2
[ 151.730832] K: dwc3_qcom_disable_interrupts index: 1 speed: 2
[ 151.736740] K: dwc3_qcom_disable_interrupts index: 2 speed: 0
[ 151.742646] K: dwc3_qcom_disable_interrupts index: 3 speed: 0
[ 152.010699] K: dwc3_qcom_disable_interrupts index: 0 speed: 0
[ 152.107836] OOM killer enabled.
[ 152.111070] Restarting tasks ... done.
[ 152.115742] random: crng reseeded on system resumption
[ 152.121298] PM: suspend exit
/ # [ 152.240015] usb 1-3: new low-speed USB device number 8 using xhci-hcd
On SC7280 CRD Herobrine variant, enumeration and wakeup was tested and it
works fine:
Enumeration:
localhost ~ # lsusb
Bus 002 Device 004: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 002 Device 003: ID 05e3:0626 Genesys Logic, Inc. USB3.1 Hub
Bus 002 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.1 Hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 024: ID 046d:c06a Logitech, Inc. USB Optical Mouse
Bus 001 Device 007: ID 05e3:0610 Genesys Logic, Inc. 4-port hub
Bus 001 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.1 Hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
localhost ~ # dmesg | grep hub
[ 3.713331] hub 1-0:1.0: USB hub found
[ 3.717222] hub 1-0:1.0: 1 port detected
[ 3.764330] hub 2-0:1.0: USB hub found
[ 3.768216] hub 2-0:1.0: 1 port detected
[ 4.159720] hub 1-1:1.0: USB hub found
[ 4.165010] hub 1-1:1.0: 4 ports detected
[ 4.322363] hub 2-1:1.0: USB hub found
[ 4.327220] hub 2-1:1.0: 4 ports detected
[ 5.504227] hub 2-1.4:1.0: USB hub found
[ 5.508724] hub 2-1.4:1.0: 4 ports detected
[ 7.263756] hub 1-1.4:1.0: USB hub found
[ 7.268273] hub 1-1.4:1.0: 4 ports detected
[ 10.030906] hub 1-1.4:1.0: USB hub found
[ 10.035352] hub 1-1.4:1.0: 4 ports detected
Interrupt registration on SC7280-CRD:
localhost ~ # cat /proc/interrupts | grep dwc
82: 0 0 0 0 0 0 0 0 GICv3 163 Level qcom_dwc3 HS
211: 0 0 0 0 0 0 0 0 PDC 14 Level qcom_dwc3 DP_HS
212: 0 0 0 0 0 0 0 0 PDC 15 Level qcom_dwc3 DM_HS
213: 0 0 0 0 0 0 0 0 PDC 17 Level qcom_dwc3 SS
Wakeup from system suspend upon mouse click:
[ 1159.589739] K: dwc3_qcom_enable_interrupts port: 0 speed: 3
[ 1160.025300] K: qcom_dwc3_resume_irq irq: 211
[ 1160.149660] K: dwc3_qcom_disable_interrupts port: 0 speed: 3
[ 1161.649610] Resume caused by IRQ 211, qcom_dwc3 DP_HS
Also DT Binding checks were done on both modified yaml files.
Links to previous versions:
Link to v9: https://lore.kernel.org/all/[email protected]/
Link to v8: https://lore.kernel.org/all/[email protected]/
Link to v7: https://lore.kernel.org/all/[email protected]/
Link to v6: https://lore.kernel.org/all/[email protected]/
Link to v5: https://lore.kernel.org/all/[email protected]/
Link to RFC v4: https://lore.kernel.org/all/[email protected]/
Link to RFC v3: https://lore.kernel.org/all/[email protected]/#r
Link to RFC v2: https://lore.kernel.org/all/[email protected]/#r
Andrew Halaney (1):
arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
controller
Harsh Agarwal (1):
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
Krishna Kurapati (9):
dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
dt-bindings: usb: Add bindings for multiport properties on DWC3
controller
usb: dwc3: core: Access XHCI address space temporarily to read port
info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver
usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
ports
.../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 +++
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++
drivers/usb/dwc3/core.c | 326 ++++++++++++----
drivers/usb/dwc3/core.h | 16 +-
drivers/usb/dwc3/drd.c | 15 +-
drivers/usb/dwc3/dwc3-qcom.c | 358 ++++++++++++------
drivers/usb/host/xhci-ext-caps.h | 5 +
drivers/usb/host/xhci.h | 3 -
11 files changed, 714 insertions(+), 203 deletions(-)
--
2.40.0
QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
for all the ports during suspend/resume.
Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/dwc3-qcom.c | 38 ++++++++++++++++++++++++++++++------
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index a98223291306..2db1472eed21 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -37,7 +37,11 @@
#define PIPE3_PHYSTATUS_SW BIT(3)
#define PIPE_UTMI_CLK_DIS BIT(8)
-#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_IRQ1_STAT_REG 0x58
+#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
+#define PWR_EVNT_IRQ3_STAT_REG 0x228
+#define PWR_EVNT_IRQ4_STAT_REG 0x238
+
#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
@@ -121,6 +125,19 @@ enum dwc3_qcom_phy_irq_identifier {
SS_PHY_IRQ,
};
+/*
+ * SA8295 has 4 power event IRQ STAT registers to be checked
+ * during suspend resume.
+ */
+#define NUM_PWR_EVENT_STAT_REGS 4
+
+static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = {
+ PWR_EVNT_IRQ1_STAT_REG,
+ PWR_EVNT_IRQ2_STAT_REG,
+ PWR_EVNT_IRQ3_STAT_REG,
+ PWR_EVNT_IRQ4_STAT_REG,
+};
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -455,15 +472,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
{
+ u8 num_ports;
u32 val;
int i, ret;
if (qcom->is_suspended)
return 0;
- val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
- if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
- dev_err(qcom->dev, "HS-PHY not in L2\n");
+ num_ports = qcom->data->num_ports;
+ for (i = 0; i < num_ports; i++) {
+ val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+ if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+ dev_err(qcom->dev, "HS-PHY not in L2\n");
+ }
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
@@ -486,6 +507,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
{
+ u8 num_ports;
int ret;
int i;
@@ -509,8 +531,12 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
/* Clear existing events from PHY related to L2 in/out */
- dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
- PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+ num_ports = qcom->data->num_ports;
+ for (i = 0; i < num_ports; i++) {
+ dwc3_qcom_setbits(qcom->qscratch_base,
+ pwr_evnt_irq_stat_reg_offset[i],
+ PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+ }
qcom->is_suspended = false;
--
2.40.0
Currently host-only capable DWC3 controllers support Multiport.
Temporarily map XHCI address space for host-only controllers and parse
XHCI Extended Capabilities registers to read number of usb2 ports and
usb3 ports present on multiport controller. Each USB Port is at least HS
capable.
Since the extcaps header is only being used, move port_count related
macros and structure from xhci.h to xhci-ext-caps.h.
The port info for usb2 and usb3 phy are identified as num_usb2_ports
and num_usb3_ports. The intention is as follows:
Wherever we need to perform phy operations like:
LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}
If number of usb2 ports is 3, loop can go from index 0-2 for
usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
if the first 2 ports are SS capable or some other ports like (2 and 3)
are SS capable. So instead, num_usb2_ports is used to loop around all
phy's (both hs and ss) for performing phy operations. If any
usb3_generic_phy turns out to be NULL, phy operation just bails out.
num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.
Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/core.c | 61 ++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 5 +++
drivers/usb/host/xhci-ext-caps.h | 27 ++++++++++++++
drivers/usb/host/xhci.h | 27 --------------
4 files changed, 93 insertions(+), 27 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f6689b731718..edc79ce70588 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -39,6 +39,7 @@
#include "io.h"
#include "debug.h"
+#include "../host/xhci-ext-caps.h"
#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
@@ -1767,6 +1768,51 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
return 0;
}
+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+ void __iomem *base;
+ u8 major_revision;
+ u32 offset = 0;
+ u32 val;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs,
+ * since it is needed to get port info.
+ */
+ base = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ do {
+ offset = xhci_find_next_ext_cap(base, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ if (!offset)
+ break;
+
+ val = readl(base + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(val);
+
+ val = readl(base + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
+ } else {
+ dev_err(dwc->dev,
+ "Unrecognized port major revision %d\n",
+ major_revision);
+ }
+ } while (1);
+
+ dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
+ dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+ iounmap(base);
+
+ return 0;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1774,6 +1820,7 @@ static int dwc3_probe(struct platform_device *pdev)
void __iomem *regs;
struct dwc3 *dwc;
int ret;
+ unsigned int hw_mode;
dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
if (!dwc)
@@ -1854,6 +1901,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto err_disable_clks;
}
+ /*
+ * Currently only DWC3 controllers that are host-only capable
+ * support Multiport.
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_read_port_info(dwc);
+ if (ret)
+ goto err_disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8b1295e4dcdd..0840808e8a40 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1029,6 +1029,8 @@ struct dwc3_scratchpad_array {
* @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
+ * @num_usb2_ports: number of USB2 ports
+ * @num_usb3_ports: number of USB3 ports
* @phys_ready: flag to indicate that PHYs are ready
* @ulpi: pointer to ulpi interface
* @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1168,6 +1170,9 @@ struct dwc3 {
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;
+ u8 num_usb2_ports;
+ u8 num_usb3_ports;
+
bool phys_ready;
struct ulpi *ulpi;
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
index e8af0a125f84..96eb36a58738 100644
--- a/drivers/usb/host/xhci-ext-caps.h
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -79,6 +79,33 @@
/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
#define XHCI_STS_CNR (1 << 11)
+/**
+ * struct xhci_protocol_caps
+ * @revision: major revision, minor revision, capability ID,
+ * and next capability pointer.
+ * @name_string: Four ASCII characters to say which spec this xHC
+ * follows, typically "USB ".
+ * @port_info: Port offset, count, and protocol-defined information.
+ */
+struct xhci_protocol_caps {
+ u32 revision;
+ u32 name_string;
+ u32 port_info;
+};
+
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
+#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
+#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+
+#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
+#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
+#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
+#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
+#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
+#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
+
#include <linux/io.h>
/**
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 7e282b4522c0..77016338bee1 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -558,33 +558,6 @@ struct xhci_doorbell_array {
#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
#define DB_VALUE_HOST 0x00000000
-/**
- * struct xhci_protocol_caps
- * @revision: major revision, minor revision, capability ID,
- * and next capability pointer.
- * @name_string: Four ASCII characters to say which spec this xHC
- * follows, typically "USB ".
- * @port_info: Port offset, count, and protocol-defined information.
- */
-struct xhci_protocol_caps {
- u32 revision;
- u32 name_string;
- u32 port_info;
-};
-
-#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
-#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
-#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
-#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
-#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
-
-#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
-#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
-#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
-#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
-#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
-#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
-
#define PLT_MASK (0x03 << 6)
#define PLT_SYM (0x00 << 6)
#define PLT_ASYM_RX (0x02 << 6)
--
2.40.0
From: Andrew Halaney <[email protected]>
There is now support for the multiport USB controller this uses so
enable it.
The board only has a single port hooked up (despite it being wired up to
the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
which by default on boot is selected to mux properly. Grab the gpio
controlling that and ensure it stays in the right position so USB 2.0
continues to be routed from the external port to the SoC.
Co-developed-by: Andrew Halaney <[email protected]>
Signed-off-by: Andrew Halaney <[email protected]>
[Krishna: Rebased on top of usb-next]
Co-developed-by: Krishna Kurapati <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 5a26974dcf8f..69f6b13e6197 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -488,6 +488,19 @@ &usb_2_qmpphy0 {
status = "okay";
};
+&usb_2 {
+ pinctrl-0 = <&usb2_en_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+ phy-names = "usb2-port0", "usb3-port0";
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
@@ -640,4 +653,13 @@ wake-pins {
bias-pull-up;
};
};
+
+ usb2_en_state: usb2-en-state {
+ /* TS3USB221A USB2.0 mux select */
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
};
--
2.40.0
Add bindings to indicate properties required to support multiport
on Synopsys DWC3 controller.
Suggested-by: Bjorn Andersson <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index a696f23730d3..5bc941355b43 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -85,15 +85,16 @@ properties:
phys:
minItems: 1
- maxItems: 2
+ maxItems: 8
phy-names:
minItems: 1
- maxItems: 2
- items:
- enum:
- - usb2-phy
- - usb3-phy
+ maxItems: 8
+ oneOf:
+ - items:
+ enum: [ usb2-phy, usb3-phy ]
+ - items:
+ pattern: "^usb[23]-port[0-3]$"
power-domains:
description:
--
2.40.0
Enable tertiary controller for SA8295P (based on SC8280XP).
Add pinctrl support for usb ports to provide VBUS to connected peripherals.
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 ++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index fd253942e5e5..473fe858fbed 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sa8540p.dtsi"
#include "sa8540p-pmics.dtsi"
@@ -584,6 +585,20 @@ &usb_1_qmpphy {
status = "okay";
};
+&usb_2 {
+ pinctrl-0 = <&usb2_en_state>,
+ <&usb3_en_state>,
+ <&usb4_en_state>,
+ <&usb5_en_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
&usb_2_hsphy0 {
vdda-pll-supply = <&vreg_l5a>;
vdda18-supply = <&vreg_l7g>;
@@ -729,3 +744,41 @@ wake-n-pins {
};
};
};
+
+&pmm8540c_gpios {
+ usb2_en_state: usb2-en-state {
+ pins = "gpio9";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540e_gpios {
+ usb3_en_state: usb3-en-state {
+ pins = "gpio5";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540g_gpios {
+ usb4_en_state: usb4-en-state {
+ pins = "gpio5";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+
+ usb5_en_state: usb5-en-state {
+ pins = "gpio9";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
--
2.40.0
On Fri, Jul 28, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
>
> Since the extcaps header is only being used, move port_count related
> macros and structure from xhci.h to xhci-ext-caps.h.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 61 ++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 5 +++
> drivers/usb/host/xhci-ext-caps.h | 27 ++++++++++++++
> drivers/usb/host/xhci.h | 27 --------------
> 4 files changed, 93 insertions(+), 27 deletions(-)
Please split the moving of code for xhci in a separate commit.
Thanks,
Thinh