2023-08-14 13:37:01

by Sriranjani P

Subject: [PATCH v3 0/4] net: stmmac: dwc-qos: Add FSD EQoS support

FSD platform has two instances of EQoS IP, one is in FSYS0 block and
another one is in PERIC block. This patch series add required DT binding,
DT file modifications and platform driver specific changes for the same.

Changes since v2:
1. Addressed all the review comments suggested by Krzysztof with respect to
DT binding and DTS files.
2. Added SOB Swathi for her contributions in this patch.

Sriranjani P (4):
dt-bindings: net: Add FSD EQoS device tree bindings
net: stmmac: dwc-qos: Add FSD EQoS support
arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoC
arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC

.../devicetree/bindings/net/snps,dwmac.yaml | 5 +-
.../devicetree/bindings/net/tesla,ethqos.yaml | 114 ++++++++++++
arch/arm64/boot/dts/tesla/fsd-evb.dts | 18 ++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 112 ++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 51 ++++++
.../stmicro/stmmac/dwmac-dwc-qos-eth.c | 172 ++++++++++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 28 ++-
include/linux/stmmac.h | 1 +
8 files changed, 497 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/tesla,ethqos.yaml

--
2.17.1

2023-08-14 14:02:09

by Sriranjani P

Subject: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

The FSD SoC contains two instance of the Synopsys DWC ethernet QOS IP core.
The binding that it uses is slightly different from existing ones because
of the integration (clocks, resets).

For FSD SoC, a mux switch is needed between internal and external clocks.
By default after reset internal clock is used but for receiving packets
properly, external clock is needed. Mux switch to external clock happens
only when the external clock is present.

Signed-off-by: Chandrasekar R <[email protected]>
Signed-off-by: Suresh Siddha <[email protected]>
Signed-off-by: Swathi K S <[email protected]>
Signed-off-by: Sriranjani P <[email protected]>
---
.../stmicro/stmmac/dwmac-dwc-qos-eth.c | 172 ++++++++++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 28 ++-
include/linux/stmmac.h | 1 +
3 files changed, 199 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
index 61ebf36da13d..651a41e0dab9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/stmmac.h>
+#include <linux/regmap.h>

#include "stmmac_platform.h"
#include "dwmac4.h"
@@ -37,6 +38,45 @@ struct tegra_eqos {
struct gpio_desc *reset;
};

+enum fsd_rxmux_clk {
+ FSD_RXCLK_MUX = 7,
+ FSD_RXCLK_EXTERNAL,
+ FSD_RXCLK_INTERNAL
+};
+
+struct fsd_eqos_plat_data {
+ const struct fsd_eqos_variant *fsd_eqos_inst_var;
+ struct clk_bulk_data *clks;
+ struct device *dev;
+};
+
+struct fsd_eqos_variant {
+ const char * const *clk_list;
+ int num_clks;
+};
+
+static const char * const fsd_eqos_instance_0_clk[] = {
+ "ptp_ref", "master_bus", "slave_bus", "tx", "rx"
+};
+
+static const char * const fsd_eqos_instance_1_clk[] = {
+ "ptp_ref", "master_bus", "slave_bus", "tx", "rx", "master2_bus",
+ "slave2_bus", "eqos_rxclk_mux", "eqos_phyrxclk", "dout_peric_rgmii_clk"
+};
+
+static const int rx_clock_skew_val[] = {0x2, 0x0};
+
+static const struct fsd_eqos_variant fsd_eqos_clk_info[] = {
+ {
+ .clk_list = fsd_eqos_instance_0_clk,
+ .num_clks = ARRAY_SIZE(fsd_eqos_instance_0_clk)
+ },
+ {
+ .clk_list = fsd_eqos_instance_1_clk,
+ .num_clks = ARRAY_SIZE(fsd_eqos_instance_1_clk)
+ },
+};
+
static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
struct plat_stmmacenet_data *plat_dat)
{
@@ -265,6 +305,132 @@ static int tegra_eqos_init(struct platform_device *pdev, void *priv)
return 0;
}

+static int dwc_eqos_rxmux_setup(void *priv, bool external)
+{
+ struct fsd_eqos_plat_data *plat = priv;
+
+ /* doesn't support RX clock mux */
+ if (!plat->clks[FSD_RXCLK_MUX].clk)
+ return 0;
+
+ if (external)
+ return clk_set_parent(plat->clks[FSD_RXCLK_MUX].clk,
+ plat->clks[FSD_RXCLK_EXTERNAL].clk);
+ else
+ return clk_set_parent(plat->clks[FSD_RXCLK_MUX].clk,
+ plat->clks[FSD_RXCLK_INTERNAL].clk);
+}
+
+static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int ins_num)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct regmap *syscon;
+ unsigned int reg;
+
+ if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
+ syscon = syscon_regmap_lookup_by_phandle_args(np,
+ "fsd-rx-clock-skew",
+ 1, &reg);
+ if (IS_ERR(syscon)) {
+ dev_err(&pdev->dev,
+ "couldn't get the rx-clock-skew syscon!\n");
+ return PTR_ERR(syscon);
+ }
+
+ regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
+ }
+
+ return 0;
+}
+
+static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat,
+ struct plat_stmmacenet_data *data)
+{
+ int ret = 0, i;
+
+ const struct fsd_eqos_variant *fsd_eqos_v_data =
+ plat->fsd_eqos_inst_var;
+
+ plat->clks = devm_kcalloc(plat->dev, fsd_eqos_v_data->num_clks,
+ sizeof(*plat->clks), GFP_KERNEL);
+ if (!plat->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < fsd_eqos_v_data->num_clks; i++)
+ plat->clks[i].id = fsd_eqos_v_data->clk_list[i];
+
+ ret = devm_clk_bulk_get(plat->dev, fsd_eqos_v_data->num_clks,
+ plat->clks);
+
+ return ret;
+}
+
+static int fsd_clks_endisable(void *priv, bool enabled)
+{
+ int ret, num_clks;
+ struct fsd_eqos_plat_data *plat = priv;
+
+ num_clks = plat->fsd_eqos_inst_var->num_clks;
+
+ if (enabled) {
+ ret = clk_bulk_prepare_enable(num_clks, plat->clks);
+ if (ret) {
+ dev_err(plat->dev, "Clock enable failed, err = %d\n", ret);
+ return ret;
+ }
+ } else {
+ clk_bulk_disable_unprepare(num_clks, plat->clks);
+ }
+
+ return 0;
+}
+
+static int fsd_eqos_probe(struct platform_device *pdev,
+ struct plat_stmmacenet_data *data,
+ struct stmmac_resources *res)
+{
+ struct fsd_eqos_plat_data *priv_plat;
+ struct device_node *np = pdev->dev.of_node;
+ int ret = 0;
+
+ priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
+ if (!priv_plat) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ priv_plat->dev = &pdev->dev;
+ data->bus_id = of_alias_get_id(np, "eth");
+
+ priv_plat->fsd_eqos_inst_var = &fsd_eqos_clk_info[data->bus_id];
+
+ ret = fsd_eqos_clk_init(priv_plat, data);
+
+ data->bsp_priv = priv_plat;
+ data->clks_config = fsd_clks_endisable;
+ data->rxmux_setup = dwc_eqos_rxmux_setup;
+
+ ret = fsd_clks_endisable(priv_plat, true);
+ if (ret)
+ goto error;
+
+ ret = dwc_eqos_setup_rxclock(pdev, data->bus_id);
+ if (ret) {
+ fsd_clks_endisable(priv_plat, false);
+ dev_err_probe(&pdev->dev, ret, "Unable to setup rxclock\n");
+ }
+
+error:
+ return ret;
+}
+
+static void fsd_eqos_remove(struct platform_device *pdev)
+{
+ struct fsd_eqos_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev);
+
+ fsd_clks_endisable(priv_plat, false);
+}
+
static int tegra_eqos_probe(struct platform_device *pdev,
struct plat_stmmacenet_data *data,
struct stmmac_resources *res)
@@ -411,6 +577,11 @@ static const struct dwc_eth_dwmac_data tegra_eqos_data = {
.remove = tegra_eqos_remove,
};

+static const struct dwc_eth_dwmac_data fsd_eqos_data = {
+ .probe = fsd_eqos_probe,
+ .remove = fsd_eqos_remove,
+};
+
static int dwc_eth_dwmac_probe(struct platform_device *pdev)
{
const struct dwc_eth_dwmac_data *data;
@@ -482,6 +653,7 @@ static void dwc_eth_dwmac_remove(struct platform_device *pdev)
static const struct of_device_id dwc_eth_dwmac_match[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
{ .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
+ { .compatible = "tesla,dwc-qos-ethernet-4.21", .data = &fsd_eqos_data },
{ }
};
MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 733b5e900817..3c7d55786aaa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3883,6 +3883,12 @@ static int __stmmac_open(struct net_device *dev,
netif_tx_start_all_queues(priv->dev);
stmmac_enable_all_dma_irq(priv);

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, true);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
return 0;

irq_error:
@@ -3936,7 +3942,13 @@ static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
static int stmmac_release(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
- u32 chan;
+ u32 chan, ret;
+
+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, false);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }

if (device_may_wakeup(priv->device))
phylink_speed_down(priv->phylink, false);
@@ -7630,11 +7642,17 @@ int stmmac_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
- u32 chan;
+ u32 chan, ret;

if (!ndev || !netif_running(ndev))
return 0;

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, false);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
mutex_lock(&priv->lock);

netif_device_detach(ndev);
@@ -7799,6 +7817,12 @@ int stmmac_resume(struct device *dev)
mutex_unlock(&priv->lock);
rtnl_unlock();

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, true);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
netif_device_attach(ndev);

return 0;
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 784277d666eb..69150c8c8df7 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -264,6 +264,7 @@ struct plat_stmmacenet_data {
void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
int (*init)(struct platform_device *pdev, void *priv);
void (*exit)(struct platform_device *pdev, void *priv);
+ int (*rxmux_setup)(void *priv, bool external);
struct mac_device_info *(*setup)(void *priv);
int (*clks_config)(void *priv, bool enabled);
int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
--
2.17.1

2023-08-14 15:49:50

by Sriranjani P

Subject: [PATCH v3 4/4] arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC

The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in
FSYS0 block and other in PERIC block.

Adds device tree node for Ethernet in PERIC Block and enables the same for
FSD platform.

Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Jayati Sahu <[email protected]>
Signed-off-by: Swathi K S <[email protected]>
Signed-off-by: Sriranjani P <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 29 +++++++++++
3 files changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 2c37097c709a..80ca120b3d7f 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -73,6 +73,15 @@
};
};

+&ethernet_1 {
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&fin_pll {
clock-frequency = <24000000>;
};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index cb437483ff6e..6f4658f57453 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -437,6 +437,62 @@
samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
+
+ eth1_tx_clk: eth1-tx-clk-pins {
+ samsung,pins = "gpf2-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_tx_data: eth1-tx-data-pins {
+ samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_tx_ctrl: eth1-tx-ctrl-pins {
+ samsung,pins = "gpf2-5";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_phy_intr: eth1-phy-intr-pins {
+ samsung,pins = "gpf2-6";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ eth1_rx_clk: eth1-rx-clk-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_rx_data: eth1-rx-data-pins {
+ samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_rx_ctrl: eth1-rx-ctrl-pins {
+ samsung,pins = "gpf3-5";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth1_mdio: eth1-mdio-pins {
+ samsung,pins = "gpf3-6", "gpf3-7";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
};

&pinctrl_pmu {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 9a991f021711..ce5d5f8546b9 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -33,6 +33,7 @@
spi1 = &spi_1;
spi2 = &spi_2;
eth0 = &ethernet_0;
+ eth1 = &ethernet_1;
};

cpus {
@@ -1006,6 +1007,34 @@
phy-mode = "rgmii";
status = "disabled";
};
+
+ ethernet_1: ethernet@14300000 {
+ compatible = "tesla,dwc-qos-ethernet-4.21";
+ reg = <0x0 0x14300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
+ <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK>,
+ <&clock_peric PERIC_DOUT_RGMII_CLK>;
+ clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx",
+ "master2_bus", "slave2_bus", "eqos_rxclk_mux",
+ "eqos_phyrxclk", "dout_peric_rgmii_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
+ <&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
+ <&eth1_rx_ctrl>, <&eth1_mdio>;
+ local-mac-address = [00 00 00 00 00 00];
+ fsd-rx-clock-skew = <&sysreg_peric 0x10>;
+ iommus = <&smmu_peric 0x0 0x1>;
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
};
};

--
2.17.1

2023-08-19 19:19:50

by Krzysztof Kozlowski

Subject: Re: [PATCH v3 4/4] arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC

On 14/08/2023 21:41, Krzysztof Kozlowski wrote:
> On 14/08/2023 13:25, Sriranjani P wrote:
>> The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in
>> FSYS0 block and other in PERIC block.
>>
>> Adds device tree node for Ethernet in PERIC Block and enables the same for
>> FSD platform.
>>
>> Signed-off-by: Pankaj Dubey <[email protected]>
>> Signed-off-by: Jayati Sahu <[email protected]>
>> Signed-off-by: Swathi K S <[email protected]>
>> Signed-off-by: Sriranjani P <[email protected]>
>> ---
>> arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++
>> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++
>> arch/arm64/boot/dts/tesla/fsd.dtsi | 29 +++++++++++
>> 3 files changed, 94 insertions(+)
>
> Looks duplicated.

Ah, not, it's another block.

My question whether this was tested remains...

Best regards,
Krzysztof

2023-08-20 20:06:23

by Sriranjani P

Subject: RE: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:[email protected]]
> Sent: 15 August 2023 01:21
> To: Sriranjani P <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-arm-
> [email protected]; Chandrasekar R <[email protected]>;
> Suresh Siddha <[email protected]>
> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
>
> On 14/08/2023 13:25, Sriranjani P wrote:
> > The FSD SoC contains two instance of the Synopsys DWC ethernet QOS IP
> core.
> > The binding that it uses is slightly different from existing ones
> > because of the integration (clocks, resets).
> >
> > For FSD SoC, a mux switch is needed between internal and external clocks.
> > By default after reset internal clock is used but for receiving
> > packets properly, external clock is needed. Mux switch to external
> > clock happens only when the external clock is present.
> >
> > Signed-off-by: Chandrasekar R <[email protected]>
> > Signed-off-by: Suresh Siddha <[email protected]>
> > Signed-off-by: Swathi K S <[email protected]>
> > Signed-off-by: Sriranjani P <[email protected]>
> > ---
>
>
> > +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
> > +ins_num) {
> > + struct device_node *np = pdev->dev.of_node;
> > + struct regmap *syscon;
> > + unsigned int reg;
> > +
> > + if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
> > + syscon = syscon_regmap_lookup_by_phandle_args(np,
> > + "fsd-rx-clock-
> skew",
> > + 1, &reg);
> > + if (IS_ERR(syscon)) {
> > + dev_err(&pdev->dev,
> > + "couldn't get the rx-clock-skew syscon!\n");
> > + return PTR_ERR(syscon);
> > + }
> > +
> > + regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat,
> > + struct plat_stmmacenet_data *data) {
> > + int ret = 0, i;
> > +
> > + const struct fsd_eqos_variant *fsd_eqos_v_data =
> > + plat->fsd_eqos_inst_var;
> > +
> > + plat->clks = devm_kcalloc(plat->dev, fsd_eqos_v_data->num_clks,
> > + sizeof(*plat->clks), GFP_KERNEL);
> > + if (!plat->clks)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < fsd_eqos_v_data->num_clks; i++)
> > + plat->clks[i].id = fsd_eqos_v_data->clk_list[i];
> > +
> > + ret = devm_clk_bulk_get(plat->dev, fsd_eqos_v_data->num_clks,
> > + plat->clks);
>
> Instead of duplicating entire clock management with existing code, you
> should extend/rework existing one.
>
> This code is unfortunately great example how not to stuff vendor code into
> upstream project. :(

I will check again if I can extend existing one to support FSD platform specific requirement.

>
> > +
> > + return ret;
> > +}
> > +
> > +static int fsd_clks_endisable(void *priv, bool enabled) {
> > + int ret, num_clks;
> > + struct fsd_eqos_plat_data *plat = priv;
> > +
> > + num_clks = plat->fsd_eqos_inst_var->num_clks;
> > +
> > + if (enabled) {
> > + ret = clk_bulk_prepare_enable(num_clks, plat->clks);
> > + if (ret) {
> > + dev_err(plat->dev, "Clock enable failed, err = %d\n",
> ret);
> > + return ret;
> > + }
> > + } else {
> > + clk_bulk_disable_unprepare(num_clks, plat->clks);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int fsd_eqos_probe(struct platform_device *pdev,
> > + struct plat_stmmacenet_data *data,
> > + struct stmmac_resources *res)
> > +{
> > + struct fsd_eqos_plat_data *priv_plat;
> > + struct device_node *np = pdev->dev.of_node;
> > + int ret = 0;
> > +
> > + priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat),
> GFP_KERNEL);
> > + if (!priv_plat) {
> > + ret = -ENOMEM;
>
> return -ENOMEM

Will fix this in v4.

>
> > + goto error;
> > + }
> > +
> > + priv_plat->dev = &pdev->dev;
> > + data->bus_id = of_alias_get_id(np, "eth");
>
> No, you cannot do like this. Aliases are board specific and are based on
> labeling on the board.

So if I understood this correctly, I need to move alias in the board specific DTS file and I can use this, because we have to handle rx-clock-skew differently for the two instances in the FSD platform. Another approach we took in v1, by specifying the value to be programmed in rx-clock-skew property itself, but it seems it is not a preferred approach.
I can see that in drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +436 common code is already using this API and getting alias id, so I can probably use the same rather getting same again here, but I have to specify alias in DTS file.

>
> > +
> > + priv_plat->fsd_eqos_inst_var = &fsd_eqos_clk_info[data->bus_id];
> > +
> > + ret = fsd_eqos_clk_init(priv_plat, data);
> > +
> > + data->bsp_priv = priv_plat;
> > + data->clks_config = fsd_clks_endisable;
> > + data->rxmux_setup = dwc_eqos_rxmux_setup;
> > +
> > + ret = fsd_clks_endisable(priv_plat, true);
> > + if (ret)
> > + goto error;
> > +
> > + ret = dwc_eqos_setup_rxclock(pdev, data->bus_id);
> > + if (ret) {
> > + fsd_clks_endisable(priv_plat, false);
> > + dev_err_probe(&pdev->dev, ret, "Unable to setup
> rxclock\n");
>
> The syntax is: return dev_err_probe().

Will fix it in v4.

>
> > + }
> > +
> > +error:
> > + return ret;
> > +}
>
> ....
>
>
> Best regards,
> Krzysztof

2024-06-06 10:12:09

by Swathi K S

Subject: RE: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

> -----Original Message-----
> From: Andrew Lunn [mailto:[email protected]]
> Sent: 15 August 2023 02:17
> To: Sriranjani P <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-samsung-
> [email protected]; [email protected]; Chandrasekar R
> <[email protected]>; Suresh Siddha <[email protected]>
> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
>
> > +static const int rx_clock_skew_val[] = {0x2, 0x0};
>
> > +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
> > +ins_num) {
> > + struct device_node *np = pdev->dev.of_node;
> > + struct regmap *syscon;
> > + unsigned int reg;
> > +
> > + if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
> > + syscon = syscon_regmap_lookup_by_phandle_args(np,
> > + "fsd-rx-clock-
> skew",
> > + 1, &reg);
> > + if (IS_ERR(syscon)) {
> > + dev_err(&pdev->dev,
> > + "couldn't get the rx-clock-skew syscon!\n");
> > + return PTR_ERR(syscon);
> > + }
> > +
> > + regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
>
> Please could you explain what this is doing.

As per customer requirement, we need to provide a delay of 2ns in FSYS in
both TX and RX path and no delay in peric block

>
> Andrew

Regards,
Swathi

2024-06-06 10:17:21

by Swathi K S

Subject: RE: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:[email protected]]
> Sent: 18 August 2023 14:57
> To: Sriranjani P <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-arm-
> [email protected]; 'Chandrasekar R' <[email protected]>;
> 'Suresh Siddha' <[email protected]>
> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
>
> On 16/08/2023 08:38, Sriranjani P wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski [mailto:[email protected]]
> >> Sent: 15 August 2023 01:21
> >> To: Sriranjani P <[email protected]>; [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; [email protected]; linux-
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]
> >> Cc: [email protected]; [email protected]; linux-
> >> [email protected]; [email protected]; linux-arm-
> >> [email protected]; Chandrasekar R <[email protected]>;
> >> Suresh Siddha <[email protected]>
> >> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS
> >> support
> >>
> >> On 14/08/2023 13:25, Sriranjani P wrote:
> >>> The FSD SoC contains two instance of the Synopsys DWC ethernet QOS
> >>> IP
> >> core.
> >>> The binding that it uses is slightly different from existing ones
> >>> because of the integration (clocks, resets).
> >>>
> >>> For FSD SoC, a mux switch is needed between internal and external
> clocks.
> >>> By default after reset internal clock is used but for receiving
> >>> packets properly, external clock is needed. Mux switch to external
> >>> clock happens only when the external clock is present.
> >>>
> >>> Signed-off-by: Chandrasekar R <[email protected]>
> >>> Signed-off-by: Suresh Siddha <[email protected]>
> >>> Signed-off-by: Swathi K S <[email protected]>
> >>> Signed-off-by: Sriranjani P <[email protected]>
> >>> ---
> >>
> >>
> >>> +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
> >>> +ins_num) {
> >>> + struct device_node *np = pdev->dev.of_node;
> >>> + struct regmap *syscon;
> >>> + unsigned int reg;
> >>> +
> >>> + if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
> >>> + syscon = syscon_regmap_lookup_by_phandle_args(np,
> >>> + "fsd-rx-clock-
> >> skew",
> >>> + 1, &reg);
> >>> + if (IS_ERR(syscon)) {
> >>> + dev_err(&pdev->dev,
> >>> + "couldn't get the rx-clock-skew syscon!\n");
> >>> + return PTR_ERR(syscon);
> >>> + }
> >>> +
> >>> + regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat,
> >>> + struct plat_stmmacenet_data *data) {
> >>> + int ret = 0, i;
> >>> +
> >>> + const struct fsd_eqos_variant *fsd_eqos_v_data =
> >>> + plat->fsd_eqos_inst_var;
> >>> +
> >>> + plat->clks = devm_kcalloc(plat->dev, fsd_eqos_v_data->num_clks,
> >>> + sizeof(*plat->clks), GFP_KERNEL);
> >>> + if (!plat->clks)
> >>> + return -ENOMEM;
> >>> +
> >>> + for (i = 0; i < fsd_eqos_v_data->num_clks; i++)
> >>> + plat->clks[i].id = fsd_eqos_v_data->clk_list[i];
> >>> +
> >>> + ret = devm_clk_bulk_get(plat->dev, fsd_eqos_v_data->num_clks,
> >>> + plat->clks);
> >>
> >> Instead of duplicating entire clock management with existing code,
> >> you should extend/rework existing one.
> >>
> >> This code is unfortunately great example how not to stuff vendor code
> >> into upstream project. :(
> >
> > I will check again if I can extend existing one to support FSD platform
> specific requirement.
> >
> >>
> >>> +
> >>> + return ret;
> >>> +}
> >>> +
> >>> +static int fsd_clks_endisable(void *priv, bool enabled) {
> >>> + int ret, num_clks;
> >>> + struct fsd_eqos_plat_data *plat = priv;
> >>> +
> >>> + num_clks = plat->fsd_eqos_inst_var->num_clks;
> >>> +
> >>> + if (enabled) {
> >>> + ret = clk_bulk_prepare_enable(num_clks, plat->clks);
> >>> + if (ret) {
> >>> + dev_err(plat->dev, "Clock enable failed, err = %d\n",
> >> ret);
> >>> + return ret;
> >>> + }
> >>> + } else {
> >>> + clk_bulk_disable_unprepare(num_clks, plat->clks);
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int fsd_eqos_probe(struct platform_device *pdev,
> >>> + struct plat_stmmacenet_data *data,
> >>> + struct stmmac_resources *res)
> >>> +{
> >>> + struct fsd_eqos_plat_data *priv_plat;
> >>> + struct device_node *np = pdev->dev.of_node;
> >>> + int ret = 0;
> >>> +
> >>> + priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat),
> >> GFP_KERNEL);
> >>> + if (!priv_plat) {
> >>> + ret = -ENOMEM;
> >>
> >> return -ENOMEM
> >
> > Will fix this in v4.
> >
> >>
> >>> + goto error;
> >>> + }
> >>> +
> >>> + priv_plat->dev = &pdev->dev;
> >>> + data->bus_id = of_alias_get_id(np, "eth");
> >>
> >> No, you cannot do like this. Aliases are board specific and are based
> >> on labeling on the board.
> >
> > So if I understood this correctly, I need to move alias in the board
> > specific DTS file
>
> This part: yes
>
> > and I can use this, because we have to handle rx-clock-skew differently for
> the two instances in the FSD platform.
>
> Not really. Do you expect it to work correctly if given EQoS instance receives
> different alias, e.g. 5?
>
> > Another approach we took in v1, by specifying the value to be programmed
> in rx-clock-skew property itself, but it seems it is not a preferred approach.
> > I can see that in drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +436 common code is already using this API and getting alias id, so I can
> probably use the same rather getting same again here, but I have to specify
> alias in DTS file.
>
> Getting alias ID is okay in general. It is used to provide user-visible ID of the
> devices (see mmc). Using such alias to configure hardware is abuse of the
> alias, because of the reasons I said - how is it supposed to work if alias is 5
> (this is perfectly valid alias)?
>
> I suspect that all this is to substitute missing abstractions, like clocks, phys or
> resets...

Will avoid using the API to get alias id to configure the HW. Will share the new implementation in v4.

>
> Best regards,
> Krzysztof


Regards,
Swathi

2024-06-06 12:17:39

by Krzysztof Kozlowski

Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

On 06/06/2024 11:14, Swathi K S wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: 18 August 2023 14:57
>> To: Sriranjani P <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; linux-
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected]; linux-
>> [email protected]; [email protected]; linux-arm-
>> [email protected]; 'Chandrasekar R' <[email protected]>;
>> 'Suresh Siddha' <[email protected]>
>> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
>>
>> On 16/08/2023 08:38, Sriranjani P wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski [mailto:[email protected]]
>>>> Sent: 15 August 2023 01:21
>>>> To: Sriranjani P <[email protected]>; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected]; linux-
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]
>>>> Cc: [email protected]; [email protected]; linux-
>>>> [email protected]; [email protected]; linux-arm-
>>>> [email protected]; Chandrasekar R <[email protected]>;
>>>> Suresh Siddha <[email protected]>
>>>> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS
>>>> support
>>>>
>>>> On 14/08/2023 13:25, Sriranjani P wrote:
>>>>> The FSD SoC contains two instance of the Synopsys DWC ethernet QOS
>>>>> IP
>>>> core.
>>>>> The binding that it uses is slightly different from existing ones
>>>>> because of the integration (clocks, resets).
>>>>>
>>>>> For FSD SoC, a mux switch is needed between internal and external
>> clocks.
>>>>> By default after reset internal clock is used but for receiving
>>>>> packets properly, external clock is needed. Mux switch to external
>>>>> clock happens only when the external clock is present.
>>>>>
>>>>> Signed-off-by: Chandrasekar R <[email protected]>
>>>>> Signed-off-by: Suresh Siddha <[email protected]>
>>>>> Signed-off-by: Swathi K S <[email protected]>
>>>>> Signed-off-by: Sriranjani P <[email protected]>
>>>>> ---
>>>>
>>>>
>>>>> +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
>>>>> +ins_num) {
>>>>> + struct device_node *np = pdev->dev.of_node;
>>>>> + struct regmap *syscon;
>>>>> + unsigned int reg;
>>>>> +
>>>>> + if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
>>>>> + syscon = syscon_regmap_lookup_by_phandle_args(np,
>>>>> + "fsd-rx-clock-
>>>> skew",
>>>>> + 1, &reg);
>>>>> + if (IS_ERR(syscon)) {
>>>>> + dev_err(&pdev->dev,
>>>>> + "couldn't get the rx-clock-skew syscon!\n");
>>>>> + return PTR_ERR(syscon);
>>>>> + }
>>>>> +
>>>>> + regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat,
>>>>> + struct plat_stmmacenet_data *data) {
>>>>> + int ret = 0, i;
>>>>> +
>>>>> + const struct fsd_eqos_variant *fsd_eqos_v_data =
>>>>> + plat->fsd_eqos_inst_var;
>>>>> +
>>>>> + plat->clks = devm_kcalloc(plat->dev, fsd_eqos_v_data->num_clks,
>>>>> + sizeof(*plat->clks), GFP_KERNEL);
>>>>> + if (!plat->clks)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + for (i = 0; i < fsd_eqos_v_data->num_clks; i++)
>>>>> + plat->clks[i].id = fsd_eqos_v_data->clk_list[i];
>>>>> +
>>>>> + ret = devm_clk_bulk_get(plat->dev, fsd_eqos_v_data->num_clks,
>>>>> + plat->clks);
>>>>
>>>> Instead of duplicating entire clock management with existing code,
>>>> you should extend/rework existing one.
>>>>
>>>> This code is unfortunately great example how not to stuff vendor code
>>>> into upstream project. :(
>>>
>>> I will check again if I can extend existing one to support FSD platform
>> specific requirement.
>>>
>>>>
>>>>> +
>>>>> + return ret;
>>>>> +}
>>>>> +
>>>>> +static int fsd_clks_endisable(void *priv, bool enabled) {
>>>>> + int ret, num_clks;
>>>>> + struct fsd_eqos_plat_data *plat = priv;
>>>>> +
>>>>> + num_clks = plat->fsd_eqos_inst_var->num_clks;
>>>>> +
>>>>> + if (enabled) {
>>>>> + ret = clk_bulk_prepare_enable(num_clks, plat->clks);
>>>>> + if (ret) {
>>>>> + dev_err(plat->dev, "Clock enable failed, err = %d\n",
>>>> ret);
>>>>> + return ret;
>>>>> + }
>>>>> + } else {
>>>>> + clk_bulk_disable_unprepare(num_clks, plat->clks);
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int fsd_eqos_probe(struct platform_device *pdev,
>>>>> + struct plat_stmmacenet_data *data,
>>>>> + struct stmmac_resources *res)
>>>>> +{
>>>>> + struct fsd_eqos_plat_data *priv_plat;
>>>>> + struct device_node *np = pdev->dev.of_node;
>>>>> + int ret = 0;
>>>>> +
>>>>> + priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat),
>>>> GFP_KERNEL);
>>>>> + if (!priv_plat) {
>>>>> + ret = -ENOMEM;
>>>>
>>>> return -ENOMEM
>>>
>>> Will fix this in v4.
>>>
>>>>
>>>>> + goto error;
>>>>> + }
>>>>> +
>>>>> + priv_plat->dev = &pdev->dev;
>>>>> + data->bus_id = of_alias_get_id(np, "eth");
>>>>
>>>> No, you cannot do like this. Aliases are board specific and are based
>>>> on labeling on the board.
>>>
>>> So if I understood this correctly, I need to move alias in the board
>>> specific DTS file
>>
>> This part: yes
>>
>>> and I can use this, because we have to handle rx-clock-skew differently for
>> the two instances in the FSD platform.
>>
>> Not really. Do you expect it to work correctly if given EQoS instance receives
>> different alias, e.g. 5?
>>
>>> Another approach we took in v1, by specifying the value to be programmed
>> in rx-clock-skew property itself, but it seems it is not a preferred approach.
>>> I can see that in drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>> +436 common code is already using this API and getting alias id, so I can
>> probably use the same rather getting same again here, but I have to specify
>> alias in DTS file.
>>
>> Getting alias ID is okay in general. It is used to provide user-visible ID of the
>> devices (see mmc). Using such alias to configure hardware is abuse of the
>> alias, because of the reasons I said - how is it supposed to work if alias is 5
>> (this is perfectly valid alias)?
>>
>> I suspect that all this is to substitute missing abstractions, like clocks, phys or
>> resets...
>
> Will avoid using the API to get alias id to configure the HW. Will share the new implementation in v4.

That was August 2023, almost year ago.

Whatever you plan, expect having same questions in the discussion
because we forgot everything said that year ago...

Best regards,
Krzysztof